1 //===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass rewrites Rd to x0 for instrs whose return values are unused. 10 // 11 //===---------------------------------------------------------------------===// 12 13 #include "RISCV.h" 14 #include "RISCVInstrInfo.h" 15 #include "RISCVSubtarget.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/CodeGen/MachineFunctionPass.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 20 using namespace llvm; 21 #define DEBUG_TYPE "riscv-dead-defs" 22 #define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions" 23 24 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced"); 25 26 namespace { 27 class RISCVDeadRegisterDefinitions : public MachineFunctionPass { 28 public: 29 static char ID; 30 31 RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {} 32 bool runOnMachineFunction(MachineFunction &MF) override; 33 void getAnalysisUsage(AnalysisUsage &AU) const override { 34 AU.setPreservesCFG(); 35 MachineFunctionPass::getAnalysisUsage(AU); 36 } 37 38 StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; } 39 }; 40 } // end anonymous namespace 41 42 char RISCVDeadRegisterDefinitions::ID = 0; 43 INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE, 44 RISCV_DEAD_REG_DEF_NAME, false, false) 45 46 FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() { 47 return new RISCVDeadRegisterDefinitions(); 48 } 49 50 bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { 51 if (skipFunction(MF.getFunction())) 52 return false; 53 54 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 55 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); 56 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 57 LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n"); 58 59 bool MadeChange = false; 60 for (MachineBasicBlock &MBB : MF) { 61 for (MachineInstr &MI : MBB) { 62 // We only handle non-computational instructions since some NOP encodings 63 // are reserved for HINT instructions. 64 const MCInstrDesc &Desc = MI.getDesc(); 65 if (!Desc.mayLoad() && !Desc.mayStore() && 66 !Desc.hasUnmodeledSideEffects()) 67 continue; 68 // For PseudoVSETVLIX0, Rd = X0 has special meaning. 69 if (MI.getOpcode() == RISCV::PseudoVSETVLIX0) 70 continue; 71 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { 72 MachineOperand &MO = MI.getOperand(I); 73 if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber()) 74 continue; 75 // Be careful not to change the register if it's a tied operand. 76 if (MI.isRegTiedToUseOperand(I)) { 77 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); 78 continue; 79 } 80 // We should not have any relevant physreg defs that are replacable by 81 // zero before register allocation. So we just check for dead vreg defs. 82 Register Reg = MO.getReg(); 83 if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg))) 84 continue; 85 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; 86 MI.print(dbgs())); 87 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); 88 if (!(RC && RC->contains(RISCV::X0))) { 89 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 90 continue; 91 } 92 MO.setReg(RISCV::X0); 93 MO.setIsDead(); 94 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "; 95 MI.print(dbgs())); 96 ++NumDeadDefsReplaced; 97 MadeChange = true; 98 } 99 } 100 } 101 102 return MadeChange; 103 } 104