1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014 IBM Corporation 3 * Copyright(c) 2022 StarFive 4 * Copyright(c) 2022 SiFive 5 * Copyright(c) 2022 Semihalf 6 */ 7 8 #ifndef RTE_CPUFLAGS_RISCV_H 9 #define RTE_CPUFLAGS_RISCV_H 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** 16 * Enumeration of all CPU features supported 17 */ 18 enum rte_cpu_flag_t { 19 RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */ 20 RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */ 21 RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */ 22 RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */ 23 RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */ 24 RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */ 25 RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */ 26 RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */ 27 RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */ 28 RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */ 29 RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */ 30 RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */ 31 RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */ 32 RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */ 33 RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */ 34 RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */ 35 RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */ 36 RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */ 37 RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */ 38 RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */ 39 RTE_CPUFLAG_RISCV_ISA_U, /* User mode */ 40 RTE_CPUFLAG_RISCV_ISA_V, /* Vector */ 41 RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */ 42 RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */ 43 RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */ 44 RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */ 45 /* The last item */ 46 RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ 47 }; 48 49 #include "generic/rte_cpuflags.h" 50 51 #ifdef __cplusplus 52 } 53 #endif 54 55 #endif /* RTE_CPUFLAGS_RISCV_H */ 56