1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014 IBM Corporation 3 * Copyright(c) 2022 StarFive 4 * Copyright(c) 2022 SiFive 5 * Copyright(c) 2022 Semihalf 6 */ 7 8 #ifndef RTE_CPUFLAGS_RISCV_H 9 #define RTE_CPUFLAGS_RISCV_H 10 11 /** 12 * Enumeration of all CPU features supported 13 */ 14 enum rte_cpu_flag_t { 15 RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */ 16 RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */ 17 RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */ 18 RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */ 19 RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */ 20 RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */ 21 RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */ 22 RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */ 23 RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */ 24 RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */ 25 RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */ 26 RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */ 27 RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */ 28 RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */ 29 RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */ 30 RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */ 31 RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */ 32 RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */ 33 RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */ 34 RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */ 35 RTE_CPUFLAG_RISCV_ISA_U, /* User mode */ 36 RTE_CPUFLAG_RISCV_ISA_V, /* Vector */ 37 RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */ 38 RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */ 39 RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */ 40 RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */ 41 }; 42 43 #include "generic/rte_cpuflags.h" 44 45 #endif /* RTE_CPUFLAGS_RISCV_H */ 46