1*f22e705eSMichal Mazurek /* SPDX-License-Identifier: BSD-3-Clause 2*f22e705eSMichal Mazurek * Copyright(c) 2014 IBM Corporation 3*f22e705eSMichal Mazurek * Copyright(c) 2022 StarFive 4*f22e705eSMichal Mazurek * Copyright(c) 2022 SiFive 5*f22e705eSMichal Mazurek * Copyright(c) 2022 Semihalf 6*f22e705eSMichal Mazurek */ 7*f22e705eSMichal Mazurek 8*f22e705eSMichal Mazurek #ifndef RTE_CPUFLAGS_RISCV_H 9*f22e705eSMichal Mazurek #define RTE_CPUFLAGS_RISCV_H 10*f22e705eSMichal Mazurek 11*f22e705eSMichal Mazurek /** 12*f22e705eSMichal Mazurek * Enumeration of all CPU features supported 13*f22e705eSMichal Mazurek */ 14*f22e705eSMichal Mazurek enum rte_cpu_flag_t { 15*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */ 16*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */ 17*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */ 18*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */ 19*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */ 20*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */ 21*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */ 22*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */ 23*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */ 24*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */ 25*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */ 26*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */ 27*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */ 28*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */ 29*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */ 30*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */ 31*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */ 32*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */ 33*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */ 34*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */ 35*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_U, /* User mode */ 36*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_V, /* Vector */ 37*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */ 38*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */ 39*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */ 40*f22e705eSMichal Mazurek RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */ 41*f22e705eSMichal Mazurek }; 42*f22e705eSMichal Mazurek 43*f22e705eSMichal Mazurek #include "generic/rte_cpuflags.h" 44*f22e705eSMichal Mazurek 45*f22e705eSMichal Mazurek #endif /* RTE_CPUFLAGS_RISCV_H */ 46