1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2022 StarFive 3 * Copyright(c) 2022 SiFive 4 * Copyright(c) 2022 Semihalf 5 * All rights reserved. 6 */ 7 8 #ifndef RTE_ATOMIC_RISCV_H 9 #define RTE_ATOMIC_RISCV_H 10 11 #ifndef RTE_FORCE_INTRINSICS 12 # error Platform must be built with RTE_FORCE_INTRINSICS 13 #endif 14 15 #include <stdint.h> 16 #include <rte_common.h> 17 #include <rte_config.h> 18 #include "generic/rte_atomic.h" 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #define rte_mb() asm volatile("fence rw, rw" : : : "memory") 25 26 #define rte_wmb() asm volatile("fence w, w" : : : "memory") 27 28 #define rte_rmb() asm volatile("fence r, r" : : : "memory") 29 30 #define rte_smp_mb() rte_mb() 31 32 #define rte_smp_wmb() rte_wmb() 33 34 #define rte_smp_rmb() rte_rmb() 35 36 #define rte_io_mb() asm volatile("fence iorw, iorw" : : : "memory") 37 38 #define rte_io_wmb() asm volatile("fence orw, ow" : : : "memory") 39 40 #define rte_io_rmb() asm volatile("fence ir, ir" : : : "memory") 41 42 static __rte_always_inline void 43 rte_atomic_thread_fence(rte_memory_order memorder) 44 { 45 __rte_atomic_thread_fence(memorder); 46 } 47 48 #ifdef __cplusplus 49 } 50 #endif 51 52 #endif /* RTE_ATOMIC_RISCV_H */ 53