1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) Cavium, Inc. 2015. 3 * Copyright(c) 2015 RehiveTech. All rights reserved. 4 */ 5 6 #include "rte_cpuflags.h" 7 8 #include <elf.h> 9 #include <fcntl.h> 10 #include <assert.h> 11 #include <unistd.h> 12 #include <string.h> 13 14 #ifndef AT_HWCAP 15 #define AT_HWCAP 16 16 #endif 17 18 #ifndef AT_HWCAP2 19 #define AT_HWCAP2 26 20 #endif 21 22 #ifndef AT_PLATFORM 23 #define AT_PLATFORM 15 24 #endif 25 26 enum cpu_register_t { 27 REG_NONE = 0, 28 REG_HWCAP, 29 REG_HWCAP2, 30 REG_PLATFORM, 31 REG_MAX 32 }; 33 34 typedef uint32_t hwcap_registers_t[REG_MAX]; 35 36 /** 37 * Struct to hold a processor feature entry 38 */ 39 struct feature_entry { 40 uint32_t reg; 41 uint32_t bit; 42 #define CPU_FLAG_NAME_MAX_LEN 64 43 char name[CPU_FLAG_NAME_MAX_LEN]; 44 }; 45 46 #define FEAT_DEF(name, reg, bit) \ 47 [RTE_CPUFLAG_##name] = {reg, bit, #name}, 48 49 #ifdef RTE_ARCH_ARMv7 50 #define PLATFORM_STR "v7l" 51 52 const struct feature_entry rte_cpu_feature_table[] = { 53 FEAT_DEF(SWP, REG_HWCAP, 0) 54 FEAT_DEF(HALF, REG_HWCAP, 1) 55 FEAT_DEF(THUMB, REG_HWCAP, 2) 56 FEAT_DEF(A26BIT, REG_HWCAP, 3) 57 FEAT_DEF(FAST_MULT, REG_HWCAP, 4) 58 FEAT_DEF(FPA, REG_HWCAP, 5) 59 FEAT_DEF(VFP, REG_HWCAP, 6) 60 FEAT_DEF(EDSP, REG_HWCAP, 7) 61 FEAT_DEF(JAVA, REG_HWCAP, 8) 62 FEAT_DEF(IWMMXT, REG_HWCAP, 9) 63 FEAT_DEF(CRUNCH, REG_HWCAP, 10) 64 FEAT_DEF(THUMBEE, REG_HWCAP, 11) 65 FEAT_DEF(NEON, REG_HWCAP, 12) 66 FEAT_DEF(VFPv3, REG_HWCAP, 13) 67 FEAT_DEF(VFPv3D16, REG_HWCAP, 14) 68 FEAT_DEF(TLS, REG_HWCAP, 15) 69 FEAT_DEF(VFPv4, REG_HWCAP, 16) 70 FEAT_DEF(IDIVA, REG_HWCAP, 17) 71 FEAT_DEF(IDIVT, REG_HWCAP, 18) 72 FEAT_DEF(VFPD32, REG_HWCAP, 19) 73 FEAT_DEF(LPAE, REG_HWCAP, 20) 74 FEAT_DEF(EVTSTRM, REG_HWCAP, 21) 75 FEAT_DEF(AES, REG_HWCAP2, 0) 76 FEAT_DEF(PMULL, REG_HWCAP2, 1) 77 FEAT_DEF(SHA1, REG_HWCAP2, 2) 78 FEAT_DEF(SHA2, REG_HWCAP2, 3) 79 FEAT_DEF(CRC32, REG_HWCAP2, 4) 80 FEAT_DEF(V7L, REG_PLATFORM, 0) 81 }; 82 83 #elif defined RTE_ARCH_ARM64 84 #define PLATFORM_STR "aarch64" 85 86 const struct feature_entry rte_cpu_feature_table[] = { 87 FEAT_DEF(FP, REG_HWCAP, 0) 88 FEAT_DEF(NEON, REG_HWCAP, 1) 89 FEAT_DEF(EVTSTRM, REG_HWCAP, 2) 90 FEAT_DEF(AES, REG_HWCAP, 3) 91 FEAT_DEF(PMULL, REG_HWCAP, 4) 92 FEAT_DEF(SHA1, REG_HWCAP, 5) 93 FEAT_DEF(SHA2, REG_HWCAP, 6) 94 FEAT_DEF(CRC32, REG_HWCAP, 7) 95 FEAT_DEF(ATOMICS, REG_HWCAP, 8) 96 FEAT_DEF(SVE, REG_HWCAP, 22) 97 FEAT_DEF(SVE2, REG_HWCAP2, 1) 98 FEAT_DEF(SVEAES, REG_HWCAP2, 2) 99 FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) 100 FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) 101 FEAT_DEF(SVESHA3, REG_HWCAP2, 5) 102 FEAT_DEF(SVESM4, REG_HWCAP2, 6) 103 FEAT_DEF(FLAGM2, REG_HWCAP2, 7) 104 FEAT_DEF(FRINT, REG_HWCAP2, 8) 105 FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) 106 FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) 107 FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) 108 FEAT_DEF(SVEBF16, REG_HWCAP2, 12) 109 FEAT_DEF(AARCH64, REG_PLATFORM, 0) 110 }; 111 #endif /* RTE_ARCH */ 112 113 /* 114 * Read AUXV software register and get cpu features for ARM 115 */ 116 static void 117 rte_cpu_get_features(hwcap_registers_t out) 118 { 119 out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP); 120 out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2); 121 if (!rte_cpu_strcmp_auxval(AT_PLATFORM, PLATFORM_STR)) 122 out[REG_PLATFORM] = 0x0001; 123 } 124 125 /* 126 * Checks if a particular flag is available on current machine. 127 */ 128 int 129 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) 130 { 131 const struct feature_entry *feat; 132 hwcap_registers_t regs = {0}; 133 134 if (feature >= RTE_CPUFLAG_NUMFLAGS) 135 return -ENOENT; 136 137 feat = &rte_cpu_feature_table[feature]; 138 if (feat->reg == REG_NONE) 139 return -EFAULT; 140 141 rte_cpu_get_features(regs); 142 return (regs[feat->reg] >> feat->bit) & 1; 143 } 144 145 const char * 146 rte_cpu_get_flag_name(enum rte_cpu_flag_t feature) 147 { 148 if (feature >= RTE_CPUFLAG_NUMFLAGS) 149 return NULL; 150 return rte_cpu_feature_table[feature].name; 151 } 152 153 void 154 rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) 155 { 156 memset(intrinsics, 0, sizeof(*intrinsics)); 157 } 158