xref: /dpdk/lib/eal/arm/rte_cpuflags.c (revision 2f1a90f0455b4920df3a767ab5d9be37dcbf0d12)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright (C) Cavium, Inc. 2015.
3  * Copyright(c) 2015 RehiveTech. All rights reserved.
4  */
5 
6 #include "rte_cpuflags.h"
7 
8 #include <elf.h>
9 #include <fcntl.h>
10 #include <assert.h>
11 #include <unistd.h>
12 #include <string.h>
13 
14 #ifndef AT_HWCAP
15 #define AT_HWCAP 16
16 #endif
17 
18 #ifndef AT_HWCAP2
19 #define AT_HWCAP2 26
20 #endif
21 
22 #ifndef AT_PLATFORM
23 #define AT_PLATFORM 15
24 #endif
25 
26 enum cpu_register_t {
27 	REG_NONE = 0,
28 	REG_HWCAP,
29 	REG_HWCAP2,
30 	REG_PLATFORM,
31 	REG_MAX
32 };
33 
34 typedef uint32_t hwcap_registers_t[REG_MAX];
35 
36 /**
37  * Struct to hold a processor feature entry
38  */
39 struct feature_entry {
40 	uint32_t reg;
41 	uint32_t bit;
42 #define CPU_FLAG_NAME_MAX_LEN 64
43 	char name[CPU_FLAG_NAME_MAX_LEN];
44 };
45 
46 #define FEAT_DEF(name, reg, bit) \
47 	[RTE_CPUFLAG_##name] = {reg, bit, #name},
48 
49 #ifdef RTE_ARCH_32
50 #ifdef RTE_ARCH_ARMv7
51 #define PLATFORM_STR "v7l"
52 #elif defined RTE_ARCH_ARMv8_AARCH32
53 #define PLATFORM_STR "v8l"
54 #endif
55 typedef Elf32_auxv_t _Elfx_auxv_t;
56 
57 const struct feature_entry rte_cpu_feature_table[] = {
58 	FEAT_DEF(SWP,       REG_HWCAP,    0)
59 	FEAT_DEF(HALF,      REG_HWCAP,    1)
60 	FEAT_DEF(THUMB,     REG_HWCAP,    2)
61 	FEAT_DEF(A26BIT,    REG_HWCAP,    3)
62 	FEAT_DEF(FAST_MULT, REG_HWCAP,    4)
63 	FEAT_DEF(FPA,       REG_HWCAP,    5)
64 	FEAT_DEF(VFP,       REG_HWCAP,    6)
65 	FEAT_DEF(EDSP,      REG_HWCAP,    7)
66 	FEAT_DEF(JAVA,      REG_HWCAP,    8)
67 	FEAT_DEF(IWMMXT,    REG_HWCAP,    9)
68 	FEAT_DEF(CRUNCH,    REG_HWCAP,   10)
69 	FEAT_DEF(THUMBEE,   REG_HWCAP,   11)
70 	FEAT_DEF(NEON,      REG_HWCAP,   12)
71 	FEAT_DEF(VFPv3,     REG_HWCAP,   13)
72 	FEAT_DEF(VFPv3D16,  REG_HWCAP,   14)
73 	FEAT_DEF(TLS,       REG_HWCAP,   15)
74 	FEAT_DEF(VFPv4,     REG_HWCAP,   16)
75 	FEAT_DEF(IDIVA,     REG_HWCAP,   17)
76 	FEAT_DEF(IDIVT,     REG_HWCAP,   18)
77 	FEAT_DEF(VFPD32,    REG_HWCAP,   19)
78 	FEAT_DEF(LPAE,      REG_HWCAP,   20)
79 	FEAT_DEF(EVTSTRM,   REG_HWCAP,   21)
80 	FEAT_DEF(AES,       REG_HWCAP2,   0)
81 	FEAT_DEF(PMULL,     REG_HWCAP2,   1)
82 	FEAT_DEF(SHA1,      REG_HWCAP2,   2)
83 	FEAT_DEF(SHA2,      REG_HWCAP2,   3)
84 	FEAT_DEF(CRC32,     REG_HWCAP2,   4)
85 	#ifdef RTE_ARCH_ARMv7
86 	FEAT_DEF(V7L,       REG_PLATFORM, 0)
87 	#elif defined RTE_ARCH_ARMv8_AARCH32
88 	FEAT_DEF(V8L,       REG_PLATFORM, 0)
89 	#endif
90 };
91 
92 #elif defined RTE_ARCH_64
93 #define PLATFORM_STR "aarch64"
94 
95 const struct feature_entry rte_cpu_feature_table[] = {
96 	FEAT_DEF(FP,		REG_HWCAP,    0)
97 	FEAT_DEF(NEON,		REG_HWCAP,    1)
98 	FEAT_DEF(EVTSTRM,	REG_HWCAP,    2)
99 	FEAT_DEF(AES,		REG_HWCAP,    3)
100 	FEAT_DEF(PMULL,		REG_HWCAP,    4)
101 	FEAT_DEF(SHA1,		REG_HWCAP,    5)
102 	FEAT_DEF(SHA2,		REG_HWCAP,    6)
103 	FEAT_DEF(CRC32,		REG_HWCAP,    7)
104 	FEAT_DEF(ATOMICS,	REG_HWCAP,    8)
105 	FEAT_DEF(SVE,		REG_HWCAP,    22)
106 	FEAT_DEF(SVE2,		REG_HWCAP2,   1)
107 	FEAT_DEF(SVEAES,	REG_HWCAP2,   2)
108 	FEAT_DEF(SVEPMULL,	REG_HWCAP2,   3)
109 	FEAT_DEF(SVEBITPERM,	REG_HWCAP2,   4)
110 	FEAT_DEF(SVESHA3,	REG_HWCAP2,   5)
111 	FEAT_DEF(SVESM4,	REG_HWCAP2,   6)
112 	FEAT_DEF(FLAGM2,	REG_HWCAP2,   7)
113 	FEAT_DEF(FRINT,		REG_HWCAP2,   8)
114 	FEAT_DEF(SVEI8MM,	REG_HWCAP2,   9)
115 	FEAT_DEF(SVEF32MM,	REG_HWCAP2,   10)
116 	FEAT_DEF(SVEF64MM,	REG_HWCAP2,   11)
117 	FEAT_DEF(SVEBF16,	REG_HWCAP2,   12)
118 	FEAT_DEF(WFXT,		REG_HWCAP2,   31)
119 	FEAT_DEF(AARCH64,	REG_PLATFORM,  0)
120 };
121 #endif /* RTE_ARCH */
122 
123 /*
124  * Read AUXV software register and get cpu features for ARM
125  */
126 static void
127 rte_cpu_get_features(hwcap_registers_t out)
128 {
129 	out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
130 	out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
131 	if (!rte_cpu_strcmp_auxval(AT_PLATFORM, PLATFORM_STR))
132 		out[REG_PLATFORM] = 0x0001;
133 }
134 
135 /*
136  * Checks if a particular flag is available on current machine.
137  */
138 int
139 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
140 {
141 	const struct feature_entry *feat;
142 	hwcap_registers_t regs = {0};
143 
144 	if ((unsigned int)feature >= RTE_DIM(rte_cpu_feature_table))
145 		return -ENOENT;
146 
147 	feat = &rte_cpu_feature_table[feature];
148 	if (feat->reg == REG_NONE)
149 		return -EFAULT;
150 
151 	rte_cpu_get_features(regs);
152 	return (regs[feat->reg] >> feat->bit) & 1;
153 }
154 
155 const char *
156 rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
157 {
158 	if ((unsigned int)feature >= RTE_DIM(rte_cpu_feature_table))
159 		return NULL;
160 	return rte_cpu_feature_table[feature].name;
161 }
162 
163 void
164 rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
165 {
166 	memset(intrinsics, 0, sizeof(*intrinsics));
167 #ifdef RTE_ARCH_64
168 	intrinsics->power_monitor = 1;
169 #endif /* RTE_ARCH_64 */
170 }
171