1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015 Cavium, Inc 3 */ 4 5 #ifndef _RTE_CPUFLAGS_ARM64_H_ 6 #define _RTE_CPUFLAGS_ARM64_H_ 7 8 /** 9 * Enumeration of all CPU features supported 10 */ 11 enum rte_cpu_flag_t { 12 /* Floating point capability */ 13 RTE_CPUFLAG_FP = 0, 14 15 /* Arm Neon extension */ 16 RTE_CPUFLAG_NEON, 17 18 /* Generic timer event stream */ 19 RTE_CPUFLAG_EVTSTRM, 20 21 /* AES instructions */ 22 RTE_CPUFLAG_AES, 23 24 /* Polynomial multiply long instruction */ 25 RTE_CPUFLAG_PMULL, 26 27 /* SHA1 instructions */ 28 RTE_CPUFLAG_SHA1, 29 30 /* SHA2 instructions */ 31 RTE_CPUFLAG_SHA2, 32 33 /* CRC32 instruction */ 34 RTE_CPUFLAG_CRC32, 35 36 /* 37 * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, 38 * CASP, and SWP instructions 39 */ 40 RTE_CPUFLAG_ATOMICS, 41 42 /* Arm SVE extension */ 43 RTE_CPUFLAG_SVE, 44 45 /* Arm SVE2 extension */ 46 RTE_CPUFLAG_SVE2, 47 48 /* SVE-AES instructions */ 49 RTE_CPUFLAG_SVEAES, 50 51 /* SVE-PMULL instruction */ 52 RTE_CPUFLAG_SVEPMULL, 53 54 /* SVE bit permute instructions */ 55 RTE_CPUFLAG_SVEBITPERM, 56 57 /* SVE-SHA3 instructions */ 58 RTE_CPUFLAG_SVESHA3, 59 60 /* SVE-SM4 instructions */ 61 RTE_CPUFLAG_SVESM4, 62 63 /* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */ 64 RTE_CPUFLAG_FLAGM2, 65 66 /* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */ 67 RTE_CPUFLAG_FRINT, 68 69 /* SVE Int8 matrix multiplication instructions */ 70 RTE_CPUFLAG_SVEI8MM, 71 72 /* SVE FP32 floating-point matrix multiplication instructions */ 73 RTE_CPUFLAG_SVEF32MM, 74 75 /* SVE FP64 floating-point matrix multiplication instructions */ 76 RTE_CPUFLAG_SVEF64MM, 77 78 /* SVE BFloat16 instructions */ 79 RTE_CPUFLAG_SVEBF16, 80 81 /* 64 bit execution state of the Arm architecture */ 82 RTE_CPUFLAG_AARCH64, 83 84 /* WFET and WFIT instructions */ 85 RTE_CPUFLAG_WFXT, 86 }; 87 88 #include "generic/rte_cpuflags.h" 89 90 #endif /* _RTE_CPUFLAGS_ARM64_H_ */ 91