xref: /dpdk/examples/qos_sched/app_thread.c (revision d827c2695e564a378c59d24ec116bf022ca3feda)
1de3cfa2cSIntel /*-
2de3cfa2cSIntel  *   BSD LICENSE
3de3cfa2cSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5de3cfa2cSIntel  *   All rights reserved.
6de3cfa2cSIntel  *
7de3cfa2cSIntel  *   Redistribution and use in source and binary forms, with or without
8de3cfa2cSIntel  *   modification, are permitted provided that the following conditions
9de3cfa2cSIntel  *   are met:
10de3cfa2cSIntel  *
11de3cfa2cSIntel  *     * Redistributions of source code must retain the above copyright
12de3cfa2cSIntel  *       notice, this list of conditions and the following disclaimer.
13de3cfa2cSIntel  *     * Redistributions in binary form must reproduce the above copyright
14de3cfa2cSIntel  *       notice, this list of conditions and the following disclaimer in
15de3cfa2cSIntel  *       the documentation and/or other materials provided with the
16de3cfa2cSIntel  *       distribution.
17de3cfa2cSIntel  *     * Neither the name of Intel Corporation nor the names of its
18de3cfa2cSIntel  *       contributors may be used to endorse or promote products derived
19de3cfa2cSIntel  *       from this software without specific prior written permission.
20de3cfa2cSIntel  *
21de3cfa2cSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22de3cfa2cSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23de3cfa2cSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24de3cfa2cSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25de3cfa2cSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26de3cfa2cSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27de3cfa2cSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28de3cfa2cSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29de3cfa2cSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30de3cfa2cSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31de3cfa2cSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32de3cfa2cSIntel  */
33de3cfa2cSIntel 
34de3cfa2cSIntel #include <stdint.h>
35de3cfa2cSIntel 
36de3cfa2cSIntel #include <rte_log.h>
37de3cfa2cSIntel #include <rte_mbuf.h>
38de3cfa2cSIntel #include <rte_malloc.h>
39de3cfa2cSIntel #include <rte_cycles.h>
40de3cfa2cSIntel #include <rte_ethdev.h>
41de3cfa2cSIntel #include <rte_memcpy.h>
42de3cfa2cSIntel #include <rte_byteorder.h>
43de3cfa2cSIntel #include <rte_branch_prediction.h>
44de3cfa2cSIntel #include <rte_sched.h>
45de3cfa2cSIntel 
46de3cfa2cSIntel #include "main.h"
47de3cfa2cSIntel 
48de3cfa2cSIntel /*
49de3cfa2cSIntel  * QoS parameters are encoded as follows:
50de3cfa2cSIntel  *		Outer VLAN ID defines subport
51de3cfa2cSIntel  *		Inner VLAN ID defines pipe
52de3cfa2cSIntel  *		Destination IP 0.0.XXX.0 defines traffic class
53de3cfa2cSIntel  *		Destination IP host (0.0.0.XXX) defines queue
54de3cfa2cSIntel  * Values below define offset to each field from start of frame
55de3cfa2cSIntel  */
56de3cfa2cSIntel #define SUBPORT_OFFSET	7
57de3cfa2cSIntel #define PIPE_OFFSET		9
58de3cfa2cSIntel #define TC_OFFSET		20
59de3cfa2cSIntel #define QUEUE_OFFSET	20
60de3cfa2cSIntel #define COLOR_OFFSET	19
61de3cfa2cSIntel 
62de3cfa2cSIntel static inline int
63de3cfa2cSIntel get_pkt_sched(struct rte_mbuf *m, uint32_t *subport, uint32_t *pipe,
64de3cfa2cSIntel 			uint32_t *traffic_class, uint32_t *queue, uint32_t *color)
65de3cfa2cSIntel {
66de3cfa2cSIntel 	uint16_t *pdata = rte_pktmbuf_mtod(m, uint16_t *);
67de3cfa2cSIntel 
68de3cfa2cSIntel 	*subport = (rte_be_to_cpu_16(pdata[SUBPORT_OFFSET]) & 0x0FFF) &
69de3cfa2cSIntel 			(port_params.n_subports_per_port - 1); /* Outer VLAN ID*/
70de3cfa2cSIntel 	*pipe = (rte_be_to_cpu_16(pdata[PIPE_OFFSET]) & 0x0FFF) &
71de3cfa2cSIntel 			(port_params.n_pipes_per_subport - 1); /* Inner VLAN ID */
72de3cfa2cSIntel 	*traffic_class = (pdata[QUEUE_OFFSET] & 0x0F) &
73de3cfa2cSIntel 			(RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE - 1); /* Destination IP */
74de3cfa2cSIntel 	*queue = ((pdata[QUEUE_OFFSET] >> 8) & 0x0F) &
75de3cfa2cSIntel 			(RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS - 1) ; /* Destination IP */
76de3cfa2cSIntel 	*color = pdata[COLOR_OFFSET] & 0x03; 	/* Destination IP */
77de3cfa2cSIntel 
78de3cfa2cSIntel 	return 0;
79de3cfa2cSIntel }
80de3cfa2cSIntel 
81de3cfa2cSIntel void
82de3cfa2cSIntel app_rx_thread(struct thread_conf **confs)
83de3cfa2cSIntel {
84de3cfa2cSIntel 	uint32_t i, nb_rx;
85de3cfa2cSIntel 	struct rte_mbuf *rx_mbufs[burst_conf.rx_burst] __rte_cache_aligned;
86de3cfa2cSIntel 	struct thread_conf *conf;
87de3cfa2cSIntel 	int conf_idx = 0;
88de3cfa2cSIntel 
89de3cfa2cSIntel 	uint32_t subport;
90de3cfa2cSIntel 	uint32_t pipe;
91de3cfa2cSIntel 	uint32_t traffic_class;
92de3cfa2cSIntel 	uint32_t queue;
93de3cfa2cSIntel 	uint32_t color;
94de3cfa2cSIntel 
95de3cfa2cSIntel 	while ((conf = confs[conf_idx])) {
96de3cfa2cSIntel 		nb_rx = rte_eth_rx_burst(conf->rx_port, conf->rx_queue, rx_mbufs,
97de3cfa2cSIntel 				burst_conf.rx_burst);
98de3cfa2cSIntel 
99de3cfa2cSIntel 		if (likely(nb_rx != 0)) {
100de3cfa2cSIntel 			APP_STATS_ADD(conf->stat.nb_rx, nb_rx);
101de3cfa2cSIntel 
102de3cfa2cSIntel 			for(i = 0; i < nb_rx; i++) {
103de3cfa2cSIntel 				get_pkt_sched(rx_mbufs[i],
104de3cfa2cSIntel 						&subport, &pipe, &traffic_class, &queue, &color);
105de3cfa2cSIntel 				rte_sched_port_pkt_write(rx_mbufs[i], subport, pipe,
106de3cfa2cSIntel 						traffic_class, queue, (enum rte_meter_color) color);
107de3cfa2cSIntel 			}
108de3cfa2cSIntel 
109de3cfa2cSIntel 			if (unlikely(rte_ring_sp_enqueue_bulk(conf->rx_ring,
110de3cfa2cSIntel 								(void **)rx_mbufs, nb_rx) != 0)) {
111de3cfa2cSIntel 				for(i = 0; i < nb_rx; i++) {
112de3cfa2cSIntel 					rte_pktmbuf_free(rx_mbufs[i]);
113de3cfa2cSIntel 
114de3cfa2cSIntel 					APP_STATS_ADD(conf->stat.nb_drop, 1);
115de3cfa2cSIntel 				}
116de3cfa2cSIntel 			}
117de3cfa2cSIntel 		}
118de3cfa2cSIntel 		conf_idx++;
119de3cfa2cSIntel 		if (confs[conf_idx] == NULL)
120de3cfa2cSIntel 			conf_idx = 0;
121de3cfa2cSIntel 	}
122de3cfa2cSIntel }
123de3cfa2cSIntel 
124de3cfa2cSIntel 
125de3cfa2cSIntel 
126de3cfa2cSIntel /* Send the packet to an output interface
127de3cfa2cSIntel  * For performance reason function returns number of packets dropped, not sent,
128de3cfa2cSIntel  * so 0 means that all packets were sent successfully
129de3cfa2cSIntel  */
130de3cfa2cSIntel 
131de3cfa2cSIntel static inline void
132de3cfa2cSIntel app_send_burst(struct thread_conf *qconf)
133de3cfa2cSIntel {
134de3cfa2cSIntel 	struct rte_mbuf **mbufs;
135de3cfa2cSIntel 	uint32_t n, ret;
136de3cfa2cSIntel 
137de3cfa2cSIntel 	mbufs = (struct rte_mbuf **)qconf->m_table;
138de3cfa2cSIntel 	n = qconf->n_mbufs;
139de3cfa2cSIntel 
140de3cfa2cSIntel 	do {
141de3cfa2cSIntel 		ret = rte_eth_tx_burst(qconf->tx_port, qconf->tx_queue, mbufs, (uint16_t)n);
142*d827c269SYong Liu 		/* we cannot drop the packets, so re-send */
143de3cfa2cSIntel 		/* update number of packets to be sent */
144de3cfa2cSIntel 		n -= ret;
145de3cfa2cSIntel 		mbufs = (struct rte_mbuf **)&mbufs[ret];
146*d827c269SYong Liu 	} while (n);
147de3cfa2cSIntel }
148de3cfa2cSIntel 
149de3cfa2cSIntel 
150de3cfa2cSIntel /* Send the packet to an output interface */
151de3cfa2cSIntel static void
152de3cfa2cSIntel app_send_packets(struct thread_conf *qconf, struct rte_mbuf **mbufs, uint32_t nb_pkt)
153de3cfa2cSIntel {
154de3cfa2cSIntel 	uint32_t i, len;
155de3cfa2cSIntel 
156de3cfa2cSIntel 	len = qconf->n_mbufs;
157de3cfa2cSIntel 	for(i = 0; i < nb_pkt; i++) {
158de3cfa2cSIntel 		qconf->m_table[len] = mbufs[i];
159de3cfa2cSIntel 		len++;
160de3cfa2cSIntel 		/* enough pkts to be sent */
161de3cfa2cSIntel 		if (unlikely(len == burst_conf.tx_burst)) {
162de3cfa2cSIntel 			qconf->n_mbufs = len;
163de3cfa2cSIntel 			app_send_burst(qconf);
164de3cfa2cSIntel 			len = 0;
165de3cfa2cSIntel 		}
166de3cfa2cSIntel 	}
167de3cfa2cSIntel 
168de3cfa2cSIntel 	qconf->n_mbufs = len;
169de3cfa2cSIntel }
170de3cfa2cSIntel 
171de3cfa2cSIntel void
172de3cfa2cSIntel app_tx_thread(struct thread_conf **confs)
173de3cfa2cSIntel {
174de3cfa2cSIntel 	struct rte_mbuf *mbufs[burst_conf.qos_dequeue];
175de3cfa2cSIntel 	struct thread_conf *conf;
176de3cfa2cSIntel 	int conf_idx = 0;
177de3cfa2cSIntel 	int retval;
178de3cfa2cSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
179de3cfa2cSIntel 
180de3cfa2cSIntel 	while ((conf = confs[conf_idx])) {
181de3cfa2cSIntel 		retval = rte_ring_sc_dequeue_bulk(conf->tx_ring, (void **)mbufs,
182de3cfa2cSIntel 					burst_conf.qos_dequeue);
183de3cfa2cSIntel 		if (likely(retval == 0)) {
184de3cfa2cSIntel 			app_send_packets(conf, mbufs, burst_conf.qos_dequeue);
185de3cfa2cSIntel 
186de3cfa2cSIntel 			conf->counter = 0; /* reset empty read loop counter */
187de3cfa2cSIntel 		}
188de3cfa2cSIntel 
189de3cfa2cSIntel 		conf->counter++;
190de3cfa2cSIntel 
191de3cfa2cSIntel 		/* drain ring and TX queues */
192de3cfa2cSIntel 		if (unlikely(conf->counter > drain_tsc)) {
193de3cfa2cSIntel 			/* now check is there any packets left to be transmitted */
194de3cfa2cSIntel 			if (conf->n_mbufs != 0) {
195de3cfa2cSIntel 				app_send_burst(conf);
196de3cfa2cSIntel 
197de3cfa2cSIntel 				conf->n_mbufs = 0;
198de3cfa2cSIntel 			}
199de3cfa2cSIntel 			conf->counter = 0;
200de3cfa2cSIntel 		}
201de3cfa2cSIntel 
202de3cfa2cSIntel 		conf_idx++;
203de3cfa2cSIntel 		if (confs[conf_idx] == NULL)
204de3cfa2cSIntel 			conf_idx = 0;
205de3cfa2cSIntel 	}
206de3cfa2cSIntel }
207de3cfa2cSIntel 
208de3cfa2cSIntel 
209de3cfa2cSIntel void
210de3cfa2cSIntel app_worker_thread(struct thread_conf **confs)
211de3cfa2cSIntel {
212de3cfa2cSIntel 	struct rte_mbuf *mbufs[burst_conf.ring_burst];
213de3cfa2cSIntel 	struct thread_conf *conf;
214de3cfa2cSIntel 	int conf_idx = 0;
215de3cfa2cSIntel 
216de3cfa2cSIntel 	while ((conf = confs[conf_idx])) {
217de3cfa2cSIntel 		uint32_t nb_pkt;
218de3cfa2cSIntel 		int retval;
219de3cfa2cSIntel 
220de3cfa2cSIntel 		/* Read packet from the ring */
221de3cfa2cSIntel 		retval = rte_ring_sc_dequeue_bulk(conf->rx_ring, (void **)mbufs,
222de3cfa2cSIntel 					burst_conf.ring_burst);
223de3cfa2cSIntel 		if (likely(retval == 0)) {
224de3cfa2cSIntel 			int nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs,
225de3cfa2cSIntel 					burst_conf.ring_burst);
226de3cfa2cSIntel 
227de3cfa2cSIntel 			APP_STATS_ADD(conf->stat.nb_drop, burst_conf.ring_burst - nb_sent);
228de3cfa2cSIntel 			APP_STATS_ADD(conf->stat.nb_rx, burst_conf.ring_burst);
229de3cfa2cSIntel 		}
230de3cfa2cSIntel 
231de3cfa2cSIntel 		nb_pkt = rte_sched_port_dequeue(conf->sched_port, mbufs,
232de3cfa2cSIntel 					burst_conf.qos_dequeue);
233de3cfa2cSIntel 		if (likely(nb_pkt > 0))
234de3cfa2cSIntel 			while (rte_ring_sp_enqueue_bulk(conf->tx_ring, (void **)mbufs, nb_pkt) != 0);
235de3cfa2cSIntel 
236de3cfa2cSIntel 		conf_idx++;
237de3cfa2cSIntel 		if (confs[conf_idx] == NULL)
238de3cfa2cSIntel 			conf_idx = 0;
239de3cfa2cSIntel 	}
240de3cfa2cSIntel }
241de3cfa2cSIntel 
242de3cfa2cSIntel 
243de3cfa2cSIntel void
244de3cfa2cSIntel app_mixed_thread(struct thread_conf **confs)
245de3cfa2cSIntel {
246de3cfa2cSIntel 	struct rte_mbuf *mbufs[burst_conf.ring_burst];
247de3cfa2cSIntel 	struct thread_conf *conf;
248de3cfa2cSIntel 	int conf_idx = 0;
249de3cfa2cSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
250de3cfa2cSIntel 
251de3cfa2cSIntel 	while ((conf = confs[conf_idx])) {
252de3cfa2cSIntel 		uint32_t nb_pkt;
253de3cfa2cSIntel 		int retval;
254de3cfa2cSIntel 
255de3cfa2cSIntel 		/* Read packet from the ring */
256de3cfa2cSIntel 		retval = rte_ring_sc_dequeue_bulk(conf->rx_ring, (void **)mbufs,
257de3cfa2cSIntel 					burst_conf.ring_burst);
258de3cfa2cSIntel 		if (likely(retval == 0)) {
259de3cfa2cSIntel 			int nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs,
260de3cfa2cSIntel 					burst_conf.ring_burst);
261de3cfa2cSIntel 
262de3cfa2cSIntel 			APP_STATS_ADD(conf->stat.nb_drop, burst_conf.ring_burst - nb_sent);
263de3cfa2cSIntel 			APP_STATS_ADD(conf->stat.nb_rx, burst_conf.ring_burst);
264de3cfa2cSIntel 		}
265de3cfa2cSIntel 
266de3cfa2cSIntel 
267de3cfa2cSIntel 		nb_pkt = rte_sched_port_dequeue(conf->sched_port, mbufs,
268de3cfa2cSIntel 					burst_conf.qos_dequeue);
269de3cfa2cSIntel 		if (likely(nb_pkt > 0)) {
270de3cfa2cSIntel 			app_send_packets(conf, mbufs, nb_pkt);
271de3cfa2cSIntel 
272de3cfa2cSIntel 			conf->counter = 0; /* reset empty read loop counter */
273de3cfa2cSIntel 		}
274de3cfa2cSIntel 
275de3cfa2cSIntel 		conf->counter++;
276de3cfa2cSIntel 
277de3cfa2cSIntel 		/* drain ring and TX queues */
278de3cfa2cSIntel 		if (unlikely(conf->counter > drain_tsc)) {
279de3cfa2cSIntel 
280de3cfa2cSIntel 			/* now check is there any packets left to be transmitted */
281de3cfa2cSIntel 			if (conf->n_mbufs != 0) {
282de3cfa2cSIntel 				app_send_burst(conf);
283de3cfa2cSIntel 
284de3cfa2cSIntel 				conf->n_mbufs = 0;
285de3cfa2cSIntel 			}
286de3cfa2cSIntel 			conf->counter = 0;
287de3cfa2cSIntel 		}
288de3cfa2cSIntel 
289de3cfa2cSIntel 		conf_idx++;
290de3cfa2cSIntel 		if (confs[conf_idx] == NULL)
291de3cfa2cSIntel 			conf_idx = 0;
292de3cfa2cSIntel 	}
293de3cfa2cSIntel }
294de3cfa2cSIntel 
295de3cfa2cSIntel 
296