xref: /dpdk/examples/ipv4_multicast/main.c (revision ea0c20ea95fd5d71a10757e6598ac66233ea1495)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #include <stdio.h>
35af75078fSIntel #include <stdlib.h>
36af75078fSIntel #include <stdint.h>
37af75078fSIntel #include <inttypes.h>
38af75078fSIntel #include <sys/types.h>
39af75078fSIntel #include <string.h>
40af75078fSIntel #include <sys/queue.h>
41af75078fSIntel #include <stdarg.h>
42af75078fSIntel #include <errno.h>
43af75078fSIntel #include <getopt.h>
44af75078fSIntel 
45af75078fSIntel #include <rte_common.h>
46af75078fSIntel #include <rte_byteorder.h>
47af75078fSIntel #include <rte_log.h>
48af75078fSIntel #include <rte_memory.h>
49af75078fSIntel #include <rte_memcpy.h>
50af75078fSIntel #include <rte_memzone.h>
51af75078fSIntel #include <rte_eal.h>
52af75078fSIntel #include <rte_per_lcore.h>
53af75078fSIntel #include <rte_launch.h>
54af75078fSIntel #include <rte_atomic.h>
55af75078fSIntel #include <rte_cycles.h>
56af75078fSIntel #include <rte_prefetch.h>
57af75078fSIntel #include <rte_lcore.h>
58af75078fSIntel #include <rte_per_lcore.h>
59af75078fSIntel #include <rte_branch_prediction.h>
60af75078fSIntel #include <rte_interrupts.h>
61af75078fSIntel #include <rte_pci.h>
62af75078fSIntel #include <rte_random.h>
63af75078fSIntel #include <rte_debug.h>
64af75078fSIntel #include <rte_ether.h>
65af75078fSIntel #include <rte_ethdev.h>
66af75078fSIntel #include <rte_ring.h>
67af75078fSIntel #include <rte_mempool.h>
68af75078fSIntel #include <rte_mbuf.h>
69af75078fSIntel #include <rte_malloc.h>
70af75078fSIntel #include <rte_fbk_hash.h>
71af75078fSIntel #include <rte_ip.h>
72af75078fSIntel 
73af75078fSIntel #define RTE_LOGTYPE_IPv4_MULTICAST RTE_LOGTYPE_USER1
74af75078fSIntel 
75af75078fSIntel #define MAX_PORTS 16
76af75078fSIntel 
77af75078fSIntel #define	MCAST_CLONE_PORTS	2
78af75078fSIntel #define	MCAST_CLONE_SEGS	2
79af75078fSIntel 
80*ea0c20eaSOlivier Matz #define	PKT_MBUF_DATA_SIZE	(2048 + RTE_PKTMBUF_HEADROOM)
81af75078fSIntel #define	NB_PKT_MBUF	8192
82af75078fSIntel 
83*ea0c20eaSOlivier Matz #define	HDR_MBUF_DATA_SIZE	(2 * RTE_PKTMBUF_HEADROOM)
84af75078fSIntel #define	NB_HDR_MBUF	(NB_PKT_MBUF * MAX_PORTS)
85af75078fSIntel 
86af75078fSIntel #define	NB_CLONE_MBUF	(NB_PKT_MBUF * MCAST_CLONE_PORTS * MCAST_CLONE_SEGS * 2)
87af75078fSIntel 
88af75078fSIntel /* allow max jumbo frame 9.5 KB */
89af75078fSIntel #define	JUMBO_FRAME_MAX_SIZE	0x2600
90af75078fSIntel 
91af75078fSIntel #define MAX_PKT_BURST 32
925c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
93af75078fSIntel 
94af75078fSIntel /* Configure how many packets ahead to prefetch, when reading packets */
95af75078fSIntel #define PREFETCH_OFFSET	3
96af75078fSIntel 
97af75078fSIntel /*
98af75078fSIntel  * Construct Ethernet multicast address from IPv4 multicast address.
99af75078fSIntel  * Citing RFC 1112, section 6.4:
100af75078fSIntel  * "An IP host group address is mapped to an Ethernet multicast address
101af75078fSIntel  * by placing the low-order 23-bits of the IP address into the low-order
102af75078fSIntel  * 23 bits of the Ethernet multicast address 01-00-5E-00-00-00 (hex)."
103af75078fSIntel  */
104af75078fSIntel #define	ETHER_ADDR_FOR_IPV4_MCAST(x)	\
105af75078fSIntel 	(rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16)
106af75078fSIntel 
107af75078fSIntel /*
108af75078fSIntel  * Configurable number of RX/TX ring descriptors
109af75078fSIntel  */
110af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128
111af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512
112af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
113af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
114af75078fSIntel 
115af75078fSIntel /* ethernet addresses of ports */
116af75078fSIntel static struct ether_addr ports_eth_addr[MAX_PORTS];
117af75078fSIntel 
118af75078fSIntel /* mask of enabled ports */
119af75078fSIntel static uint32_t enabled_port_mask = 0;
120af75078fSIntel 
121af75078fSIntel static uint8_t nb_ports = 0;
122af75078fSIntel 
123af75078fSIntel static int rx_queue_per_lcore = 1;
124af75078fSIntel 
125af75078fSIntel struct mbuf_table {
126af75078fSIntel 	uint16_t len;
127af75078fSIntel 	struct rte_mbuf *m_table[MAX_PKT_BURST];
128af75078fSIntel };
129af75078fSIntel 
130af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16
131af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16
132af75078fSIntel struct lcore_queue_conf {
133af75078fSIntel 	uint64_t tx_tsc;
134af75078fSIntel 	uint16_t n_rx_queue;
135af75078fSIntel 	uint8_t rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
136af75078fSIntel 	uint16_t tx_queue_id[MAX_PORTS];
137af75078fSIntel 	struct mbuf_table tx_mbufs[MAX_PORTS];
138af75078fSIntel } __rte_cache_aligned;
139af75078fSIntel static struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];
140af75078fSIntel 
141af75078fSIntel static const struct rte_eth_conf port_conf = {
142af75078fSIntel 	.rxmode = {
143af75078fSIntel 		.max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE,
144af75078fSIntel 		.split_hdr_size = 0,
145af75078fSIntel 		.header_split   = 0, /**< Header Split disabled */
146af75078fSIntel 		.hw_ip_checksum = 0, /**< IP checksum offload disabled */
147af75078fSIntel 		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
148af75078fSIntel 		.jumbo_frame    = 1, /**< Jumbo Frame Support enabled */
149af75078fSIntel 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
150af75078fSIntel 	},
151af75078fSIntel 	.txmode = {
15232e7aa0bSIntel 		.mq_mode = ETH_MQ_TX_NONE,
153af75078fSIntel 	},
154af75078fSIntel };
155af75078fSIntel 
156af75078fSIntel static struct rte_mempool *packet_pool, *header_pool, *clone_pool;
157af75078fSIntel 
158af75078fSIntel 
159af75078fSIntel /* Multicast */
160af75078fSIntel static struct rte_fbk_hash_params mcast_hash_params = {
161af75078fSIntel 	.name = "MCAST_HASH",
162af75078fSIntel 	.entries = 1024,
163af75078fSIntel 	.entries_per_bucket = 4,
164e60f71ebSIntel 	.socket_id = 0,
165af75078fSIntel 	.hash_func = NULL,
166af75078fSIntel 	.init_val = 0,
167af75078fSIntel };
168af75078fSIntel 
169af75078fSIntel struct rte_fbk_hash_table *mcast_hash = NULL;
170af75078fSIntel 
171af75078fSIntel struct mcast_group_params {
172af75078fSIntel 	uint32_t ip;
173af75078fSIntel 	uint16_t port_mask;
174af75078fSIntel };
175af75078fSIntel 
176af75078fSIntel static struct mcast_group_params mcast_group_table[] = {
177af75078fSIntel 		{IPv4(224,0,0,101), 0x1},
178af75078fSIntel 		{IPv4(224,0,0,102), 0x2},
179af75078fSIntel 		{IPv4(224,0,0,103), 0x3},
180af75078fSIntel 		{IPv4(224,0,0,104), 0x4},
181af75078fSIntel 		{IPv4(224,0,0,105), 0x5},
182af75078fSIntel 		{IPv4(224,0,0,106), 0x6},
183af75078fSIntel 		{IPv4(224,0,0,107), 0x7},
184af75078fSIntel 		{IPv4(224,0,0,108), 0x8},
185af75078fSIntel 		{IPv4(224,0,0,109), 0x9},
186af75078fSIntel 		{IPv4(224,0,0,110), 0xA},
187af75078fSIntel 		{IPv4(224,0,0,111), 0xB},
188af75078fSIntel 		{IPv4(224,0,0,112), 0xC},
189af75078fSIntel 		{IPv4(224,0,0,113), 0xD},
190af75078fSIntel 		{IPv4(224,0,0,114), 0xE},
191af75078fSIntel 		{IPv4(224,0,0,115), 0xF},
192af75078fSIntel };
193af75078fSIntel 
194af75078fSIntel #define N_MCAST_GROUPS \
195af75078fSIntel 	(sizeof (mcast_group_table) / sizeof (mcast_group_table[0]))
196af75078fSIntel 
197af75078fSIntel 
198af75078fSIntel /* Send burst of packets on an output interface */
199af75078fSIntel static void
200af75078fSIntel send_burst(struct lcore_queue_conf *qconf, uint8_t port)
201af75078fSIntel {
202af75078fSIntel 	struct rte_mbuf **m_table;
203af75078fSIntel 	uint16_t n, queueid;
204af75078fSIntel 	int ret;
205af75078fSIntel 
206af75078fSIntel 	queueid = qconf->tx_queue_id[port];
207af75078fSIntel 	m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;
208af75078fSIntel 	n = qconf->tx_mbufs[port].len;
209af75078fSIntel 
210af75078fSIntel 	ret = rte_eth_tx_burst(port, queueid, m_table, n);
211af75078fSIntel 	while (unlikely (ret < n)) {
212af75078fSIntel 		rte_pktmbuf_free(m_table[ret]);
213af75078fSIntel 		ret++;
214af75078fSIntel 	}
215af75078fSIntel 
216af75078fSIntel 	qconf->tx_mbufs[port].len = 0;
217af75078fSIntel }
218af75078fSIntel 
219af75078fSIntel /* Get number of bits set. */
220af75078fSIntel static inline uint32_t
221af75078fSIntel bitcnt(uint32_t v)
222af75078fSIntel {
223af75078fSIntel 	uint32_t n;
224af75078fSIntel 
225af75078fSIntel 	for (n = 0; v != 0; v &= v - 1, n++)
226af75078fSIntel 		;
227af75078fSIntel 
228af75078fSIntel 	return (n);
229af75078fSIntel }
230af75078fSIntel 
231af75078fSIntel /**
232af75078fSIntel  * Create the output multicast packet based on the given input packet.
233af75078fSIntel  * There are two approaches for creating outgoing packet, though both
234af75078fSIntel  * are based on data zero-copy idea, they differ in few details:
235af75078fSIntel  * First one creates a clone of the input packet, e.g - walk though all
236af75078fSIntel  * segments of the input packet, and for each of them create a new packet
237af75078fSIntel  * mbuf and attach that new mbuf to the segment (refer to rte_pktmbuf_clone()
238af75078fSIntel  * for more details). Then new mbuf is allocated for the packet header
239af75078fSIntel  * and is prepended to the 'clone' mbuf.
240af75078fSIntel  * Second approach doesn't make a clone, it just increment refcnt for all
241af75078fSIntel  * input packet segments. Then it allocates new mbuf for the packet header
242af75078fSIntel  * and prepends it to the input packet.
243af75078fSIntel  * Basically first approach reuses only input packet's data, but creates
244af75078fSIntel  * it's own copy of packet's metadata. Second approach reuses both input's
245af75078fSIntel  * packet data and metadata.
246af75078fSIntel  * The advantage of first approach - is that each outgoing packet has it's
247af75078fSIntel  * own copy of metadata, so we can safely modify data pointer of the
248af75078fSIntel  * input packet. That allows us to skip creation if the output packet for
249af75078fSIntel  * the last destination port, but instead modify input packet's header inplace,
250af75078fSIntel  * e.g: for N destination ports we need to invoke mcast_out_pkt (N-1) times.
251af75078fSIntel  * The advantage of second approach - less work for each outgoing packet,
252af75078fSIntel  * e.g: we skip "clone" operation completely. Though it comes with a price -
253af75078fSIntel  * input packet's metadata has to be intact. So for N destination ports we
254af75078fSIntel  * need to invoke mcast_out_pkt N times.
255af75078fSIntel  * So for small number of outgoing ports (and segments in the input packet)
256af75078fSIntel  * first approach will be faster.
257af75078fSIntel  * As number of outgoing ports (and/or input segments) will grow,
258af75078fSIntel  * second way will become more preferable.
259af75078fSIntel  *
260af75078fSIntel  *  @param pkt
261af75078fSIntel  *  Input packet mbuf.
262af75078fSIntel  *  @param use_clone
263af75078fSIntel  *  Control which of the two approaches described above should be used:
264af75078fSIntel  *  - 0 - use second approach:
265af75078fSIntel  *    Don't "clone" input packet.
266af75078fSIntel  *    Prepend new header directly to the input packet
267af75078fSIntel  *  - 1 - use first approach:
268af75078fSIntel  *    Make a "clone" of input packet first.
269af75078fSIntel  *    Prepend new header to the clone of the input packet
270af75078fSIntel  *  @return
271af75078fSIntel  *  - The pointer to the new outgoing packet.
272af75078fSIntel  *  - NULL if operation failed.
273af75078fSIntel  */
274af75078fSIntel static inline struct rte_mbuf *
275af75078fSIntel mcast_out_pkt(struct rte_mbuf *pkt, int use_clone)
276af75078fSIntel {
277af75078fSIntel 	struct rte_mbuf *hdr;
278af75078fSIntel 
279af75078fSIntel 	/* Create new mbuf for the header. */
280af75078fSIntel 	if (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL))
281af75078fSIntel 		return (NULL);
282af75078fSIntel 
283af75078fSIntel 	/* If requested, then make a new clone packet. */
284af75078fSIntel 	if (use_clone != 0 &&
285af75078fSIntel 	    unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) {
286af75078fSIntel 		rte_pktmbuf_free(hdr);
287af75078fSIntel 		return (NULL);
288af75078fSIntel 	}
289af75078fSIntel 
290af75078fSIntel 	/* prepend new header */
291ea672a8bSOlivier Matz 	hdr->next = pkt;
292af75078fSIntel 
293af75078fSIntel 
294af75078fSIntel 	/* update header's fields */
295ea672a8bSOlivier Matz 	hdr->pkt_len = (uint16_t)(hdr->data_len + pkt->pkt_len);
296ea672a8bSOlivier Matz 	hdr->nb_segs = (uint8_t)(pkt->nb_segs + 1);
297af75078fSIntel 
298af75078fSIntel 	/* copy metadata from source packet*/
299ca04aaeaSBruce Richardson 	hdr->port = pkt->port;
3007869536fSBruce Richardson 	hdr->vlan_tci = pkt->vlan_tci;
3014199fdeaSOlivier Matz 	hdr->tx_offload = pkt->tx_offload;
302ea672a8bSOlivier Matz 	hdr->hash = pkt->hash;
303af75078fSIntel 
304af75078fSIntel 	hdr->ol_flags = pkt->ol_flags;
305af75078fSIntel 
3069aaccf1aSOlivier Matz 	__rte_mbuf_sanity_check(hdr, 1);
307af75078fSIntel 	return (hdr);
308af75078fSIntel }
309af75078fSIntel 
310af75078fSIntel /*
311af75078fSIntel  * Write new Ethernet header to the outgoing packet,
312af75078fSIntel  * and put it into the outgoing queue for the given port.
313af75078fSIntel  */
314af75078fSIntel static inline void
315af75078fSIntel mcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr,
316af75078fSIntel 		struct lcore_queue_conf *qconf, uint8_t port)
317af75078fSIntel {
318af75078fSIntel 	struct ether_hdr *ethdr;
319af75078fSIntel 	uint16_t len;
320af75078fSIntel 
321af75078fSIntel 	/* Construct Ethernet header. */
322af75078fSIntel 	ethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(*ethdr));
323af75078fSIntel 	RTE_MBUF_ASSERT(ethdr != NULL);
324af75078fSIntel 
325af75078fSIntel 	ether_addr_copy(dest_addr, &ethdr->d_addr);
326af75078fSIntel 	ether_addr_copy(&ports_eth_addr[port], &ethdr->s_addr);
327af75078fSIntel 	ethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);
328af75078fSIntel 
329af75078fSIntel 	/* Put new packet into the output queue */
330af75078fSIntel 	len = qconf->tx_mbufs[port].len;
331af75078fSIntel 	qconf->tx_mbufs[port].m_table[len] = pkt;
332af75078fSIntel 	qconf->tx_mbufs[port].len = ++len;
333af75078fSIntel 
334af75078fSIntel 	/* Transmit packets */
335af75078fSIntel 	if (unlikely(MAX_PKT_BURST == len))
336af75078fSIntel 		send_burst(qconf, port);
337af75078fSIntel }
338af75078fSIntel 
339af75078fSIntel /* Multicast forward of the input packet */
340af75078fSIntel static inline void
341af75078fSIntel mcast_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf)
342af75078fSIntel {
343af75078fSIntel 	struct rte_mbuf *mc;
344af75078fSIntel 	struct ipv4_hdr *iphdr;
345af75078fSIntel 	uint32_t dest_addr, port_mask, port_num, use_clone;
346af75078fSIntel 	int32_t hash;
347af75078fSIntel 	uint8_t port;
348af75078fSIntel 	union {
349af75078fSIntel 		uint64_t as_int;
350af75078fSIntel 		struct ether_addr as_addr;
351af75078fSIntel 	} dst_eth_addr;
352af75078fSIntel 
353af75078fSIntel 	/* Remove the Ethernet header from the input packet */
354af75078fSIntel 	iphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr));
355af75078fSIntel 	RTE_MBUF_ASSERT(iphdr != NULL);
356af75078fSIntel 
357af75078fSIntel 	dest_addr = rte_be_to_cpu_32(iphdr->dst_addr);
358af75078fSIntel 
359af75078fSIntel 	/*
360af75078fSIntel 	 * Check that it is a valid multicast address and
361af75078fSIntel 	 * we have some active ports assigned to it.
362af75078fSIntel 	 */
363af75078fSIntel 	if(!IS_IPV4_MCAST(dest_addr) ||
364af75078fSIntel 	    (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 ||
365af75078fSIntel 	    (port_mask = hash & enabled_port_mask) == 0) {
366af75078fSIntel 		rte_pktmbuf_free(m);
367af75078fSIntel 		return;
368af75078fSIntel 	}
369af75078fSIntel 
370af75078fSIntel 	/* Calculate number of destination ports. */
371af75078fSIntel 	port_num = bitcnt(port_mask);
372af75078fSIntel 
373af75078fSIntel 	/* Should we use rte_pktmbuf_clone() or not. */
374af75078fSIntel 	use_clone = (port_num <= MCAST_CLONE_PORTS &&
375ea672a8bSOlivier Matz 	    m->nb_segs <= MCAST_CLONE_SEGS);
376af75078fSIntel 
377af75078fSIntel 	/* Mark all packet's segments as referenced port_num times */
378af75078fSIntel 	if (use_clone == 0)
379af75078fSIntel 		rte_pktmbuf_refcnt_update(m, (uint16_t)port_num);
380af75078fSIntel 
381af75078fSIntel 	/* construct destination ethernet address */
382af75078fSIntel 	dst_eth_addr.as_int = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr);
383af75078fSIntel 
384af75078fSIntel 	for (port = 0; use_clone != port_mask; port_mask >>= 1, port++) {
385af75078fSIntel 
386af75078fSIntel 		/* Prepare output packet and send it out. */
387af75078fSIntel 		if ((port_mask & 1) != 0) {
388af75078fSIntel 			if (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL))
389af75078fSIntel 				mcast_send_pkt(mc, &dst_eth_addr.as_addr,
390af75078fSIntel 						qconf, port);
391af75078fSIntel 			else if (use_clone == 0)
392af75078fSIntel 				rte_pktmbuf_free(m);
393af75078fSIntel 		}
394af75078fSIntel 	}
395af75078fSIntel 
396af75078fSIntel 	/*
397af75078fSIntel 	 * If we making clone packets, then, for the last destination port,
398af75078fSIntel 	 * we can overwrite input packet's metadata.
399af75078fSIntel 	 */
400af75078fSIntel 	if (use_clone != 0)
401af75078fSIntel 		mcast_send_pkt(m, &dst_eth_addr.as_addr, qconf, port);
402af75078fSIntel 	else
403af75078fSIntel 		rte_pktmbuf_free(m);
404af75078fSIntel }
405af75078fSIntel 
406af75078fSIntel /* Send burst of outgoing packet, if timeout expires. */
407af75078fSIntel static inline void
408af75078fSIntel send_timeout_burst(struct lcore_queue_conf *qconf)
409af75078fSIntel {
410af75078fSIntel 	uint64_t cur_tsc;
411af75078fSIntel 	uint8_t portid;
4125c95261dSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
413af75078fSIntel 
414af75078fSIntel 	cur_tsc = rte_rdtsc();
4155c95261dSIntel 	if (likely (cur_tsc < qconf->tx_tsc + drain_tsc))
416af75078fSIntel 		return;
417af75078fSIntel 
418af75078fSIntel 	for (portid = 0; portid < MAX_PORTS; portid++) {
419af75078fSIntel 		if (qconf->tx_mbufs[portid].len != 0)
420af75078fSIntel 			send_burst(qconf, portid);
421af75078fSIntel 	}
422af75078fSIntel 	qconf->tx_tsc = cur_tsc;
423af75078fSIntel }
424af75078fSIntel 
425af75078fSIntel /* main processing loop */
426cdfd5dbbSIntel static int
427af75078fSIntel main_loop(__rte_unused void *dummy)
428af75078fSIntel {
429af75078fSIntel 	struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
4306441b9f6SIntel 	unsigned lcore_id;
431af75078fSIntel 	int i, j, nb_rx;
432af75078fSIntel 	uint8_t portid;
433af75078fSIntel 	struct lcore_queue_conf *qconf;
434af75078fSIntel 
435af75078fSIntel 	lcore_id = rte_lcore_id();
436af75078fSIntel 	qconf = &lcore_queue_conf[lcore_id];
437af75078fSIntel 
438af75078fSIntel 
439af75078fSIntel 	if (qconf->n_rx_queue == 0) {
440af75078fSIntel 		RTE_LOG(INFO, IPv4_MULTICAST, "lcore %u has nothing to do\n",
441af75078fSIntel 		    lcore_id);
442cdfd5dbbSIntel 		return 0;
443af75078fSIntel 	}
444af75078fSIntel 
445af75078fSIntel 	RTE_LOG(INFO, IPv4_MULTICAST, "entering main loop on lcore %u\n",
446af75078fSIntel 	    lcore_id);
447af75078fSIntel 
448af75078fSIntel 	for (i = 0; i < qconf->n_rx_queue; i++) {
449af75078fSIntel 
450af75078fSIntel 		portid = qconf->rx_queue_list[i];
451af75078fSIntel 		RTE_LOG(INFO, IPv4_MULTICAST, " -- lcoreid=%u portid=%d\n",
452af75078fSIntel 		    lcore_id, (int) portid);
453af75078fSIntel 	}
454af75078fSIntel 
455af75078fSIntel 	while (1) {
456af75078fSIntel 
457af75078fSIntel 		/*
458af75078fSIntel 		 * Read packet from RX queues
459af75078fSIntel 		 */
460af75078fSIntel 		for (i = 0; i < qconf->n_rx_queue; i++) {
461af75078fSIntel 
462af75078fSIntel 			portid = qconf->rx_queue_list[i];
463af75078fSIntel 			nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst,
464af75078fSIntel 						 MAX_PKT_BURST);
465af75078fSIntel 
466af75078fSIntel 			/* Prefetch first packets */
467af75078fSIntel 			for (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {
468af75078fSIntel 				rte_prefetch0(rte_pktmbuf_mtod(
469af75078fSIntel 						pkts_burst[j], void *));
470af75078fSIntel 			}
471af75078fSIntel 
472af75078fSIntel 			/* Prefetch and forward already prefetched packets */
473af75078fSIntel 			for (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {
474af75078fSIntel 				rte_prefetch0(rte_pktmbuf_mtod(pkts_burst[
475af75078fSIntel 						j + PREFETCH_OFFSET], void *));
476af75078fSIntel 				mcast_forward(pkts_burst[j], qconf);
477af75078fSIntel 			}
478af75078fSIntel 
479af75078fSIntel 			/* Forward remaining prefetched packets */
480af75078fSIntel 			for (; j < nb_rx; j++) {
481af75078fSIntel 				mcast_forward(pkts_burst[j], qconf);
482af75078fSIntel 			}
483af75078fSIntel 		}
484af75078fSIntel 
485af75078fSIntel 		/* Send out packets from TX queues */
486af75078fSIntel 		send_timeout_burst(qconf);
487af75078fSIntel 	}
488af75078fSIntel }
489af75078fSIntel 
490af75078fSIntel /* display usage */
491af75078fSIntel static void
492af75078fSIntel print_usage(const char *prgname)
493af75078fSIntel {
494af75078fSIntel 	printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n"
495af75078fSIntel 	    "  -p PORTMASK: hexadecimal bitmask of ports to configure\n"
496af75078fSIntel 	    "  -q NQ: number of queue (=ports) per lcore (default is 1)\n",
497af75078fSIntel 	    prgname);
498af75078fSIntel }
499af75078fSIntel 
500af75078fSIntel static uint32_t
501af75078fSIntel parse_portmask(const char *portmask)
502af75078fSIntel {
503af75078fSIntel 	char *end = NULL;
504af75078fSIntel 	unsigned long pm;
505af75078fSIntel 
506af75078fSIntel 	/* parse hexadecimal string */
507af75078fSIntel 	pm = strtoul(portmask, &end, 16);
508af75078fSIntel 	if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
509af75078fSIntel 		return 0;
510af75078fSIntel 
511af75078fSIntel 	return ((uint32_t)pm);
512af75078fSIntel }
513af75078fSIntel 
514af75078fSIntel static int
515af75078fSIntel parse_nqueue(const char *q_arg)
516af75078fSIntel {
517af75078fSIntel 	char *end = NULL;
518af75078fSIntel 	unsigned long n;
519af75078fSIntel 
520af75078fSIntel 	/* parse numerical string */
521af75078fSIntel 	errno = 0;
522af75078fSIntel 	n = strtoul(q_arg, &end, 0);
523af75078fSIntel 	if (errno != 0 || end == NULL || *end != '\0' ||
524af75078fSIntel 			n == 0 || n >= MAX_RX_QUEUE_PER_LCORE)
525af75078fSIntel 		return (-1);
526af75078fSIntel 
527af75078fSIntel 	return (n);
528af75078fSIntel }
529af75078fSIntel 
530af75078fSIntel /* Parse the argument given in the command line of the application */
531af75078fSIntel static int
532af75078fSIntel parse_args(int argc, char **argv)
533af75078fSIntel {
534af75078fSIntel 	int opt, ret;
535af75078fSIntel 	char **argvopt;
536af75078fSIntel 	int option_index;
537af75078fSIntel 	char *prgname = argv[0];
538af75078fSIntel 	static struct option lgopts[] = {
539af75078fSIntel 		{NULL, 0, 0, 0}
540af75078fSIntel 	};
541af75078fSIntel 
542af75078fSIntel 	argvopt = argv;
543af75078fSIntel 
544af75078fSIntel 	while ((opt = getopt_long(argc, argvopt, "p:q:",
545af75078fSIntel 				  lgopts, &option_index)) != EOF) {
546af75078fSIntel 
547af75078fSIntel 		switch (opt) {
548af75078fSIntel 		/* portmask */
549af75078fSIntel 		case 'p':
550af75078fSIntel 			enabled_port_mask = parse_portmask(optarg);
551af75078fSIntel 			if (enabled_port_mask == 0) {
552af75078fSIntel 				printf("invalid portmask\n");
553af75078fSIntel 				print_usage(prgname);
554af75078fSIntel 				return -1;
555af75078fSIntel 			}
556af75078fSIntel 			break;
557af75078fSIntel 
558af75078fSIntel 		/* nqueue */
559af75078fSIntel 		case 'q':
560af75078fSIntel 			rx_queue_per_lcore = parse_nqueue(optarg);
561af75078fSIntel 			if (rx_queue_per_lcore < 0) {
562af75078fSIntel 				printf("invalid queue number\n");
563af75078fSIntel 				print_usage(prgname);
564af75078fSIntel 				return -1;
565af75078fSIntel 			}
566af75078fSIntel 			break;
567af75078fSIntel 
568af75078fSIntel 		default:
569af75078fSIntel 			print_usage(prgname);
570af75078fSIntel 			return -1;
571af75078fSIntel 		}
572af75078fSIntel 	}
573af75078fSIntel 
574af75078fSIntel 	if (optind >= 0)
575af75078fSIntel 		argv[optind-1] = prgname;
576af75078fSIntel 
577af75078fSIntel 	ret = optind-1;
578af75078fSIntel 	optind = 0; /* reset getopt lib */
579af75078fSIntel 	return ret;
580af75078fSIntel }
581af75078fSIntel 
582af75078fSIntel static void
583af75078fSIntel print_ethaddr(const char *name, struct ether_addr *eth_addr)
584af75078fSIntel {
585ec3d82dbSCunming Liang 	char buf[ETHER_ADDR_FMT_SIZE];
586ec3d82dbSCunming Liang 	ether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);
587ec3d82dbSCunming Liang 	printf("%s%s", name, buf);
588af75078fSIntel }
589af75078fSIntel 
590af75078fSIntel static int
591af75078fSIntel init_mcast_hash(void)
592af75078fSIntel {
593af75078fSIntel 	uint32_t i;
594af75078fSIntel 
595e60f71ebSIntel 	mcast_hash_params.socket_id = rte_socket_id();
596af75078fSIntel 	mcast_hash = rte_fbk_hash_create(&mcast_hash_params);
597af75078fSIntel 	if (mcast_hash == NULL){
598af75078fSIntel 		return -1;
599af75078fSIntel 	}
600af75078fSIntel 
601af75078fSIntel 	for (i = 0; i < N_MCAST_GROUPS; i ++){
602af75078fSIntel 		if (rte_fbk_hash_add_key(mcast_hash,
603af75078fSIntel 			mcast_group_table[i].ip,
604af75078fSIntel 			mcast_group_table[i].port_mask) < 0) {
605af75078fSIntel 			return -1;
606af75078fSIntel 		}
607af75078fSIntel 	}
608af75078fSIntel 
609af75078fSIntel 	return 0;
610af75078fSIntel }
611af75078fSIntel 
612d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */
613d3641ae8SIntel static void
614d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask)
615d3641ae8SIntel {
616d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */
617d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
618d3641ae8SIntel 	uint8_t portid, count, all_ports_up, print_flag = 0;
619d3641ae8SIntel 	struct rte_eth_link link;
620d3641ae8SIntel 
621d3641ae8SIntel 	printf("\nChecking link status");
622d3641ae8SIntel 	fflush(stdout);
623d3641ae8SIntel 	for (count = 0; count <= MAX_CHECK_TIME; count++) {
624d3641ae8SIntel 		all_ports_up = 1;
625d3641ae8SIntel 		for (portid = 0; portid < port_num; portid++) {
626d3641ae8SIntel 			if ((port_mask & (1 << portid)) == 0)
627d3641ae8SIntel 				continue;
628d3641ae8SIntel 			memset(&link, 0, sizeof(link));
629d3641ae8SIntel 			rte_eth_link_get_nowait(portid, &link);
630d3641ae8SIntel 			/* print link status if flag set */
631d3641ae8SIntel 			if (print_flag == 1) {
632d3641ae8SIntel 				if (link.link_status)
633d3641ae8SIntel 					printf("Port %d Link Up - speed %u "
634d3641ae8SIntel 						"Mbps - %s\n", (uint8_t)portid,
635d3641ae8SIntel 						(unsigned)link.link_speed,
636d3641ae8SIntel 				(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
637d3641ae8SIntel 					("full-duplex") : ("half-duplex\n"));
638d3641ae8SIntel 				else
639d3641ae8SIntel 					printf("Port %d Link Down\n",
640d3641ae8SIntel 							(uint8_t)portid);
641d3641ae8SIntel 				continue;
642d3641ae8SIntel 			}
643d3641ae8SIntel 			/* clear all_ports_up flag if any link down */
644d3641ae8SIntel 			if (link.link_status == 0) {
645d3641ae8SIntel 				all_ports_up = 0;
646d3641ae8SIntel 				break;
647d3641ae8SIntel 			}
648d3641ae8SIntel 		}
649d3641ae8SIntel 		/* after finally printing all link status, get out */
650d3641ae8SIntel 		if (print_flag == 1)
651d3641ae8SIntel 			break;
652d3641ae8SIntel 
653d3641ae8SIntel 		if (all_ports_up == 0) {
654d3641ae8SIntel 			printf(".");
655d3641ae8SIntel 			fflush(stdout);
656d3641ae8SIntel 			rte_delay_ms(CHECK_INTERVAL);
657d3641ae8SIntel 		}
658d3641ae8SIntel 
659d3641ae8SIntel 		/* set the print_flag if all ports up or timeout */
660d3641ae8SIntel 		if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
661d3641ae8SIntel 			print_flag = 1;
662d3641ae8SIntel 			printf("done\n");
663d3641ae8SIntel 		}
664d3641ae8SIntel 	}
665d3641ae8SIntel }
666d3641ae8SIntel 
667af75078fSIntel int
66898a16481SDavid Marchand main(int argc, char **argv)
669af75078fSIntel {
670af75078fSIntel 	struct lcore_queue_conf *qconf;
67181f7ecd9SPablo de Lara 	struct rte_eth_dev_info dev_info;
67281f7ecd9SPablo de Lara 	struct rte_eth_txconf *txconf;
673af75078fSIntel 	int ret;
674af75078fSIntel 	uint16_t queueid;
6759787d22fSIntel 	unsigned lcore_id = 0, rx_lcore_id = 0;
676af75078fSIntel 	uint32_t n_tx_queue, nb_lcores;
677af75078fSIntel 	uint8_t portid;
678af75078fSIntel 
679af75078fSIntel 	/* init EAL */
680af75078fSIntel 	ret = rte_eal_init(argc, argv);
681af75078fSIntel 	if (ret < 0)
682af75078fSIntel 		rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n");
683af75078fSIntel 	argc -= ret;
684af75078fSIntel 	argv += ret;
685af75078fSIntel 
686af75078fSIntel 	/* parse application arguments (after the EAL ones) */
687af75078fSIntel 	ret = parse_args(argc, argv);
688af75078fSIntel 	if (ret < 0)
689af75078fSIntel 		rte_exit(EXIT_FAILURE, "Invalid IPV4_MULTICAST parameters\n");
690af75078fSIntel 
691af75078fSIntel 	/* create the mbuf pools */
692*ea0c20eaSOlivier Matz 	packet_pool = rte_pktmbuf_pool_create("packet_pool", NB_PKT_MBUF, 32,
693*ea0c20eaSOlivier Matz 		0, PKT_MBUF_DATA_SIZE, rte_socket_id());
694af75078fSIntel 
695af75078fSIntel 	if (packet_pool == NULL)
696af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init packet mbuf pool\n");
697af75078fSIntel 
698*ea0c20eaSOlivier Matz 	header_pool = rte_pktmbuf_pool_create("header_pool", NB_HDR_MBUF, 32,
699*ea0c20eaSOlivier Matz 		0, HDR_MBUF_DATA_SIZE, rte_socket_id());
700af75078fSIntel 
701af75078fSIntel 	if (header_pool == NULL)
702af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init header mbuf pool\n");
703af75078fSIntel 
704*ea0c20eaSOlivier Matz 	clone_pool = rte_pktmbuf_pool_create("clone_pool", NB_CLONE_MBUF, 32,
705*ea0c20eaSOlivier Matz 		0, 0, rte_socket_id());
706af75078fSIntel 
707af75078fSIntel 	if (clone_pool == NULL)
708af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init clone mbuf pool\n");
709af75078fSIntel 
710af75078fSIntel 	nb_ports = rte_eth_dev_count();
711af75078fSIntel 	if (nb_ports == 0)
712af75078fSIntel 		rte_exit(EXIT_FAILURE, "No physical ports!\n");
713af75078fSIntel 	if (nb_ports > MAX_PORTS)
714af75078fSIntel 		nb_ports = MAX_PORTS;
715af75078fSIntel 
716af75078fSIntel 	nb_lcores = rte_lcore_count();
717af75078fSIntel 
718af75078fSIntel 	/* initialize all ports */
719af75078fSIntel 	for (portid = 0; portid < nb_ports; portid++) {
720af75078fSIntel 		/* skip ports that are not enabled */
721af75078fSIntel 		if ((enabled_port_mask & (1 << portid)) == 0) {
722af75078fSIntel 			printf("Skipping disabled port %d\n", portid);
723af75078fSIntel 			continue;
724af75078fSIntel 		}
725af75078fSIntel 
726af75078fSIntel 		qconf = &lcore_queue_conf[rx_lcore_id];
727af75078fSIntel 
728af75078fSIntel 		/* get the lcore_id for this port */
729af75078fSIntel 		while (rte_lcore_is_enabled(rx_lcore_id) == 0 ||
730af75078fSIntel 		       qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) {
731af75078fSIntel 
732af75078fSIntel 			rx_lcore_id ++;
733af75078fSIntel 			qconf = &lcore_queue_conf[rx_lcore_id];
734af75078fSIntel 
735af75078fSIntel 			if (rx_lcore_id >= RTE_MAX_LCORE)
736af75078fSIntel 				rte_exit(EXIT_FAILURE, "Not enough cores\n");
737af75078fSIntel 		}
738af75078fSIntel 		qconf->rx_queue_list[qconf->n_rx_queue] = portid;
739af75078fSIntel 		qconf->n_rx_queue++;
740af75078fSIntel 
741af75078fSIntel 		/* init port */
742af75078fSIntel 		printf("Initializing port %d on lcore %u... ", portid,
743af75078fSIntel 		       rx_lcore_id);
744af75078fSIntel 		fflush(stdout);
745af75078fSIntel 
746af75078fSIntel 		n_tx_queue = nb_lcores;
747af75078fSIntel 		if (n_tx_queue > MAX_TX_QUEUE_PER_PORT)
748af75078fSIntel 			n_tx_queue = MAX_TX_QUEUE_PER_PORT;
749af75078fSIntel 		ret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue,
750af75078fSIntel 					    &port_conf);
751af75078fSIntel 		if (ret < 0)
752af75078fSIntel 			rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%d\n",
753af75078fSIntel 				  ret, portid);
754af75078fSIntel 
755af75078fSIntel 		rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
756af75078fSIntel 		print_ethaddr(" Address:", &ports_eth_addr[portid]);
757af75078fSIntel 		printf(", ");
758af75078fSIntel 
759af75078fSIntel 		/* init one RX queue */
760af75078fSIntel 		queueid = 0;
761af75078fSIntel 		printf("rxq=%hu ", queueid);
762af75078fSIntel 		fflush(stdout);
763af75078fSIntel 		ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
76481f7ecd9SPablo de Lara 					     rte_eth_dev_socket_id(portid),
76581f7ecd9SPablo de Lara 					     NULL,
766af75078fSIntel 					     packet_pool);
767af75078fSIntel 		if (ret < 0)
768af75078fSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, port=%d\n",
769af75078fSIntel 				  ret, portid);
770af75078fSIntel 
771af75078fSIntel 		/* init one TX queue per couple (lcore,port) */
772af75078fSIntel 		queueid = 0;
773af75078fSIntel 
774af75078fSIntel 		RTE_LCORE_FOREACH(lcore_id) {
775af75078fSIntel 			if (rte_lcore_is_enabled(lcore_id) == 0)
776af75078fSIntel 				continue;
777af75078fSIntel 			printf("txq=%u,%hu ", lcore_id, queueid);
778af75078fSIntel 			fflush(stdout);
77981f7ecd9SPablo de Lara 
78081f7ecd9SPablo de Lara 			rte_eth_dev_info_get(portid, &dev_info);
78181f7ecd9SPablo de Lara 			txconf = &dev_info.default_txconf;
78281f7ecd9SPablo de Lara 			txconf->txq_flags = 0;
783af75078fSIntel 			ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
78481f7ecd9SPablo de Lara 						     rte_lcore_to_socket_id(lcore_id), txconf);
785af75078fSIntel 			if (ret < 0)
786af75078fSIntel 				rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, "
787af75078fSIntel 					  "port=%d\n", ret, portid);
788af75078fSIntel 
789af75078fSIntel 			qconf = &lcore_queue_conf[lcore_id];
790af75078fSIntel 			qconf->tx_queue_id[portid] = queueid;
791af75078fSIntel 			queueid++;
792af75078fSIntel 		}
793af75078fSIntel 
794af75078fSIntel 		/* Start device */
795af75078fSIntel 		ret = rte_eth_dev_start(portid);
796af75078fSIntel 		if (ret < 0)
797af75078fSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%d\n",
798af75078fSIntel 				  ret, portid);
799af75078fSIntel 
800d3641ae8SIntel 		printf("done:\n");
801af75078fSIntel 	}
802af75078fSIntel 
803d3641ae8SIntel 	check_all_ports_link_status(nb_ports, enabled_port_mask);
804af75078fSIntel 
805af75078fSIntel 	/* initialize the multicast hash */
806af75078fSIntel 	int retval = init_mcast_hash();
807af75078fSIntel 	if (retval != 0)
808af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot build the multicast hash\n");
809af75078fSIntel 
810af75078fSIntel 	/* launch per-lcore init on every lcore */
811af75078fSIntel 	rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
812af75078fSIntel 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
813af75078fSIntel 		if (rte_eal_wait_lcore(lcore_id) < 0)
814af75078fSIntel 			return -1;
815af75078fSIntel 	}
816af75078fSIntel 
817af75078fSIntel 	return 0;
818af75078fSIntel }
819