1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel */ 33af75078fSIntel 34af75078fSIntel #include <stdio.h> 35af75078fSIntel #include <stdlib.h> 36af75078fSIntel #include <stdint.h> 37af75078fSIntel #include <inttypes.h> 38af75078fSIntel #include <sys/types.h> 39af75078fSIntel #include <string.h> 40af75078fSIntel #include <sys/queue.h> 41af75078fSIntel #include <stdarg.h> 42af75078fSIntel #include <errno.h> 43af75078fSIntel #include <getopt.h> 44af75078fSIntel 45af75078fSIntel #include <rte_common.h> 46af75078fSIntel #include <rte_byteorder.h> 47af75078fSIntel #include <rte_log.h> 48af75078fSIntel #include <rte_tailq.h> 49af75078fSIntel #include <rte_memory.h> 50af75078fSIntel #include <rte_memcpy.h> 51af75078fSIntel #include <rte_memzone.h> 52af75078fSIntel #include <rte_eal.h> 53af75078fSIntel #include <rte_per_lcore.h> 54af75078fSIntel #include <rte_launch.h> 55af75078fSIntel #include <rte_atomic.h> 56af75078fSIntel #include <rte_cycles.h> 57af75078fSIntel #include <rte_prefetch.h> 58af75078fSIntel #include <rte_lcore.h> 59af75078fSIntel #include <rte_per_lcore.h> 60af75078fSIntel #include <rte_branch_prediction.h> 61af75078fSIntel #include <rte_interrupts.h> 62af75078fSIntel #include <rte_pci.h> 63af75078fSIntel #include <rte_random.h> 64af75078fSIntel #include <rte_debug.h> 65af75078fSIntel #include <rte_ether.h> 66af75078fSIntel #include <rte_ethdev.h> 67af75078fSIntel #include <rte_ring.h> 68af75078fSIntel #include <rte_mempool.h> 69af75078fSIntel #include <rte_mbuf.h> 70af75078fSIntel #include <rte_malloc.h> 71af75078fSIntel #include <rte_fbk_hash.h> 72af75078fSIntel #include <rte_ip.h> 73af75078fSIntel 74af75078fSIntel #define RTE_LOGTYPE_IPv4_MULTICAST RTE_LOGTYPE_USER1 75af75078fSIntel 76af75078fSIntel #define MAX_PORTS 16 77af75078fSIntel 78af75078fSIntel #define MCAST_CLONE_PORTS 2 79af75078fSIntel #define MCAST_CLONE_SEGS 2 80af75078fSIntel 81af75078fSIntel #define PKT_MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM) 82af75078fSIntel #define NB_PKT_MBUF 8192 83af75078fSIntel 84af75078fSIntel #define HDR_MBUF_SIZE (sizeof(struct rte_mbuf) + 2 * RTE_PKTMBUF_HEADROOM) 85af75078fSIntel #define NB_HDR_MBUF (NB_PKT_MBUF * MAX_PORTS) 86af75078fSIntel 87af75078fSIntel #define CLONE_MBUF_SIZE (sizeof(struct rte_mbuf)) 88af75078fSIntel #define NB_CLONE_MBUF (NB_PKT_MBUF * MCAST_CLONE_PORTS * MCAST_CLONE_SEGS * 2) 89af75078fSIntel 90af75078fSIntel /* allow max jumbo frame 9.5 KB */ 91af75078fSIntel #define JUMBO_FRAME_MAX_SIZE 0x2600 92af75078fSIntel 93af75078fSIntel #define MAX_PKT_BURST 32 945c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */ 95af75078fSIntel 96af75078fSIntel /* Configure how many packets ahead to prefetch, when reading packets */ 97af75078fSIntel #define PREFETCH_OFFSET 3 98af75078fSIntel 99af75078fSIntel /* 100af75078fSIntel * Construct Ethernet multicast address from IPv4 multicast address. 101af75078fSIntel * Citing RFC 1112, section 6.4: 102af75078fSIntel * "An IP host group address is mapped to an Ethernet multicast address 103af75078fSIntel * by placing the low-order 23-bits of the IP address into the low-order 104af75078fSIntel * 23 bits of the Ethernet multicast address 01-00-5E-00-00-00 (hex)." 105af75078fSIntel */ 106af75078fSIntel #define ETHER_ADDR_FOR_IPV4_MCAST(x) \ 107af75078fSIntel (rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16) 108af75078fSIntel 109af75078fSIntel /* 110af75078fSIntel * Configurable number of RX/TX ring descriptors 111af75078fSIntel */ 112af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128 113af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512 114af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; 115af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; 116af75078fSIntel 117af75078fSIntel /* ethernet addresses of ports */ 118af75078fSIntel static struct ether_addr ports_eth_addr[MAX_PORTS]; 119af75078fSIntel 120af75078fSIntel /* mask of enabled ports */ 121af75078fSIntel static uint32_t enabled_port_mask = 0; 122af75078fSIntel 123af75078fSIntel static uint8_t nb_ports = 0; 124af75078fSIntel 125af75078fSIntel static int rx_queue_per_lcore = 1; 126af75078fSIntel 127af75078fSIntel struct mbuf_table { 128af75078fSIntel uint16_t len; 129af75078fSIntel struct rte_mbuf *m_table[MAX_PKT_BURST]; 130af75078fSIntel }; 131af75078fSIntel 132af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16 133af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16 134af75078fSIntel struct lcore_queue_conf { 135af75078fSIntel uint64_t tx_tsc; 136af75078fSIntel uint16_t n_rx_queue; 137af75078fSIntel uint8_t rx_queue_list[MAX_RX_QUEUE_PER_LCORE]; 138af75078fSIntel uint16_t tx_queue_id[MAX_PORTS]; 139af75078fSIntel struct mbuf_table tx_mbufs[MAX_PORTS]; 140af75078fSIntel } __rte_cache_aligned; 141af75078fSIntel static struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE]; 142af75078fSIntel 143af75078fSIntel static const struct rte_eth_conf port_conf = { 144af75078fSIntel .rxmode = { 145af75078fSIntel .max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE, 146af75078fSIntel .split_hdr_size = 0, 147af75078fSIntel .header_split = 0, /**< Header Split disabled */ 148af75078fSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled */ 149af75078fSIntel .hw_vlan_filter = 0, /**< VLAN filtering disabled */ 150af75078fSIntel .jumbo_frame = 1, /**< Jumbo Frame Support enabled */ 151af75078fSIntel .hw_strip_crc = 0, /**< CRC stripped by hardware */ 152af75078fSIntel }, 153af75078fSIntel .txmode = { 15432e7aa0bSIntel .mq_mode = ETH_MQ_TX_NONE, 155af75078fSIntel }, 156af75078fSIntel }; 157af75078fSIntel 158af75078fSIntel static struct rte_mempool *packet_pool, *header_pool, *clone_pool; 159af75078fSIntel 160af75078fSIntel 161af75078fSIntel /* Multicast */ 162af75078fSIntel static struct rte_fbk_hash_params mcast_hash_params = { 163af75078fSIntel .name = "MCAST_HASH", 164af75078fSIntel .entries = 1024, 165af75078fSIntel .entries_per_bucket = 4, 166e60f71ebSIntel .socket_id = 0, 167af75078fSIntel .hash_func = NULL, 168af75078fSIntel .init_val = 0, 169af75078fSIntel }; 170af75078fSIntel 171af75078fSIntel struct rte_fbk_hash_table *mcast_hash = NULL; 172af75078fSIntel 173af75078fSIntel struct mcast_group_params { 174af75078fSIntel uint32_t ip; 175af75078fSIntel uint16_t port_mask; 176af75078fSIntel }; 177af75078fSIntel 178af75078fSIntel static struct mcast_group_params mcast_group_table[] = { 179af75078fSIntel {IPv4(224,0,0,101), 0x1}, 180af75078fSIntel {IPv4(224,0,0,102), 0x2}, 181af75078fSIntel {IPv4(224,0,0,103), 0x3}, 182af75078fSIntel {IPv4(224,0,0,104), 0x4}, 183af75078fSIntel {IPv4(224,0,0,105), 0x5}, 184af75078fSIntel {IPv4(224,0,0,106), 0x6}, 185af75078fSIntel {IPv4(224,0,0,107), 0x7}, 186af75078fSIntel {IPv4(224,0,0,108), 0x8}, 187af75078fSIntel {IPv4(224,0,0,109), 0x9}, 188af75078fSIntel {IPv4(224,0,0,110), 0xA}, 189af75078fSIntel {IPv4(224,0,0,111), 0xB}, 190af75078fSIntel {IPv4(224,0,0,112), 0xC}, 191af75078fSIntel {IPv4(224,0,0,113), 0xD}, 192af75078fSIntel {IPv4(224,0,0,114), 0xE}, 193af75078fSIntel {IPv4(224,0,0,115), 0xF}, 194af75078fSIntel }; 195af75078fSIntel 196af75078fSIntel #define N_MCAST_GROUPS \ 197af75078fSIntel (sizeof (mcast_group_table) / sizeof (mcast_group_table[0])) 198af75078fSIntel 199af75078fSIntel 200af75078fSIntel /* Send burst of packets on an output interface */ 201af75078fSIntel static void 202af75078fSIntel send_burst(struct lcore_queue_conf *qconf, uint8_t port) 203af75078fSIntel { 204af75078fSIntel struct rte_mbuf **m_table; 205af75078fSIntel uint16_t n, queueid; 206af75078fSIntel int ret; 207af75078fSIntel 208af75078fSIntel queueid = qconf->tx_queue_id[port]; 209af75078fSIntel m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table; 210af75078fSIntel n = qconf->tx_mbufs[port].len; 211af75078fSIntel 212af75078fSIntel ret = rte_eth_tx_burst(port, queueid, m_table, n); 213af75078fSIntel while (unlikely (ret < n)) { 214af75078fSIntel rte_pktmbuf_free(m_table[ret]); 215af75078fSIntel ret++; 216af75078fSIntel } 217af75078fSIntel 218af75078fSIntel qconf->tx_mbufs[port].len = 0; 219af75078fSIntel } 220af75078fSIntel 221af75078fSIntel /* Get number of bits set. */ 222af75078fSIntel static inline uint32_t 223af75078fSIntel bitcnt(uint32_t v) 224af75078fSIntel { 225af75078fSIntel uint32_t n; 226af75078fSIntel 227af75078fSIntel for (n = 0; v != 0; v &= v - 1, n++) 228af75078fSIntel ; 229af75078fSIntel 230af75078fSIntel return (n); 231af75078fSIntel } 232af75078fSIntel 233af75078fSIntel /** 234af75078fSIntel * Create the output multicast packet based on the given input packet. 235af75078fSIntel * There are two approaches for creating outgoing packet, though both 236af75078fSIntel * are based on data zero-copy idea, they differ in few details: 237af75078fSIntel * First one creates a clone of the input packet, e.g - walk though all 238af75078fSIntel * segments of the input packet, and for each of them create a new packet 239af75078fSIntel * mbuf and attach that new mbuf to the segment (refer to rte_pktmbuf_clone() 240af75078fSIntel * for more details). Then new mbuf is allocated for the packet header 241af75078fSIntel * and is prepended to the 'clone' mbuf. 242af75078fSIntel * Second approach doesn't make a clone, it just increment refcnt for all 243af75078fSIntel * input packet segments. Then it allocates new mbuf for the packet header 244af75078fSIntel * and prepends it to the input packet. 245af75078fSIntel * Basically first approach reuses only input packet's data, but creates 246af75078fSIntel * it's own copy of packet's metadata. Second approach reuses both input's 247af75078fSIntel * packet data and metadata. 248af75078fSIntel * The advantage of first approach - is that each outgoing packet has it's 249af75078fSIntel * own copy of metadata, so we can safely modify data pointer of the 250af75078fSIntel * input packet. That allows us to skip creation if the output packet for 251af75078fSIntel * the last destination port, but instead modify input packet's header inplace, 252af75078fSIntel * e.g: for N destination ports we need to invoke mcast_out_pkt (N-1) times. 253af75078fSIntel * The advantage of second approach - less work for each outgoing packet, 254af75078fSIntel * e.g: we skip "clone" operation completely. Though it comes with a price - 255af75078fSIntel * input packet's metadata has to be intact. So for N destination ports we 256af75078fSIntel * need to invoke mcast_out_pkt N times. 257af75078fSIntel * So for small number of outgoing ports (and segments in the input packet) 258af75078fSIntel * first approach will be faster. 259af75078fSIntel * As number of outgoing ports (and/or input segments) will grow, 260af75078fSIntel * second way will become more preferable. 261af75078fSIntel * 262af75078fSIntel * @param pkt 263af75078fSIntel * Input packet mbuf. 264af75078fSIntel * @param use_clone 265af75078fSIntel * Control which of the two approaches described above should be used: 266af75078fSIntel * - 0 - use second approach: 267af75078fSIntel * Don't "clone" input packet. 268af75078fSIntel * Prepend new header directly to the input packet 269af75078fSIntel * - 1 - use first approach: 270af75078fSIntel * Make a "clone" of input packet first. 271af75078fSIntel * Prepend new header to the clone of the input packet 272af75078fSIntel * @return 273af75078fSIntel * - The pointer to the new outgoing packet. 274af75078fSIntel * - NULL if operation failed. 275af75078fSIntel */ 276af75078fSIntel static inline struct rte_mbuf * 277af75078fSIntel mcast_out_pkt(struct rte_mbuf *pkt, int use_clone) 278af75078fSIntel { 279af75078fSIntel struct rte_mbuf *hdr; 280af75078fSIntel 281af75078fSIntel /* Create new mbuf for the header. */ 282af75078fSIntel if (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL)) 283af75078fSIntel return (NULL); 284af75078fSIntel 285af75078fSIntel /* If requested, then make a new clone packet. */ 286af75078fSIntel if (use_clone != 0 && 287af75078fSIntel unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) { 288af75078fSIntel rte_pktmbuf_free(hdr); 289af75078fSIntel return (NULL); 290af75078fSIntel } 291af75078fSIntel 292af75078fSIntel /* prepend new header */ 293ea672a8bSOlivier Matz hdr->next = pkt; 294af75078fSIntel 295af75078fSIntel 296af75078fSIntel /* update header's fields */ 297ea672a8bSOlivier Matz hdr->pkt_len = (uint16_t)(hdr->data_len + pkt->pkt_len); 298ea672a8bSOlivier Matz hdr->nb_segs = (uint8_t)(pkt->nb_segs + 1); 299af75078fSIntel 300af75078fSIntel /* copy metadata from source packet*/ 301ca04aaeaSBruce Richardson hdr->port = pkt->port; 3027869536fSBruce Richardson hdr->vlan_tci = pkt->vlan_tci; 3034199fdeaSOlivier Matz hdr->tx_offload = pkt->tx_offload; 304ea672a8bSOlivier Matz hdr->hash = pkt->hash; 305af75078fSIntel 306af75078fSIntel hdr->ol_flags = pkt->ol_flags; 307af75078fSIntel 3089aaccf1aSOlivier Matz __rte_mbuf_sanity_check(hdr, 1); 309af75078fSIntel return (hdr); 310af75078fSIntel } 311af75078fSIntel 312af75078fSIntel /* 313af75078fSIntel * Write new Ethernet header to the outgoing packet, 314af75078fSIntel * and put it into the outgoing queue for the given port. 315af75078fSIntel */ 316af75078fSIntel static inline void 317af75078fSIntel mcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr, 318af75078fSIntel struct lcore_queue_conf *qconf, uint8_t port) 319af75078fSIntel { 320af75078fSIntel struct ether_hdr *ethdr; 321af75078fSIntel uint16_t len; 322af75078fSIntel 323af75078fSIntel /* Construct Ethernet header. */ 324af75078fSIntel ethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(*ethdr)); 325af75078fSIntel RTE_MBUF_ASSERT(ethdr != NULL); 326af75078fSIntel 327af75078fSIntel ether_addr_copy(dest_addr, ðdr->d_addr); 328af75078fSIntel ether_addr_copy(&ports_eth_addr[port], ðdr->s_addr); 329af75078fSIntel ethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4); 330af75078fSIntel 331af75078fSIntel /* Put new packet into the output queue */ 332af75078fSIntel len = qconf->tx_mbufs[port].len; 333af75078fSIntel qconf->tx_mbufs[port].m_table[len] = pkt; 334af75078fSIntel qconf->tx_mbufs[port].len = ++len; 335af75078fSIntel 336af75078fSIntel /* Transmit packets */ 337af75078fSIntel if (unlikely(MAX_PKT_BURST == len)) 338af75078fSIntel send_burst(qconf, port); 339af75078fSIntel } 340af75078fSIntel 341af75078fSIntel /* Multicast forward of the input packet */ 342af75078fSIntel static inline void 343af75078fSIntel mcast_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf) 344af75078fSIntel { 345af75078fSIntel struct rte_mbuf *mc; 346af75078fSIntel struct ipv4_hdr *iphdr; 347af75078fSIntel uint32_t dest_addr, port_mask, port_num, use_clone; 348af75078fSIntel int32_t hash; 349af75078fSIntel uint8_t port; 350af75078fSIntel union { 351af75078fSIntel uint64_t as_int; 352af75078fSIntel struct ether_addr as_addr; 353af75078fSIntel } dst_eth_addr; 354af75078fSIntel 355af75078fSIntel /* Remove the Ethernet header from the input packet */ 356af75078fSIntel iphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr)); 357af75078fSIntel RTE_MBUF_ASSERT(iphdr != NULL); 358af75078fSIntel 359af75078fSIntel dest_addr = rte_be_to_cpu_32(iphdr->dst_addr); 360af75078fSIntel 361af75078fSIntel /* 362af75078fSIntel * Check that it is a valid multicast address and 363af75078fSIntel * we have some active ports assigned to it. 364af75078fSIntel */ 365af75078fSIntel if(!IS_IPV4_MCAST(dest_addr) || 366af75078fSIntel (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 || 367af75078fSIntel (port_mask = hash & enabled_port_mask) == 0) { 368af75078fSIntel rte_pktmbuf_free(m); 369af75078fSIntel return; 370af75078fSIntel } 371af75078fSIntel 372af75078fSIntel /* Calculate number of destination ports. */ 373af75078fSIntel port_num = bitcnt(port_mask); 374af75078fSIntel 375af75078fSIntel /* Should we use rte_pktmbuf_clone() or not. */ 376af75078fSIntel use_clone = (port_num <= MCAST_CLONE_PORTS && 377ea672a8bSOlivier Matz m->nb_segs <= MCAST_CLONE_SEGS); 378af75078fSIntel 379af75078fSIntel /* Mark all packet's segments as referenced port_num times */ 380af75078fSIntel if (use_clone == 0) 381af75078fSIntel rte_pktmbuf_refcnt_update(m, (uint16_t)port_num); 382af75078fSIntel 383af75078fSIntel /* construct destination ethernet address */ 384af75078fSIntel dst_eth_addr.as_int = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr); 385af75078fSIntel 386af75078fSIntel for (port = 0; use_clone != port_mask; port_mask >>= 1, port++) { 387af75078fSIntel 388af75078fSIntel /* Prepare output packet and send it out. */ 389af75078fSIntel if ((port_mask & 1) != 0) { 390af75078fSIntel if (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL)) 391af75078fSIntel mcast_send_pkt(mc, &dst_eth_addr.as_addr, 392af75078fSIntel qconf, port); 393af75078fSIntel else if (use_clone == 0) 394af75078fSIntel rte_pktmbuf_free(m); 395af75078fSIntel } 396af75078fSIntel } 397af75078fSIntel 398af75078fSIntel /* 399af75078fSIntel * If we making clone packets, then, for the last destination port, 400af75078fSIntel * we can overwrite input packet's metadata. 401af75078fSIntel */ 402af75078fSIntel if (use_clone != 0) 403af75078fSIntel mcast_send_pkt(m, &dst_eth_addr.as_addr, qconf, port); 404af75078fSIntel else 405af75078fSIntel rte_pktmbuf_free(m); 406af75078fSIntel } 407af75078fSIntel 408af75078fSIntel /* Send burst of outgoing packet, if timeout expires. */ 409af75078fSIntel static inline void 410af75078fSIntel send_timeout_burst(struct lcore_queue_conf *qconf) 411af75078fSIntel { 412af75078fSIntel uint64_t cur_tsc; 413af75078fSIntel uint8_t portid; 4145c95261dSIntel const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US; 415af75078fSIntel 416af75078fSIntel cur_tsc = rte_rdtsc(); 4175c95261dSIntel if (likely (cur_tsc < qconf->tx_tsc + drain_tsc)) 418af75078fSIntel return; 419af75078fSIntel 420af75078fSIntel for (portid = 0; portid < MAX_PORTS; portid++) { 421af75078fSIntel if (qconf->tx_mbufs[portid].len != 0) 422af75078fSIntel send_burst(qconf, portid); 423af75078fSIntel } 424af75078fSIntel qconf->tx_tsc = cur_tsc; 425af75078fSIntel } 426af75078fSIntel 427af75078fSIntel /* main processing loop */ 428cdfd5dbbSIntel static int 429af75078fSIntel main_loop(__rte_unused void *dummy) 430af75078fSIntel { 431af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 4326441b9f6SIntel unsigned lcore_id; 433af75078fSIntel int i, j, nb_rx; 434af75078fSIntel uint8_t portid; 435af75078fSIntel struct lcore_queue_conf *qconf; 436af75078fSIntel 437af75078fSIntel lcore_id = rte_lcore_id(); 438af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 439af75078fSIntel 440af75078fSIntel 441af75078fSIntel if (qconf->n_rx_queue == 0) { 442af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, "lcore %u has nothing to do\n", 443af75078fSIntel lcore_id); 444cdfd5dbbSIntel return 0; 445af75078fSIntel } 446af75078fSIntel 447af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, "entering main loop on lcore %u\n", 448af75078fSIntel lcore_id); 449af75078fSIntel 450af75078fSIntel for (i = 0; i < qconf->n_rx_queue; i++) { 451af75078fSIntel 452af75078fSIntel portid = qconf->rx_queue_list[i]; 453af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, " -- lcoreid=%u portid=%d\n", 454af75078fSIntel lcore_id, (int) portid); 455af75078fSIntel } 456af75078fSIntel 457af75078fSIntel while (1) { 458af75078fSIntel 459af75078fSIntel /* 460af75078fSIntel * Read packet from RX queues 461af75078fSIntel */ 462af75078fSIntel for (i = 0; i < qconf->n_rx_queue; i++) { 463af75078fSIntel 464af75078fSIntel portid = qconf->rx_queue_list[i]; 465af75078fSIntel nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst, 466af75078fSIntel MAX_PKT_BURST); 467af75078fSIntel 468af75078fSIntel /* Prefetch first packets */ 469af75078fSIntel for (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) { 470af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod( 471af75078fSIntel pkts_burst[j], void *)); 472af75078fSIntel } 473af75078fSIntel 474af75078fSIntel /* Prefetch and forward already prefetched packets */ 475af75078fSIntel for (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) { 476af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod(pkts_burst[ 477af75078fSIntel j + PREFETCH_OFFSET], void *)); 478af75078fSIntel mcast_forward(pkts_burst[j], qconf); 479af75078fSIntel } 480af75078fSIntel 481af75078fSIntel /* Forward remaining prefetched packets */ 482af75078fSIntel for (; j < nb_rx; j++) { 483af75078fSIntel mcast_forward(pkts_burst[j], qconf); 484af75078fSIntel } 485af75078fSIntel } 486af75078fSIntel 487af75078fSIntel /* Send out packets from TX queues */ 488af75078fSIntel send_timeout_burst(qconf); 489af75078fSIntel } 490af75078fSIntel } 491af75078fSIntel 492af75078fSIntel /* display usage */ 493af75078fSIntel static void 494af75078fSIntel print_usage(const char *prgname) 495af75078fSIntel { 496af75078fSIntel printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n" 497af75078fSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n" 498af75078fSIntel " -q NQ: number of queue (=ports) per lcore (default is 1)\n", 499af75078fSIntel prgname); 500af75078fSIntel } 501af75078fSIntel 502af75078fSIntel static uint32_t 503af75078fSIntel parse_portmask(const char *portmask) 504af75078fSIntel { 505af75078fSIntel char *end = NULL; 506af75078fSIntel unsigned long pm; 507af75078fSIntel 508af75078fSIntel /* parse hexadecimal string */ 509af75078fSIntel pm = strtoul(portmask, &end, 16); 510af75078fSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0')) 511af75078fSIntel return 0; 512af75078fSIntel 513af75078fSIntel return ((uint32_t)pm); 514af75078fSIntel } 515af75078fSIntel 516af75078fSIntel static int 517af75078fSIntel parse_nqueue(const char *q_arg) 518af75078fSIntel { 519af75078fSIntel char *end = NULL; 520af75078fSIntel unsigned long n; 521af75078fSIntel 522af75078fSIntel /* parse numerical string */ 523af75078fSIntel errno = 0; 524af75078fSIntel n = strtoul(q_arg, &end, 0); 525af75078fSIntel if (errno != 0 || end == NULL || *end != '\0' || 526af75078fSIntel n == 0 || n >= MAX_RX_QUEUE_PER_LCORE) 527af75078fSIntel return (-1); 528af75078fSIntel 529af75078fSIntel return (n); 530af75078fSIntel } 531af75078fSIntel 532af75078fSIntel /* Parse the argument given in the command line of the application */ 533af75078fSIntel static int 534af75078fSIntel parse_args(int argc, char **argv) 535af75078fSIntel { 536af75078fSIntel int opt, ret; 537af75078fSIntel char **argvopt; 538af75078fSIntel int option_index; 539af75078fSIntel char *prgname = argv[0]; 540af75078fSIntel static struct option lgopts[] = { 541af75078fSIntel {NULL, 0, 0, 0} 542af75078fSIntel }; 543af75078fSIntel 544af75078fSIntel argvopt = argv; 545af75078fSIntel 546af75078fSIntel while ((opt = getopt_long(argc, argvopt, "p:q:", 547af75078fSIntel lgopts, &option_index)) != EOF) { 548af75078fSIntel 549af75078fSIntel switch (opt) { 550af75078fSIntel /* portmask */ 551af75078fSIntel case 'p': 552af75078fSIntel enabled_port_mask = parse_portmask(optarg); 553af75078fSIntel if (enabled_port_mask == 0) { 554af75078fSIntel printf("invalid portmask\n"); 555af75078fSIntel print_usage(prgname); 556af75078fSIntel return -1; 557af75078fSIntel } 558af75078fSIntel break; 559af75078fSIntel 560af75078fSIntel /* nqueue */ 561af75078fSIntel case 'q': 562af75078fSIntel rx_queue_per_lcore = parse_nqueue(optarg); 563af75078fSIntel if (rx_queue_per_lcore < 0) { 564af75078fSIntel printf("invalid queue number\n"); 565af75078fSIntel print_usage(prgname); 566af75078fSIntel return -1; 567af75078fSIntel } 568af75078fSIntel break; 569af75078fSIntel 570af75078fSIntel default: 571af75078fSIntel print_usage(prgname); 572af75078fSIntel return -1; 573af75078fSIntel } 574af75078fSIntel } 575af75078fSIntel 576af75078fSIntel if (optind >= 0) 577af75078fSIntel argv[optind-1] = prgname; 578af75078fSIntel 579af75078fSIntel ret = optind-1; 580af75078fSIntel optind = 0; /* reset getopt lib */ 581af75078fSIntel return ret; 582af75078fSIntel } 583af75078fSIntel 584af75078fSIntel static void 585af75078fSIntel print_ethaddr(const char *name, struct ether_addr *eth_addr) 586af75078fSIntel { 587ec3d82dbSCunming Liang char buf[ETHER_ADDR_FMT_SIZE]; 588ec3d82dbSCunming Liang ether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr); 589ec3d82dbSCunming Liang printf("%s%s", name, buf); 590af75078fSIntel } 591af75078fSIntel 592af75078fSIntel static int 593af75078fSIntel init_mcast_hash(void) 594af75078fSIntel { 595af75078fSIntel uint32_t i; 596af75078fSIntel 597e60f71ebSIntel mcast_hash_params.socket_id = rte_socket_id(); 598af75078fSIntel mcast_hash = rte_fbk_hash_create(&mcast_hash_params); 599af75078fSIntel if (mcast_hash == NULL){ 600af75078fSIntel return -1; 601af75078fSIntel } 602af75078fSIntel 603af75078fSIntel for (i = 0; i < N_MCAST_GROUPS; i ++){ 604af75078fSIntel if (rte_fbk_hash_add_key(mcast_hash, 605af75078fSIntel mcast_group_table[i].ip, 606af75078fSIntel mcast_group_table[i].port_mask) < 0) { 607af75078fSIntel return -1; 608af75078fSIntel } 609af75078fSIntel } 610af75078fSIntel 611af75078fSIntel return 0; 612af75078fSIntel } 613af75078fSIntel 614d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 615d3641ae8SIntel static void 616d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask) 617d3641ae8SIntel { 618d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */ 619d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 620d3641ae8SIntel uint8_t portid, count, all_ports_up, print_flag = 0; 621d3641ae8SIntel struct rte_eth_link link; 622d3641ae8SIntel 623d3641ae8SIntel printf("\nChecking link status"); 624d3641ae8SIntel fflush(stdout); 625d3641ae8SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 626d3641ae8SIntel all_ports_up = 1; 627d3641ae8SIntel for (portid = 0; portid < port_num; portid++) { 628d3641ae8SIntel if ((port_mask & (1 << portid)) == 0) 629d3641ae8SIntel continue; 630d3641ae8SIntel memset(&link, 0, sizeof(link)); 631d3641ae8SIntel rte_eth_link_get_nowait(portid, &link); 632d3641ae8SIntel /* print link status if flag set */ 633d3641ae8SIntel if (print_flag == 1) { 634d3641ae8SIntel if (link.link_status) 635d3641ae8SIntel printf("Port %d Link Up - speed %u " 636d3641ae8SIntel "Mbps - %s\n", (uint8_t)portid, 637d3641ae8SIntel (unsigned)link.link_speed, 638d3641ae8SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 639d3641ae8SIntel ("full-duplex") : ("half-duplex\n")); 640d3641ae8SIntel else 641d3641ae8SIntel printf("Port %d Link Down\n", 642d3641ae8SIntel (uint8_t)portid); 643d3641ae8SIntel continue; 644d3641ae8SIntel } 645d3641ae8SIntel /* clear all_ports_up flag if any link down */ 646d3641ae8SIntel if (link.link_status == 0) { 647d3641ae8SIntel all_ports_up = 0; 648d3641ae8SIntel break; 649d3641ae8SIntel } 650d3641ae8SIntel } 651d3641ae8SIntel /* after finally printing all link status, get out */ 652d3641ae8SIntel if (print_flag == 1) 653d3641ae8SIntel break; 654d3641ae8SIntel 655d3641ae8SIntel if (all_ports_up == 0) { 656d3641ae8SIntel printf("."); 657d3641ae8SIntel fflush(stdout); 658d3641ae8SIntel rte_delay_ms(CHECK_INTERVAL); 659d3641ae8SIntel } 660d3641ae8SIntel 661d3641ae8SIntel /* set the print_flag if all ports up or timeout */ 662d3641ae8SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 663d3641ae8SIntel print_flag = 1; 664d3641ae8SIntel printf("done\n"); 665d3641ae8SIntel } 666d3641ae8SIntel } 667d3641ae8SIntel } 668d3641ae8SIntel 669af75078fSIntel int 670*98a16481SDavid Marchand main(int argc, char **argv) 671af75078fSIntel { 672af75078fSIntel struct lcore_queue_conf *qconf; 67381f7ecd9SPablo de Lara struct rte_eth_dev_info dev_info; 67481f7ecd9SPablo de Lara struct rte_eth_txconf *txconf; 675af75078fSIntel int ret; 676af75078fSIntel uint16_t queueid; 6779787d22fSIntel unsigned lcore_id = 0, rx_lcore_id = 0; 678af75078fSIntel uint32_t n_tx_queue, nb_lcores; 679af75078fSIntel uint8_t portid; 680af75078fSIntel 681af75078fSIntel /* init EAL */ 682af75078fSIntel ret = rte_eal_init(argc, argv); 683af75078fSIntel if (ret < 0) 684af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n"); 685af75078fSIntel argc -= ret; 686af75078fSIntel argv += ret; 687af75078fSIntel 688af75078fSIntel /* parse application arguments (after the EAL ones) */ 689af75078fSIntel ret = parse_args(argc, argv); 690af75078fSIntel if (ret < 0) 691af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid IPV4_MULTICAST parameters\n"); 692af75078fSIntel 693af75078fSIntel /* create the mbuf pools */ 694af75078fSIntel packet_pool = rte_mempool_create("packet_pool", NB_PKT_MBUF, 695af75078fSIntel PKT_MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private), 696af75078fSIntel rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL, 697e60f71ebSIntel rte_socket_id(), 0); 698af75078fSIntel 699af75078fSIntel if (packet_pool == NULL) 700af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init packet mbuf pool\n"); 701af75078fSIntel 702af75078fSIntel header_pool = rte_mempool_create("header_pool", NB_HDR_MBUF, 703af75078fSIntel HDR_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, 704e60f71ebSIntel rte_socket_id(), 0); 705af75078fSIntel 706af75078fSIntel if (header_pool == NULL) 707af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init header mbuf pool\n"); 708af75078fSIntel 709af75078fSIntel clone_pool = rte_mempool_create("clone_pool", NB_CLONE_MBUF, 710af75078fSIntel CLONE_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, 711e60f71ebSIntel rte_socket_id(), 0); 712af75078fSIntel 713af75078fSIntel if (clone_pool == NULL) 714af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init clone mbuf pool\n"); 715af75078fSIntel 716af75078fSIntel nb_ports = rte_eth_dev_count(); 717af75078fSIntel if (nb_ports == 0) 718af75078fSIntel rte_exit(EXIT_FAILURE, "No physical ports!\n"); 719af75078fSIntel if (nb_ports > MAX_PORTS) 720af75078fSIntel nb_ports = MAX_PORTS; 721af75078fSIntel 722af75078fSIntel nb_lcores = rte_lcore_count(); 723af75078fSIntel 724af75078fSIntel /* initialize all ports */ 725af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 726af75078fSIntel /* skip ports that are not enabled */ 727af75078fSIntel if ((enabled_port_mask & (1 << portid)) == 0) { 728af75078fSIntel printf("Skipping disabled port %d\n", portid); 729af75078fSIntel continue; 730af75078fSIntel } 731af75078fSIntel 732af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 733af75078fSIntel 734af75078fSIntel /* get the lcore_id for this port */ 735af75078fSIntel while (rte_lcore_is_enabled(rx_lcore_id) == 0 || 736af75078fSIntel qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) { 737af75078fSIntel 738af75078fSIntel rx_lcore_id ++; 739af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 740af75078fSIntel 741af75078fSIntel if (rx_lcore_id >= RTE_MAX_LCORE) 742af75078fSIntel rte_exit(EXIT_FAILURE, "Not enough cores\n"); 743af75078fSIntel } 744af75078fSIntel qconf->rx_queue_list[qconf->n_rx_queue] = portid; 745af75078fSIntel qconf->n_rx_queue++; 746af75078fSIntel 747af75078fSIntel /* init port */ 748af75078fSIntel printf("Initializing port %d on lcore %u... ", portid, 749af75078fSIntel rx_lcore_id); 750af75078fSIntel fflush(stdout); 751af75078fSIntel 752af75078fSIntel n_tx_queue = nb_lcores; 753af75078fSIntel if (n_tx_queue > MAX_TX_QUEUE_PER_PORT) 754af75078fSIntel n_tx_queue = MAX_TX_QUEUE_PER_PORT; 755af75078fSIntel ret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue, 756af75078fSIntel &port_conf); 757af75078fSIntel if (ret < 0) 758af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%d\n", 759af75078fSIntel ret, portid); 760af75078fSIntel 761af75078fSIntel rte_eth_macaddr_get(portid, &ports_eth_addr[portid]); 762af75078fSIntel print_ethaddr(" Address:", &ports_eth_addr[portid]); 763af75078fSIntel printf(", "); 764af75078fSIntel 765af75078fSIntel /* init one RX queue */ 766af75078fSIntel queueid = 0; 767af75078fSIntel printf("rxq=%hu ", queueid); 768af75078fSIntel fflush(stdout); 769af75078fSIntel ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd, 77081f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid), 77181f7ecd9SPablo de Lara NULL, 772af75078fSIntel packet_pool); 773af75078fSIntel if (ret < 0) 774af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, port=%d\n", 775af75078fSIntel ret, portid); 776af75078fSIntel 777af75078fSIntel /* init one TX queue per couple (lcore,port) */ 778af75078fSIntel queueid = 0; 779af75078fSIntel 780af75078fSIntel RTE_LCORE_FOREACH(lcore_id) { 781af75078fSIntel if (rte_lcore_is_enabled(lcore_id) == 0) 782af75078fSIntel continue; 783af75078fSIntel printf("txq=%u,%hu ", lcore_id, queueid); 784af75078fSIntel fflush(stdout); 78581f7ecd9SPablo de Lara 78681f7ecd9SPablo de Lara rte_eth_dev_info_get(portid, &dev_info); 78781f7ecd9SPablo de Lara txconf = &dev_info.default_txconf; 78881f7ecd9SPablo de Lara txconf->txq_flags = 0; 789af75078fSIntel ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd, 79081f7ecd9SPablo de Lara rte_lcore_to_socket_id(lcore_id), txconf); 791af75078fSIntel if (ret < 0) 792af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, " 793af75078fSIntel "port=%d\n", ret, portid); 794af75078fSIntel 795af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 796af75078fSIntel qconf->tx_queue_id[portid] = queueid; 797af75078fSIntel queueid++; 798af75078fSIntel } 799af75078fSIntel 800af75078fSIntel /* Start device */ 801af75078fSIntel ret = rte_eth_dev_start(portid); 802af75078fSIntel if (ret < 0) 803af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%d\n", 804af75078fSIntel ret, portid); 805af75078fSIntel 806d3641ae8SIntel printf("done:\n"); 807af75078fSIntel } 808af75078fSIntel 809d3641ae8SIntel check_all_ports_link_status(nb_ports, enabled_port_mask); 810af75078fSIntel 811af75078fSIntel /* initialize the multicast hash */ 812af75078fSIntel int retval = init_mcast_hash(); 813af75078fSIntel if (retval != 0) 814af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot build the multicast hash\n"); 815af75078fSIntel 816af75078fSIntel /* launch per-lcore init on every lcore */ 817af75078fSIntel rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER); 818af75078fSIntel RTE_LCORE_FOREACH_SLAVE(lcore_id) { 819af75078fSIntel if (rte_eal_wait_lcore(lcore_id) < 0) 820af75078fSIntel return -1; 821af75078fSIntel } 822af75078fSIntel 823af75078fSIntel return 0; 824af75078fSIntel } 825