xref: /dpdk/examples/ipv4_multicast/main.c (revision 9787d22f34c258ee78a038c58d78a8373d2012e0)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
4b6df9fc8SIntel  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #include <stdio.h>
35af75078fSIntel #include <stdlib.h>
36af75078fSIntel #include <stdint.h>
37af75078fSIntel #include <inttypes.h>
38af75078fSIntel #include <sys/types.h>
39af75078fSIntel #include <string.h>
40af75078fSIntel #include <sys/queue.h>
41af75078fSIntel #include <stdarg.h>
42af75078fSIntel #include <errno.h>
43af75078fSIntel #include <getopt.h>
44af75078fSIntel 
45af75078fSIntel #include <rte_common.h>
46af75078fSIntel #include <rte_byteorder.h>
47af75078fSIntel #include <rte_log.h>
48af75078fSIntel #include <rte_tailq.h>
49af75078fSIntel #include <rte_memory.h>
50af75078fSIntel #include <rte_memcpy.h>
51af75078fSIntel #include <rte_memzone.h>
52af75078fSIntel #include <rte_eal.h>
53af75078fSIntel #include <rte_per_lcore.h>
54af75078fSIntel #include <rte_launch.h>
55af75078fSIntel #include <rte_atomic.h>
56af75078fSIntel #include <rte_cycles.h>
57af75078fSIntel #include <rte_prefetch.h>
58af75078fSIntel #include <rte_lcore.h>
59af75078fSIntel #include <rte_per_lcore.h>
60af75078fSIntel #include <rte_branch_prediction.h>
61af75078fSIntel #include <rte_interrupts.h>
62af75078fSIntel #include <rte_pci.h>
63af75078fSIntel #include <rte_random.h>
64af75078fSIntel #include <rte_debug.h>
65af75078fSIntel #include <rte_ether.h>
66af75078fSIntel #include <rte_ethdev.h>
67af75078fSIntel #include <rte_ring.h>
68af75078fSIntel #include <rte_mempool.h>
69af75078fSIntel #include <rte_mbuf.h>
70af75078fSIntel #include <rte_malloc.h>
71af75078fSIntel #include <rte_fbk_hash.h>
72af75078fSIntel #include <rte_ip.h>
73af75078fSIntel 
74af75078fSIntel #include "main.h"
75af75078fSIntel 
76af75078fSIntel #define RTE_LOGTYPE_IPv4_MULTICAST RTE_LOGTYPE_USER1
77af75078fSIntel 
78af75078fSIntel #define MAX_PORTS 16
79af75078fSIntel 
80af75078fSIntel #define	MCAST_CLONE_PORTS	2
81af75078fSIntel #define	MCAST_CLONE_SEGS	2
82af75078fSIntel 
83af75078fSIntel #define	PKT_MBUF_SIZE	(2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
84af75078fSIntel #define	NB_PKT_MBUF	8192
85af75078fSIntel 
86af75078fSIntel #define	HDR_MBUF_SIZE	(sizeof(struct rte_mbuf) + 2 * RTE_PKTMBUF_HEADROOM)
87af75078fSIntel #define	NB_HDR_MBUF	(NB_PKT_MBUF * MAX_PORTS)
88af75078fSIntel 
89af75078fSIntel #define	CLONE_MBUF_SIZE	(sizeof(struct rte_mbuf))
90af75078fSIntel #define	NB_CLONE_MBUF	(NB_PKT_MBUF * MCAST_CLONE_PORTS * MCAST_CLONE_SEGS * 2)
91af75078fSIntel 
92af75078fSIntel /* allow max jumbo frame 9.5 KB */
93af75078fSIntel #define	JUMBO_FRAME_MAX_SIZE	0x2600
94af75078fSIntel 
95af75078fSIntel /*
96af75078fSIntel  * RX and TX Prefetch, Host, and Write-back threshold values should be
97af75078fSIntel  * carefully set for optimal performance. Consult the network
98af75078fSIntel  * controller's datasheet and supporting DPDK documentation for guidance
99af75078fSIntel  * on how these parameters should be set.
100af75078fSIntel  */
101af75078fSIntel #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
102af75078fSIntel #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
103af75078fSIntel #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
104af75078fSIntel 
105af75078fSIntel /*
106af75078fSIntel  * These default values are optimized for use with the Intel(R) 82599 10 GbE
107af75078fSIntel  * Controller and the DPDK ixgbe PMD. Consider using other values for other
108af75078fSIntel  * network controllers and/or network drivers.
109af75078fSIntel  */
110af75078fSIntel #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
111af75078fSIntel #define TX_HTHRESH 0  /**< Default values of TX host threshold reg. */
112af75078fSIntel #define TX_WTHRESH 0  /**< Default values of TX write-back threshold reg. */
113af75078fSIntel 
114af75078fSIntel #define MAX_PKT_BURST 32
1155c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
116af75078fSIntel 
117af75078fSIntel /* Configure how many packets ahead to prefetch, when reading packets */
118af75078fSIntel #define PREFETCH_OFFSET	3
119af75078fSIntel 
120af75078fSIntel /*
121af75078fSIntel  * Construct Ethernet multicast address from IPv4 multicast address.
122af75078fSIntel  * Citing RFC 1112, section 6.4:
123af75078fSIntel  * "An IP host group address is mapped to an Ethernet multicast address
124af75078fSIntel  * by placing the low-order 23-bits of the IP address into the low-order
125af75078fSIntel  * 23 bits of the Ethernet multicast address 01-00-5E-00-00-00 (hex)."
126af75078fSIntel  */
127af75078fSIntel #define	ETHER_ADDR_FOR_IPV4_MCAST(x)	\
128af75078fSIntel 	(rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16)
129af75078fSIntel 
130af75078fSIntel /*
131af75078fSIntel  * Configurable number of RX/TX ring descriptors
132af75078fSIntel  */
133af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128
134af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512
135af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
136af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
137af75078fSIntel 
138af75078fSIntel /* ethernet addresses of ports */
139af75078fSIntel static struct ether_addr ports_eth_addr[MAX_PORTS];
140af75078fSIntel 
141af75078fSIntel /* mask of enabled ports */
142af75078fSIntel static uint32_t enabled_port_mask = 0;
143af75078fSIntel 
144af75078fSIntel static uint8_t nb_ports = 0;
145af75078fSIntel 
146af75078fSIntel static int rx_queue_per_lcore = 1;
147af75078fSIntel 
148af75078fSIntel struct mbuf_table {
149af75078fSIntel 	uint16_t len;
150af75078fSIntel 	struct rte_mbuf *m_table[MAX_PKT_BURST];
151af75078fSIntel };
152af75078fSIntel 
153af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16
154af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16
155af75078fSIntel struct lcore_queue_conf {
156af75078fSIntel 	uint64_t tx_tsc;
157af75078fSIntel 	uint16_t n_rx_queue;
158af75078fSIntel 	uint8_t rx_queue_list[MAX_RX_QUEUE_PER_LCORE];
159af75078fSIntel 	uint16_t tx_queue_id[MAX_PORTS];
160af75078fSIntel 	struct mbuf_table tx_mbufs[MAX_PORTS];
161af75078fSIntel } __rte_cache_aligned;
162af75078fSIntel static struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];
163af75078fSIntel 
164af75078fSIntel static const struct rte_eth_conf port_conf = {
165af75078fSIntel 	.rxmode = {
166af75078fSIntel 		.max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE,
167af75078fSIntel 		.split_hdr_size = 0,
168af75078fSIntel 		.header_split   = 0, /**< Header Split disabled */
169af75078fSIntel 		.hw_ip_checksum = 0, /**< IP checksum offload disabled */
170af75078fSIntel 		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
171af75078fSIntel 		.jumbo_frame    = 1, /**< Jumbo Frame Support enabled */
172af75078fSIntel 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
173af75078fSIntel 	},
174af75078fSIntel 	.txmode = {
17532e7aa0bSIntel 		.mq_mode = ETH_MQ_TX_NONE,
176af75078fSIntel 	},
177af75078fSIntel };
178af75078fSIntel 
179af75078fSIntel static const struct rte_eth_rxconf rx_conf = {
180af75078fSIntel 	.rx_thresh = {
181af75078fSIntel 		.pthresh = RX_PTHRESH,
182af75078fSIntel 		.hthresh = RX_HTHRESH,
183af75078fSIntel 		.wthresh = RX_WTHRESH,
184af75078fSIntel 	},
185af75078fSIntel };
186af75078fSIntel 
187af75078fSIntel static const struct rte_eth_txconf tx_conf = {
188af75078fSIntel 	.tx_thresh = {
189af75078fSIntel 		.pthresh = TX_PTHRESH,
190af75078fSIntel 		.hthresh = TX_HTHRESH,
191af75078fSIntel 		.wthresh = TX_WTHRESH,
192af75078fSIntel 	},
193af75078fSIntel 	.tx_free_thresh = 0, /* Use PMD default values */
194af75078fSIntel 	.tx_rs_thresh = 0, /* Use PMD default values */
195af75078fSIntel };
196af75078fSIntel 
197af75078fSIntel static struct rte_mempool *packet_pool, *header_pool, *clone_pool;
198af75078fSIntel 
199af75078fSIntel 
200af75078fSIntel /* Multicast */
201af75078fSIntel static struct rte_fbk_hash_params mcast_hash_params = {
202af75078fSIntel 	.name = "MCAST_HASH",
203af75078fSIntel 	.entries = 1024,
204af75078fSIntel 	.entries_per_bucket = 4,
205e60f71ebSIntel 	.socket_id = 0,
206af75078fSIntel 	.hash_func = NULL,
207af75078fSIntel 	.init_val = 0,
208af75078fSIntel };
209af75078fSIntel 
210af75078fSIntel struct rte_fbk_hash_table *mcast_hash = NULL;
211af75078fSIntel 
212af75078fSIntel struct mcast_group_params {
213af75078fSIntel 	uint32_t ip;
214af75078fSIntel 	uint16_t port_mask;
215af75078fSIntel };
216af75078fSIntel 
217af75078fSIntel static struct mcast_group_params mcast_group_table[] = {
218af75078fSIntel 		{IPv4(224,0,0,101), 0x1},
219af75078fSIntel 		{IPv4(224,0,0,102), 0x2},
220af75078fSIntel 		{IPv4(224,0,0,103), 0x3},
221af75078fSIntel 		{IPv4(224,0,0,104), 0x4},
222af75078fSIntel 		{IPv4(224,0,0,105), 0x5},
223af75078fSIntel 		{IPv4(224,0,0,106), 0x6},
224af75078fSIntel 		{IPv4(224,0,0,107), 0x7},
225af75078fSIntel 		{IPv4(224,0,0,108), 0x8},
226af75078fSIntel 		{IPv4(224,0,0,109), 0x9},
227af75078fSIntel 		{IPv4(224,0,0,110), 0xA},
228af75078fSIntel 		{IPv4(224,0,0,111), 0xB},
229af75078fSIntel 		{IPv4(224,0,0,112), 0xC},
230af75078fSIntel 		{IPv4(224,0,0,113), 0xD},
231af75078fSIntel 		{IPv4(224,0,0,114), 0xE},
232af75078fSIntel 		{IPv4(224,0,0,115), 0xF},
233af75078fSIntel };
234af75078fSIntel 
235af75078fSIntel #define N_MCAST_GROUPS \
236af75078fSIntel 	(sizeof (mcast_group_table) / sizeof (mcast_group_table[0]))
237af75078fSIntel 
238af75078fSIntel 
239af75078fSIntel /* Send burst of packets on an output interface */
240af75078fSIntel static void
241af75078fSIntel send_burst(struct lcore_queue_conf *qconf, uint8_t port)
242af75078fSIntel {
243af75078fSIntel 	struct rte_mbuf **m_table;
244af75078fSIntel 	uint16_t n, queueid;
245af75078fSIntel 	int ret;
246af75078fSIntel 
247af75078fSIntel 	queueid = qconf->tx_queue_id[port];
248af75078fSIntel 	m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;
249af75078fSIntel 	n = qconf->tx_mbufs[port].len;
250af75078fSIntel 
251af75078fSIntel 	ret = rte_eth_tx_burst(port, queueid, m_table, n);
252af75078fSIntel 	while (unlikely (ret < n)) {
253af75078fSIntel 		rte_pktmbuf_free(m_table[ret]);
254af75078fSIntel 		ret++;
255af75078fSIntel 	}
256af75078fSIntel 
257af75078fSIntel 	qconf->tx_mbufs[port].len = 0;
258af75078fSIntel }
259af75078fSIntel 
260af75078fSIntel /* Get number of bits set. */
261af75078fSIntel static inline uint32_t
262af75078fSIntel bitcnt(uint32_t v)
263af75078fSIntel {
264af75078fSIntel 	uint32_t n;
265af75078fSIntel 
266af75078fSIntel 	for (n = 0; v != 0; v &= v - 1, n++)
267af75078fSIntel 		;
268af75078fSIntel 
269af75078fSIntel 	return (n);
270af75078fSIntel }
271af75078fSIntel 
272af75078fSIntel /**
273af75078fSIntel  * Create the output multicast packet based on the given input packet.
274af75078fSIntel  * There are two approaches for creating outgoing packet, though both
275af75078fSIntel  * are based on data zero-copy idea, they differ in few details:
276af75078fSIntel  * First one creates a clone of the input packet, e.g - walk though all
277af75078fSIntel  * segments of the input packet, and for each of them create a new packet
278af75078fSIntel  * mbuf and attach that new mbuf to the segment (refer to rte_pktmbuf_clone()
279af75078fSIntel  * for more details). Then new mbuf is allocated for the packet header
280af75078fSIntel  * and is prepended to the 'clone' mbuf.
281af75078fSIntel  * Second approach doesn't make a clone, it just increment refcnt for all
282af75078fSIntel  * input packet segments. Then it allocates new mbuf for the packet header
283af75078fSIntel  * and prepends it to the input packet.
284af75078fSIntel  * Basically first approach reuses only input packet's data, but creates
285af75078fSIntel  * it's own copy of packet's metadata. Second approach reuses both input's
286af75078fSIntel  * packet data and metadata.
287af75078fSIntel  * The advantage of first approach - is that each outgoing packet has it's
288af75078fSIntel  * own copy of metadata, so we can safely modify data pointer of the
289af75078fSIntel  * input packet. That allows us to skip creation if the output packet for
290af75078fSIntel  * the last destination port, but instead modify input packet's header inplace,
291af75078fSIntel  * e.g: for N destination ports we need to invoke mcast_out_pkt (N-1) times.
292af75078fSIntel  * The advantage of second approach - less work for each outgoing packet,
293af75078fSIntel  * e.g: we skip "clone" operation completely. Though it comes with a price -
294af75078fSIntel  * input packet's metadata has to be intact. So for N destination ports we
295af75078fSIntel  * need to invoke mcast_out_pkt N times.
296af75078fSIntel  * So for small number of outgoing ports (and segments in the input packet)
297af75078fSIntel  * first approach will be faster.
298af75078fSIntel  * As number of outgoing ports (and/or input segments) will grow,
299af75078fSIntel  * second way will become more preferable.
300af75078fSIntel  *
301af75078fSIntel  *  @param pkt
302af75078fSIntel  *  Input packet mbuf.
303af75078fSIntel  *  @param use_clone
304af75078fSIntel  *  Control which of the two approaches described above should be used:
305af75078fSIntel  *  - 0 - use second approach:
306af75078fSIntel  *    Don't "clone" input packet.
307af75078fSIntel  *    Prepend new header directly to the input packet
308af75078fSIntel  *  - 1 - use first approach:
309af75078fSIntel  *    Make a "clone" of input packet first.
310af75078fSIntel  *    Prepend new header to the clone of the input packet
311af75078fSIntel  *  @return
312af75078fSIntel  *  - The pointer to the new outgoing packet.
313af75078fSIntel  *  - NULL if operation failed.
314af75078fSIntel  */
315af75078fSIntel static inline struct rte_mbuf *
316af75078fSIntel mcast_out_pkt(struct rte_mbuf *pkt, int use_clone)
317af75078fSIntel {
318af75078fSIntel 	struct rte_mbuf *hdr;
319af75078fSIntel 
320af75078fSIntel 	/* Create new mbuf for the header. */
321af75078fSIntel 	if (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL))
322af75078fSIntel 		return (NULL);
323af75078fSIntel 
324af75078fSIntel 	/* If requested, then make a new clone packet. */
325af75078fSIntel 	if (use_clone != 0 &&
326af75078fSIntel 	    unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) {
327af75078fSIntel 		rte_pktmbuf_free(hdr);
328af75078fSIntel 		return (NULL);
329af75078fSIntel 	}
330af75078fSIntel 
331af75078fSIntel 	/* prepend new header */
332af75078fSIntel 	hdr->pkt.next = pkt;
333af75078fSIntel 
334af75078fSIntel 
335af75078fSIntel 	/* update header's fields */
336af75078fSIntel 	hdr->pkt.pkt_len = (uint16_t)(hdr->pkt.data_len + pkt->pkt.pkt_len);
337af75078fSIntel 	hdr->pkt.nb_segs = (uint8_t)(pkt->pkt.nb_segs + 1);
338af75078fSIntel 
339af75078fSIntel 	/* copy metadata from source packet*/
340af75078fSIntel 	hdr->pkt.in_port = pkt->pkt.in_port;
34142d71416SIntel 	hdr->pkt.vlan_macip = pkt->pkt.vlan_macip;
342af75078fSIntel 	hdr->pkt.hash = pkt->pkt.hash;
343af75078fSIntel 
344af75078fSIntel 	hdr->ol_flags = pkt->ol_flags;
345af75078fSIntel 
346af75078fSIntel 	__rte_mbuf_sanity_check(hdr, RTE_MBUF_PKT, 1);
347af75078fSIntel 	return (hdr);
348af75078fSIntel }
349af75078fSIntel 
350af75078fSIntel /*
351af75078fSIntel  * Write new Ethernet header to the outgoing packet,
352af75078fSIntel  * and put it into the outgoing queue for the given port.
353af75078fSIntel  */
354af75078fSIntel static inline void
355af75078fSIntel mcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr,
356af75078fSIntel 		struct lcore_queue_conf *qconf, uint8_t port)
357af75078fSIntel {
358af75078fSIntel 	struct ether_hdr *ethdr;
359af75078fSIntel 	uint16_t len;
360af75078fSIntel 
361af75078fSIntel 	/* Construct Ethernet header. */
362af75078fSIntel 	ethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(*ethdr));
363af75078fSIntel 	RTE_MBUF_ASSERT(ethdr != NULL);
364af75078fSIntel 
365af75078fSIntel 	ether_addr_copy(dest_addr, &ethdr->d_addr);
366af75078fSIntel 	ether_addr_copy(&ports_eth_addr[port], &ethdr->s_addr);
367af75078fSIntel 	ethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);
368af75078fSIntel 
369af75078fSIntel 	/* Put new packet into the output queue */
370af75078fSIntel 	len = qconf->tx_mbufs[port].len;
371af75078fSIntel 	qconf->tx_mbufs[port].m_table[len] = pkt;
372af75078fSIntel 	qconf->tx_mbufs[port].len = ++len;
373af75078fSIntel 
374af75078fSIntel 	/* Transmit packets */
375af75078fSIntel 	if (unlikely(MAX_PKT_BURST == len))
376af75078fSIntel 		send_burst(qconf, port);
377af75078fSIntel }
378af75078fSIntel 
379af75078fSIntel /* Multicast forward of the input packet */
380af75078fSIntel static inline void
381af75078fSIntel mcast_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf)
382af75078fSIntel {
383af75078fSIntel 	struct rte_mbuf *mc;
384af75078fSIntel 	struct ipv4_hdr *iphdr;
385af75078fSIntel 	uint32_t dest_addr, port_mask, port_num, use_clone;
386af75078fSIntel 	int32_t hash;
387af75078fSIntel 	uint8_t port;
388af75078fSIntel 	union {
389af75078fSIntel 		uint64_t as_int;
390af75078fSIntel 		struct ether_addr as_addr;
391af75078fSIntel 	} dst_eth_addr;
392af75078fSIntel 
393af75078fSIntel 	/* Remove the Ethernet header from the input packet */
394af75078fSIntel 	iphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr));
395af75078fSIntel 	RTE_MBUF_ASSERT(iphdr != NULL);
396af75078fSIntel 
397af75078fSIntel 	dest_addr = rte_be_to_cpu_32(iphdr->dst_addr);
398af75078fSIntel 
399af75078fSIntel 	/*
400af75078fSIntel 	 * Check that it is a valid multicast address and
401af75078fSIntel 	 * we have some active ports assigned to it.
402af75078fSIntel 	 */
403af75078fSIntel 	if(!IS_IPV4_MCAST(dest_addr) ||
404af75078fSIntel 	    (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 ||
405af75078fSIntel 	    (port_mask = hash & enabled_port_mask) == 0) {
406af75078fSIntel 		rte_pktmbuf_free(m);
407af75078fSIntel 		return;
408af75078fSIntel 	}
409af75078fSIntel 
410af75078fSIntel 	/* Calculate number of destination ports. */
411af75078fSIntel 	port_num = bitcnt(port_mask);
412af75078fSIntel 
413af75078fSIntel 	/* Should we use rte_pktmbuf_clone() or not. */
414af75078fSIntel 	use_clone = (port_num <= MCAST_CLONE_PORTS &&
415af75078fSIntel 	    m->pkt.nb_segs <= MCAST_CLONE_SEGS);
416af75078fSIntel 
417af75078fSIntel 	/* Mark all packet's segments as referenced port_num times */
418af75078fSIntel 	if (use_clone == 0)
419af75078fSIntel 		rte_pktmbuf_refcnt_update(m, (uint16_t)port_num);
420af75078fSIntel 
421af75078fSIntel 	/* construct destination ethernet address */
422af75078fSIntel 	dst_eth_addr.as_int = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr);
423af75078fSIntel 
424af75078fSIntel 	for (port = 0; use_clone != port_mask; port_mask >>= 1, port++) {
425af75078fSIntel 
426af75078fSIntel 		/* Prepare output packet and send it out. */
427af75078fSIntel 		if ((port_mask & 1) != 0) {
428af75078fSIntel 			if (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL))
429af75078fSIntel 				mcast_send_pkt(mc, &dst_eth_addr.as_addr,
430af75078fSIntel 						qconf, port);
431af75078fSIntel 			else if (use_clone == 0)
432af75078fSIntel 				rte_pktmbuf_free(m);
433af75078fSIntel 		}
434af75078fSIntel 	}
435af75078fSIntel 
436af75078fSIntel 	/*
437af75078fSIntel 	 * If we making clone packets, then, for the last destination port,
438af75078fSIntel 	 * we can overwrite input packet's metadata.
439af75078fSIntel 	 */
440af75078fSIntel 	if (use_clone != 0)
441af75078fSIntel 		mcast_send_pkt(m, &dst_eth_addr.as_addr, qconf, port);
442af75078fSIntel 	else
443af75078fSIntel 		rte_pktmbuf_free(m);
444af75078fSIntel }
445af75078fSIntel 
446af75078fSIntel /* Send burst of outgoing packet, if timeout expires. */
447af75078fSIntel static inline void
448af75078fSIntel send_timeout_burst(struct lcore_queue_conf *qconf)
449af75078fSIntel {
450af75078fSIntel 	uint64_t cur_tsc;
451af75078fSIntel 	uint8_t portid;
4525c95261dSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
453af75078fSIntel 
454af75078fSIntel 	cur_tsc = rte_rdtsc();
4555c95261dSIntel 	if (likely (cur_tsc < qconf->tx_tsc + drain_tsc))
456af75078fSIntel 		return;
457af75078fSIntel 
458af75078fSIntel 	for (portid = 0; portid < MAX_PORTS; portid++) {
459af75078fSIntel 		if (qconf->tx_mbufs[portid].len != 0)
460af75078fSIntel 			send_burst(qconf, portid);
461af75078fSIntel 	}
462af75078fSIntel 	qconf->tx_tsc = cur_tsc;
463af75078fSIntel }
464af75078fSIntel 
465af75078fSIntel /* main processing loop */
466cdfd5dbbSIntel static int
467af75078fSIntel main_loop(__rte_unused void *dummy)
468af75078fSIntel {
469af75078fSIntel 	struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
4706441b9f6SIntel 	unsigned lcore_id;
471af75078fSIntel 	int i, j, nb_rx;
472af75078fSIntel 	uint8_t portid;
473af75078fSIntel 	struct lcore_queue_conf *qconf;
474af75078fSIntel 
475af75078fSIntel 	lcore_id = rte_lcore_id();
476af75078fSIntel 	qconf = &lcore_queue_conf[lcore_id];
477af75078fSIntel 
478af75078fSIntel 
479af75078fSIntel 	if (qconf->n_rx_queue == 0) {
480af75078fSIntel 		RTE_LOG(INFO, IPv4_MULTICAST, "lcore %u has nothing to do\n",
481af75078fSIntel 		    lcore_id);
482cdfd5dbbSIntel 		return 0;
483af75078fSIntel 	}
484af75078fSIntel 
485af75078fSIntel 	RTE_LOG(INFO, IPv4_MULTICAST, "entering main loop on lcore %u\n",
486af75078fSIntel 	    lcore_id);
487af75078fSIntel 
488af75078fSIntel 	for (i = 0; i < qconf->n_rx_queue; i++) {
489af75078fSIntel 
490af75078fSIntel 		portid = qconf->rx_queue_list[i];
491af75078fSIntel 		RTE_LOG(INFO, IPv4_MULTICAST, " -- lcoreid=%u portid=%d\n",
492af75078fSIntel 		    lcore_id, (int) portid);
493af75078fSIntel 	}
494af75078fSIntel 
495af75078fSIntel 	while (1) {
496af75078fSIntel 
497af75078fSIntel 		/*
498af75078fSIntel 		 * Read packet from RX queues
499af75078fSIntel 		 */
500af75078fSIntel 		for (i = 0; i < qconf->n_rx_queue; i++) {
501af75078fSIntel 
502af75078fSIntel 			portid = qconf->rx_queue_list[i];
503af75078fSIntel 			nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst,
504af75078fSIntel 						 MAX_PKT_BURST);
505af75078fSIntel 
506af75078fSIntel 			/* Prefetch first packets */
507af75078fSIntel 			for (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {
508af75078fSIntel 				rte_prefetch0(rte_pktmbuf_mtod(
509af75078fSIntel 						pkts_burst[j], void *));
510af75078fSIntel 			}
511af75078fSIntel 
512af75078fSIntel 			/* Prefetch and forward already prefetched packets */
513af75078fSIntel 			for (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {
514af75078fSIntel 				rte_prefetch0(rte_pktmbuf_mtod(pkts_burst[
515af75078fSIntel 						j + PREFETCH_OFFSET], void *));
516af75078fSIntel 				mcast_forward(pkts_burst[j], qconf);
517af75078fSIntel 			}
518af75078fSIntel 
519af75078fSIntel 			/* Forward remaining prefetched packets */
520af75078fSIntel 			for (; j < nb_rx; j++) {
521af75078fSIntel 				mcast_forward(pkts_burst[j], qconf);
522af75078fSIntel 			}
523af75078fSIntel 		}
524af75078fSIntel 
525af75078fSIntel 		/* Send out packets from TX queues */
526af75078fSIntel 		send_timeout_burst(qconf);
527af75078fSIntel 	}
528af75078fSIntel }
529af75078fSIntel 
530af75078fSIntel /* display usage */
531af75078fSIntel static void
532af75078fSIntel print_usage(const char *prgname)
533af75078fSIntel {
534af75078fSIntel 	printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n"
535af75078fSIntel 	    "  -p PORTMASK: hexadecimal bitmask of ports to configure\n"
536af75078fSIntel 	    "  -q NQ: number of queue (=ports) per lcore (default is 1)\n",
537af75078fSIntel 	    prgname);
538af75078fSIntel }
539af75078fSIntel 
540af75078fSIntel static uint32_t
541af75078fSIntel parse_portmask(const char *portmask)
542af75078fSIntel {
543af75078fSIntel 	char *end = NULL;
544af75078fSIntel 	unsigned long pm;
545af75078fSIntel 
546af75078fSIntel 	/* parse hexadecimal string */
547af75078fSIntel 	pm = strtoul(portmask, &end, 16);
548af75078fSIntel 	if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
549af75078fSIntel 		return 0;
550af75078fSIntel 
551af75078fSIntel 	return ((uint32_t)pm);
552af75078fSIntel }
553af75078fSIntel 
554af75078fSIntel static int
555af75078fSIntel parse_nqueue(const char *q_arg)
556af75078fSIntel {
557af75078fSIntel 	char *end = NULL;
558af75078fSIntel 	unsigned long n;
559af75078fSIntel 
560af75078fSIntel 	/* parse numerical string */
561af75078fSIntel 	errno = 0;
562af75078fSIntel 	n = strtoul(q_arg, &end, 0);
563af75078fSIntel 	if (errno != 0 || end == NULL || *end != '\0' ||
564af75078fSIntel 			n == 0 || n >= MAX_RX_QUEUE_PER_LCORE)
565af75078fSIntel 		return (-1);
566af75078fSIntel 
567af75078fSIntel 	return (n);
568af75078fSIntel }
569af75078fSIntel 
570af75078fSIntel /* Parse the argument given in the command line of the application */
571af75078fSIntel static int
572af75078fSIntel parse_args(int argc, char **argv)
573af75078fSIntel {
574af75078fSIntel 	int opt, ret;
575af75078fSIntel 	char **argvopt;
576af75078fSIntel 	int option_index;
577af75078fSIntel 	char *prgname = argv[0];
578af75078fSIntel 	static struct option lgopts[] = {
579af75078fSIntel 		{NULL, 0, 0, 0}
580af75078fSIntel 	};
581af75078fSIntel 
582af75078fSIntel 	argvopt = argv;
583af75078fSIntel 
584af75078fSIntel 	while ((opt = getopt_long(argc, argvopt, "p:q:",
585af75078fSIntel 				  lgopts, &option_index)) != EOF) {
586af75078fSIntel 
587af75078fSIntel 		switch (opt) {
588af75078fSIntel 		/* portmask */
589af75078fSIntel 		case 'p':
590af75078fSIntel 			enabled_port_mask = parse_portmask(optarg);
591af75078fSIntel 			if (enabled_port_mask == 0) {
592af75078fSIntel 				printf("invalid portmask\n");
593af75078fSIntel 				print_usage(prgname);
594af75078fSIntel 				return -1;
595af75078fSIntel 			}
596af75078fSIntel 			break;
597af75078fSIntel 
598af75078fSIntel 		/* nqueue */
599af75078fSIntel 		case 'q':
600af75078fSIntel 			rx_queue_per_lcore = parse_nqueue(optarg);
601af75078fSIntel 			if (rx_queue_per_lcore < 0) {
602af75078fSIntel 				printf("invalid queue number\n");
603af75078fSIntel 				print_usage(prgname);
604af75078fSIntel 				return -1;
605af75078fSIntel 			}
606af75078fSIntel 			break;
607af75078fSIntel 
608af75078fSIntel 		default:
609af75078fSIntel 			print_usage(prgname);
610af75078fSIntel 			return -1;
611af75078fSIntel 		}
612af75078fSIntel 	}
613af75078fSIntel 
614af75078fSIntel 	if (optind >= 0)
615af75078fSIntel 		argv[optind-1] = prgname;
616af75078fSIntel 
617af75078fSIntel 	ret = optind-1;
618af75078fSIntel 	optind = 0; /* reset getopt lib */
619af75078fSIntel 	return ret;
620af75078fSIntel }
621af75078fSIntel 
622af75078fSIntel static void
623af75078fSIntel print_ethaddr(const char *name, struct ether_addr *eth_addr)
624af75078fSIntel {
625af75078fSIntel 	printf("%s%02X:%02X:%02X:%02X:%02X:%02X", name,
626af75078fSIntel 	       eth_addr->addr_bytes[0],
627af75078fSIntel 	       eth_addr->addr_bytes[1],
628af75078fSIntel 	       eth_addr->addr_bytes[2],
629af75078fSIntel 	       eth_addr->addr_bytes[3],
630af75078fSIntel 	       eth_addr->addr_bytes[4],
631af75078fSIntel 	       eth_addr->addr_bytes[5]);
632af75078fSIntel }
633af75078fSIntel 
634af75078fSIntel static int
635af75078fSIntel init_mcast_hash(void)
636af75078fSIntel {
637af75078fSIntel 	uint32_t i;
638af75078fSIntel 
639e60f71ebSIntel 	mcast_hash_params.socket_id = rte_socket_id();
640af75078fSIntel 	mcast_hash = rte_fbk_hash_create(&mcast_hash_params);
641af75078fSIntel 	if (mcast_hash == NULL){
642af75078fSIntel 		return -1;
643af75078fSIntel 	}
644af75078fSIntel 
645af75078fSIntel 	for (i = 0; i < N_MCAST_GROUPS; i ++){
646af75078fSIntel 		if (rte_fbk_hash_add_key(mcast_hash,
647af75078fSIntel 			mcast_group_table[i].ip,
648af75078fSIntel 			mcast_group_table[i].port_mask) < 0) {
649af75078fSIntel 			return -1;
650af75078fSIntel 		}
651af75078fSIntel 	}
652af75078fSIntel 
653af75078fSIntel 	return 0;
654af75078fSIntel }
655af75078fSIntel 
656d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */
657d3641ae8SIntel static void
658d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask)
659d3641ae8SIntel {
660d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */
661d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
662d3641ae8SIntel 	uint8_t portid, count, all_ports_up, print_flag = 0;
663d3641ae8SIntel 	struct rte_eth_link link;
664d3641ae8SIntel 
665d3641ae8SIntel 	printf("\nChecking link status");
666d3641ae8SIntel 	fflush(stdout);
667d3641ae8SIntel 	for (count = 0; count <= MAX_CHECK_TIME; count++) {
668d3641ae8SIntel 		all_ports_up = 1;
669d3641ae8SIntel 		for (portid = 0; portid < port_num; portid++) {
670d3641ae8SIntel 			if ((port_mask & (1 << portid)) == 0)
671d3641ae8SIntel 				continue;
672d3641ae8SIntel 			memset(&link, 0, sizeof(link));
673d3641ae8SIntel 			rte_eth_link_get_nowait(portid, &link);
674d3641ae8SIntel 			/* print link status if flag set */
675d3641ae8SIntel 			if (print_flag == 1) {
676d3641ae8SIntel 				if (link.link_status)
677d3641ae8SIntel 					printf("Port %d Link Up - speed %u "
678d3641ae8SIntel 						"Mbps - %s\n", (uint8_t)portid,
679d3641ae8SIntel 						(unsigned)link.link_speed,
680d3641ae8SIntel 				(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
681d3641ae8SIntel 					("full-duplex") : ("half-duplex\n"));
682d3641ae8SIntel 				else
683d3641ae8SIntel 					printf("Port %d Link Down\n",
684d3641ae8SIntel 							(uint8_t)portid);
685d3641ae8SIntel 				continue;
686d3641ae8SIntel 			}
687d3641ae8SIntel 			/* clear all_ports_up flag if any link down */
688d3641ae8SIntel 			if (link.link_status == 0) {
689d3641ae8SIntel 				all_ports_up = 0;
690d3641ae8SIntel 				break;
691d3641ae8SIntel 			}
692d3641ae8SIntel 		}
693d3641ae8SIntel 		/* after finally printing all link status, get out */
694d3641ae8SIntel 		if (print_flag == 1)
695d3641ae8SIntel 			break;
696d3641ae8SIntel 
697d3641ae8SIntel 		if (all_ports_up == 0) {
698d3641ae8SIntel 			printf(".");
699d3641ae8SIntel 			fflush(stdout);
700d3641ae8SIntel 			rte_delay_ms(CHECK_INTERVAL);
701d3641ae8SIntel 		}
702d3641ae8SIntel 
703d3641ae8SIntel 		/* set the print_flag if all ports up or timeout */
704d3641ae8SIntel 		if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
705d3641ae8SIntel 			print_flag = 1;
706d3641ae8SIntel 			printf("done\n");
707d3641ae8SIntel 		}
708d3641ae8SIntel 	}
709d3641ae8SIntel }
710d3641ae8SIntel 
711af75078fSIntel int
712af75078fSIntel MAIN(int argc, char **argv)
713af75078fSIntel {
714af75078fSIntel 	struct lcore_queue_conf *qconf;
715af75078fSIntel 	int ret;
716af75078fSIntel 	uint16_t queueid;
717*9787d22fSIntel 	unsigned lcore_id = 0, rx_lcore_id = 0;
718af75078fSIntel 	uint32_t n_tx_queue, nb_lcores;
719af75078fSIntel 	uint8_t portid;
720af75078fSIntel 
721af75078fSIntel 	/* init EAL */
722af75078fSIntel 	ret = rte_eal_init(argc, argv);
723af75078fSIntel 	if (ret < 0)
724af75078fSIntel 		rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n");
725af75078fSIntel 	argc -= ret;
726af75078fSIntel 	argv += ret;
727af75078fSIntel 
728af75078fSIntel 	/* parse application arguments (after the EAL ones) */
729af75078fSIntel 	ret = parse_args(argc, argv);
730af75078fSIntel 	if (ret < 0)
731af75078fSIntel 		rte_exit(EXIT_FAILURE, "Invalid IPV4_MULTICAST parameters\n");
732af75078fSIntel 
733af75078fSIntel 	/* create the mbuf pools */
734af75078fSIntel 	packet_pool = rte_mempool_create("packet_pool", NB_PKT_MBUF,
735af75078fSIntel 	    PKT_MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private),
736af75078fSIntel 	    rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL,
737e60f71ebSIntel 	    rte_socket_id(), 0);
738af75078fSIntel 
739af75078fSIntel 	if (packet_pool == NULL)
740af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init packet mbuf pool\n");
741af75078fSIntel 
742af75078fSIntel 	header_pool = rte_mempool_create("header_pool", NB_HDR_MBUF,
743af75078fSIntel 	    HDR_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL,
744e60f71ebSIntel 	    rte_socket_id(), 0);
745af75078fSIntel 
746af75078fSIntel 	if (header_pool == NULL)
747af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init header mbuf pool\n");
748af75078fSIntel 
749af75078fSIntel 	clone_pool = rte_mempool_create("clone_pool", NB_CLONE_MBUF,
750af75078fSIntel 	    CLONE_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL,
751e60f71ebSIntel 	    rte_socket_id(), 0);
752af75078fSIntel 
753af75078fSIntel 	if (clone_pool == NULL)
754af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot init clone mbuf pool\n");
755af75078fSIntel 
756af75078fSIntel 	/* init driver */
75769d22b8eSIntel 	if (rte_pmd_init_all() < 0)
75869d22b8eSIntel 		rte_exit(EXIT_FAILURE, "Cannot init pmd\n");
759af75078fSIntel 
760af75078fSIntel 	if (rte_eal_pci_probe() < 0)
761af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot probe PCI\n");
762af75078fSIntel 
763af75078fSIntel 	nb_ports = rte_eth_dev_count();
764af75078fSIntel 	if (nb_ports == 0)
765af75078fSIntel 		rte_exit(EXIT_FAILURE, "No physical ports!\n");
766af75078fSIntel 	if (nb_ports > MAX_PORTS)
767af75078fSIntel 		nb_ports = MAX_PORTS;
768af75078fSIntel 
769af75078fSIntel 	nb_lcores = rte_lcore_count();
770af75078fSIntel 
771af75078fSIntel 	/* initialize all ports */
772af75078fSIntel 	for (portid = 0; portid < nb_ports; portid++) {
773af75078fSIntel 		/* skip ports that are not enabled */
774af75078fSIntel 		if ((enabled_port_mask & (1 << portid)) == 0) {
775af75078fSIntel 			printf("Skipping disabled port %d\n", portid);
776af75078fSIntel 			continue;
777af75078fSIntel 		}
778af75078fSIntel 
779af75078fSIntel 		qconf = &lcore_queue_conf[rx_lcore_id];
780af75078fSIntel 
781af75078fSIntel 		/* get the lcore_id for this port */
782af75078fSIntel 		while (rte_lcore_is_enabled(rx_lcore_id) == 0 ||
783af75078fSIntel 		       qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) {
784af75078fSIntel 
785af75078fSIntel 			rx_lcore_id ++;
786af75078fSIntel 			qconf = &lcore_queue_conf[rx_lcore_id];
787af75078fSIntel 
788af75078fSIntel 			if (rx_lcore_id >= RTE_MAX_LCORE)
789af75078fSIntel 				rte_exit(EXIT_FAILURE, "Not enough cores\n");
790af75078fSIntel 		}
791af75078fSIntel 		qconf->rx_queue_list[qconf->n_rx_queue] = portid;
792af75078fSIntel 		qconf->n_rx_queue++;
793af75078fSIntel 
794af75078fSIntel 		/* init port */
795af75078fSIntel 		printf("Initializing port %d on lcore %u... ", portid,
796af75078fSIntel 		       rx_lcore_id);
797af75078fSIntel 		fflush(stdout);
798af75078fSIntel 
799af75078fSIntel 		n_tx_queue = nb_lcores;
800af75078fSIntel 		if (n_tx_queue > MAX_TX_QUEUE_PER_PORT)
801af75078fSIntel 			n_tx_queue = MAX_TX_QUEUE_PER_PORT;
802af75078fSIntel 		ret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue,
803af75078fSIntel 					    &port_conf);
804af75078fSIntel 		if (ret < 0)
805af75078fSIntel 			rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%d\n",
806af75078fSIntel 				  ret, portid);
807af75078fSIntel 
808af75078fSIntel 		rte_eth_macaddr_get(portid, &ports_eth_addr[portid]);
809af75078fSIntel 		print_ethaddr(" Address:", &ports_eth_addr[portid]);
810af75078fSIntel 		printf(", ");
811af75078fSIntel 
812af75078fSIntel 		/* init one RX queue */
813af75078fSIntel 		queueid = 0;
814af75078fSIntel 		printf("rxq=%hu ", queueid);
815af75078fSIntel 		fflush(stdout);
816af75078fSIntel 		ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,
817e60f71ebSIntel 					     rte_eth_dev_socket_id(portid), &rx_conf,
818af75078fSIntel 					     packet_pool);
819af75078fSIntel 		if (ret < 0)
820af75078fSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, port=%d\n",
821af75078fSIntel 				  ret, portid);
822af75078fSIntel 
823af75078fSIntel 		/* init one TX queue per couple (lcore,port) */
824af75078fSIntel 		queueid = 0;
825af75078fSIntel 
826af75078fSIntel 		RTE_LCORE_FOREACH(lcore_id) {
827af75078fSIntel 			if (rte_lcore_is_enabled(lcore_id) == 0)
828af75078fSIntel 				continue;
829af75078fSIntel 			printf("txq=%u,%hu ", lcore_id, queueid);
830af75078fSIntel 			fflush(stdout);
831af75078fSIntel 			ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,
832e60f71ebSIntel 						     rte_lcore_to_socket_id(lcore_id), &tx_conf);
833af75078fSIntel 			if (ret < 0)
834af75078fSIntel 				rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, "
835af75078fSIntel 					  "port=%d\n", ret, portid);
836af75078fSIntel 
837af75078fSIntel 			qconf = &lcore_queue_conf[lcore_id];
838af75078fSIntel 			qconf->tx_queue_id[portid] = queueid;
839af75078fSIntel 			queueid++;
840af75078fSIntel 		}
841af75078fSIntel 
842af75078fSIntel 		/* Start device */
843af75078fSIntel 		ret = rte_eth_dev_start(portid);
844af75078fSIntel 		if (ret < 0)
845af75078fSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%d\n",
846af75078fSIntel 				  ret, portid);
847af75078fSIntel 
848d3641ae8SIntel 		printf("done:\n");
849af75078fSIntel 	}
850af75078fSIntel 
851d3641ae8SIntel 	check_all_ports_link_status(nb_ports, enabled_port_mask);
852af75078fSIntel 
853af75078fSIntel 	/* initialize the multicast hash */
854af75078fSIntel 	int retval = init_mcast_hash();
855af75078fSIntel 	if (retval != 0)
856af75078fSIntel 		rte_exit(EXIT_FAILURE, "Cannot build the multicast hash\n");
857af75078fSIntel 
858af75078fSIntel 	/* launch per-lcore init on every lcore */
859af75078fSIntel 	rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);
860af75078fSIntel 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
861af75078fSIntel 		if (rte_eal_wait_lcore(lcore_id) < 0)
862af75078fSIntel 			return -1;
863af75078fSIntel 	}
864af75078fSIntel 
865af75078fSIntel 	return 0;
866af75078fSIntel }
867