1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4b6df9fc8SIntel * Copyright(c) 2010-2013 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel * 33af75078fSIntel */ 34af75078fSIntel 35af75078fSIntel #include <stdio.h> 36af75078fSIntel #include <stdlib.h> 37af75078fSIntel #include <stdint.h> 38af75078fSIntel #include <inttypes.h> 39af75078fSIntel #include <sys/types.h> 40af75078fSIntel #include <string.h> 41af75078fSIntel #include <sys/queue.h> 42af75078fSIntel #include <stdarg.h> 43af75078fSIntel #include <errno.h> 44af75078fSIntel #include <getopt.h> 45af75078fSIntel 46af75078fSIntel #include <rte_common.h> 47af75078fSIntel #include <rte_byteorder.h> 48af75078fSIntel #include <rte_log.h> 49af75078fSIntel #include <rte_tailq.h> 50af75078fSIntel #include <rte_memory.h> 51af75078fSIntel #include <rte_memcpy.h> 52af75078fSIntel #include <rte_memzone.h> 53af75078fSIntel #include <rte_eal.h> 54af75078fSIntel #include <rte_per_lcore.h> 55af75078fSIntel #include <rte_launch.h> 56af75078fSIntel #include <rte_atomic.h> 57af75078fSIntel #include <rte_cycles.h> 58af75078fSIntel #include <rte_prefetch.h> 59af75078fSIntel #include <rte_lcore.h> 60af75078fSIntel #include <rte_per_lcore.h> 61af75078fSIntel #include <rte_branch_prediction.h> 62af75078fSIntel #include <rte_interrupts.h> 63af75078fSIntel #include <rte_pci.h> 64af75078fSIntel #include <rte_random.h> 65af75078fSIntel #include <rte_debug.h> 66af75078fSIntel #include <rte_ether.h> 67af75078fSIntel #include <rte_ethdev.h> 68af75078fSIntel #include <rte_ring.h> 69af75078fSIntel #include <rte_mempool.h> 70af75078fSIntel #include <rte_mbuf.h> 71af75078fSIntel #include <rte_malloc.h> 72af75078fSIntel #include <rte_fbk_hash.h> 73af75078fSIntel #include <rte_ip.h> 74af75078fSIntel 75af75078fSIntel #include "main.h" 76af75078fSIntel 77af75078fSIntel #define RTE_LOGTYPE_IPv4_MULTICAST RTE_LOGTYPE_USER1 78af75078fSIntel 79af75078fSIntel #define MAX_PORTS 16 80af75078fSIntel 81af75078fSIntel #define MCAST_CLONE_PORTS 2 82af75078fSIntel #define MCAST_CLONE_SEGS 2 83af75078fSIntel 84af75078fSIntel #define PKT_MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM) 85af75078fSIntel #define NB_PKT_MBUF 8192 86af75078fSIntel 87af75078fSIntel #define HDR_MBUF_SIZE (sizeof(struct rte_mbuf) + 2 * RTE_PKTMBUF_HEADROOM) 88af75078fSIntel #define NB_HDR_MBUF (NB_PKT_MBUF * MAX_PORTS) 89af75078fSIntel 90af75078fSIntel #define CLONE_MBUF_SIZE (sizeof(struct rte_mbuf)) 91af75078fSIntel #define NB_CLONE_MBUF (NB_PKT_MBUF * MCAST_CLONE_PORTS * MCAST_CLONE_SEGS * 2) 92af75078fSIntel 93af75078fSIntel /* allow max jumbo frame 9.5 KB */ 94af75078fSIntel #define JUMBO_FRAME_MAX_SIZE 0x2600 95af75078fSIntel 96af75078fSIntel /* 97af75078fSIntel * RX and TX Prefetch, Host, and Write-back threshold values should be 98af75078fSIntel * carefully set for optimal performance. Consult the network 99af75078fSIntel * controller's datasheet and supporting DPDK documentation for guidance 100af75078fSIntel * on how these parameters should be set. 101af75078fSIntel */ 102af75078fSIntel #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */ 103af75078fSIntel #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */ 104af75078fSIntel #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */ 105af75078fSIntel 106af75078fSIntel /* 107af75078fSIntel * These default values are optimized for use with the Intel(R) 82599 10 GbE 108af75078fSIntel * Controller and the DPDK ixgbe PMD. Consider using other values for other 109af75078fSIntel * network controllers and/or network drivers. 110af75078fSIntel */ 111af75078fSIntel #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */ 112af75078fSIntel #define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */ 113af75078fSIntel #define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */ 114af75078fSIntel 115af75078fSIntel #define MAX_PKT_BURST 32 116*5c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */ 117af75078fSIntel 118af75078fSIntel /* Configure how many packets ahead to prefetch, when reading packets */ 119af75078fSIntel #define PREFETCH_OFFSET 3 120af75078fSIntel 121af75078fSIntel /* 122af75078fSIntel * Construct Ethernet multicast address from IPv4 multicast address. 123af75078fSIntel * Citing RFC 1112, section 6.4: 124af75078fSIntel * "An IP host group address is mapped to an Ethernet multicast address 125af75078fSIntel * by placing the low-order 23-bits of the IP address into the low-order 126af75078fSIntel * 23 bits of the Ethernet multicast address 01-00-5E-00-00-00 (hex)." 127af75078fSIntel */ 128af75078fSIntel #define ETHER_ADDR_FOR_IPV4_MCAST(x) \ 129af75078fSIntel (rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16) 130af75078fSIntel 131af75078fSIntel /* 132af75078fSIntel * Configurable number of RX/TX ring descriptors 133af75078fSIntel */ 134af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128 135af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512 136af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; 137af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; 138af75078fSIntel 139af75078fSIntel /* ethernet addresses of ports */ 140af75078fSIntel static struct ether_addr ports_eth_addr[MAX_PORTS]; 141af75078fSIntel 142af75078fSIntel /* mask of enabled ports */ 143af75078fSIntel static uint32_t enabled_port_mask = 0; 144af75078fSIntel 145af75078fSIntel static uint8_t nb_ports = 0; 146af75078fSIntel 147af75078fSIntel static int rx_queue_per_lcore = 1; 148af75078fSIntel 149af75078fSIntel struct mbuf_table { 150af75078fSIntel uint16_t len; 151af75078fSIntel struct rte_mbuf *m_table[MAX_PKT_BURST]; 152af75078fSIntel }; 153af75078fSIntel 154af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16 155af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16 156af75078fSIntel struct lcore_queue_conf { 157af75078fSIntel uint64_t tx_tsc; 158af75078fSIntel uint16_t n_rx_queue; 159af75078fSIntel uint8_t rx_queue_list[MAX_RX_QUEUE_PER_LCORE]; 160af75078fSIntel uint16_t tx_queue_id[MAX_PORTS]; 161af75078fSIntel struct mbuf_table tx_mbufs[MAX_PORTS]; 162af75078fSIntel } __rte_cache_aligned; 163af75078fSIntel static struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE]; 164af75078fSIntel 165af75078fSIntel static const struct rte_eth_conf port_conf = { 166af75078fSIntel .rxmode = { 167af75078fSIntel .max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE, 168af75078fSIntel .split_hdr_size = 0, 169af75078fSIntel .header_split = 0, /**< Header Split disabled */ 170af75078fSIntel .hw_ip_checksum = 0, /**< IP checksum offload disabled */ 171af75078fSIntel .hw_vlan_filter = 0, /**< VLAN filtering disabled */ 172af75078fSIntel .jumbo_frame = 1, /**< Jumbo Frame Support enabled */ 173af75078fSIntel .hw_strip_crc = 0, /**< CRC stripped by hardware */ 174af75078fSIntel }, 175af75078fSIntel .txmode = { 17632e7aa0bSIntel .mq_mode = ETH_MQ_TX_NONE, 177af75078fSIntel }, 178af75078fSIntel }; 179af75078fSIntel 180af75078fSIntel static const struct rte_eth_rxconf rx_conf = { 181af75078fSIntel .rx_thresh = { 182af75078fSIntel .pthresh = RX_PTHRESH, 183af75078fSIntel .hthresh = RX_HTHRESH, 184af75078fSIntel .wthresh = RX_WTHRESH, 185af75078fSIntel }, 186af75078fSIntel }; 187af75078fSIntel 188af75078fSIntel static const struct rte_eth_txconf tx_conf = { 189af75078fSIntel .tx_thresh = { 190af75078fSIntel .pthresh = TX_PTHRESH, 191af75078fSIntel .hthresh = TX_HTHRESH, 192af75078fSIntel .wthresh = TX_WTHRESH, 193af75078fSIntel }, 194af75078fSIntel .tx_free_thresh = 0, /* Use PMD default values */ 195af75078fSIntel .tx_rs_thresh = 0, /* Use PMD default values */ 196af75078fSIntel }; 197af75078fSIntel 198af75078fSIntel static struct rte_mempool *packet_pool, *header_pool, *clone_pool; 199af75078fSIntel 200af75078fSIntel 201af75078fSIntel /* Multicast */ 202af75078fSIntel static struct rte_fbk_hash_params mcast_hash_params = { 203af75078fSIntel .name = "MCAST_HASH", 204af75078fSIntel .entries = 1024, 205af75078fSIntel .entries_per_bucket = 4, 206e60f71ebSIntel .socket_id = 0, 207af75078fSIntel .hash_func = NULL, 208af75078fSIntel .init_val = 0, 209af75078fSIntel }; 210af75078fSIntel 211af75078fSIntel struct rte_fbk_hash_table *mcast_hash = NULL; 212af75078fSIntel 213af75078fSIntel struct mcast_group_params { 214af75078fSIntel uint32_t ip; 215af75078fSIntel uint16_t port_mask; 216af75078fSIntel }; 217af75078fSIntel 218af75078fSIntel static struct mcast_group_params mcast_group_table[] = { 219af75078fSIntel {IPv4(224,0,0,101), 0x1}, 220af75078fSIntel {IPv4(224,0,0,102), 0x2}, 221af75078fSIntel {IPv4(224,0,0,103), 0x3}, 222af75078fSIntel {IPv4(224,0,0,104), 0x4}, 223af75078fSIntel {IPv4(224,0,0,105), 0x5}, 224af75078fSIntel {IPv4(224,0,0,106), 0x6}, 225af75078fSIntel {IPv4(224,0,0,107), 0x7}, 226af75078fSIntel {IPv4(224,0,0,108), 0x8}, 227af75078fSIntel {IPv4(224,0,0,109), 0x9}, 228af75078fSIntel {IPv4(224,0,0,110), 0xA}, 229af75078fSIntel {IPv4(224,0,0,111), 0xB}, 230af75078fSIntel {IPv4(224,0,0,112), 0xC}, 231af75078fSIntel {IPv4(224,0,0,113), 0xD}, 232af75078fSIntel {IPv4(224,0,0,114), 0xE}, 233af75078fSIntel {IPv4(224,0,0,115), 0xF}, 234af75078fSIntel }; 235af75078fSIntel 236af75078fSIntel #define N_MCAST_GROUPS \ 237af75078fSIntel (sizeof (mcast_group_table) / sizeof (mcast_group_table[0])) 238af75078fSIntel 239af75078fSIntel 240af75078fSIntel /* Send burst of packets on an output interface */ 241af75078fSIntel static void 242af75078fSIntel send_burst(struct lcore_queue_conf *qconf, uint8_t port) 243af75078fSIntel { 244af75078fSIntel struct rte_mbuf **m_table; 245af75078fSIntel uint16_t n, queueid; 246af75078fSIntel int ret; 247af75078fSIntel 248af75078fSIntel queueid = qconf->tx_queue_id[port]; 249af75078fSIntel m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table; 250af75078fSIntel n = qconf->tx_mbufs[port].len; 251af75078fSIntel 252af75078fSIntel ret = rte_eth_tx_burst(port, queueid, m_table, n); 253af75078fSIntel while (unlikely (ret < n)) { 254af75078fSIntel rte_pktmbuf_free(m_table[ret]); 255af75078fSIntel ret++; 256af75078fSIntel } 257af75078fSIntel 258af75078fSIntel qconf->tx_mbufs[port].len = 0; 259af75078fSIntel } 260af75078fSIntel 261af75078fSIntel /* Get number of bits set. */ 262af75078fSIntel static inline uint32_t 263af75078fSIntel bitcnt(uint32_t v) 264af75078fSIntel { 265af75078fSIntel uint32_t n; 266af75078fSIntel 267af75078fSIntel for (n = 0; v != 0; v &= v - 1, n++) 268af75078fSIntel ; 269af75078fSIntel 270af75078fSIntel return (n); 271af75078fSIntel } 272af75078fSIntel 273af75078fSIntel /** 274af75078fSIntel * Create the output multicast packet based on the given input packet. 275af75078fSIntel * There are two approaches for creating outgoing packet, though both 276af75078fSIntel * are based on data zero-copy idea, they differ in few details: 277af75078fSIntel * First one creates a clone of the input packet, e.g - walk though all 278af75078fSIntel * segments of the input packet, and for each of them create a new packet 279af75078fSIntel * mbuf and attach that new mbuf to the segment (refer to rte_pktmbuf_clone() 280af75078fSIntel * for more details). Then new mbuf is allocated for the packet header 281af75078fSIntel * and is prepended to the 'clone' mbuf. 282af75078fSIntel * Second approach doesn't make a clone, it just increment refcnt for all 283af75078fSIntel * input packet segments. Then it allocates new mbuf for the packet header 284af75078fSIntel * and prepends it to the input packet. 285af75078fSIntel * Basically first approach reuses only input packet's data, but creates 286af75078fSIntel * it's own copy of packet's metadata. Second approach reuses both input's 287af75078fSIntel * packet data and metadata. 288af75078fSIntel * The advantage of first approach - is that each outgoing packet has it's 289af75078fSIntel * own copy of metadata, so we can safely modify data pointer of the 290af75078fSIntel * input packet. That allows us to skip creation if the output packet for 291af75078fSIntel * the last destination port, but instead modify input packet's header inplace, 292af75078fSIntel * e.g: for N destination ports we need to invoke mcast_out_pkt (N-1) times. 293af75078fSIntel * The advantage of second approach - less work for each outgoing packet, 294af75078fSIntel * e.g: we skip "clone" operation completely. Though it comes with a price - 295af75078fSIntel * input packet's metadata has to be intact. So for N destination ports we 296af75078fSIntel * need to invoke mcast_out_pkt N times. 297af75078fSIntel * So for small number of outgoing ports (and segments in the input packet) 298af75078fSIntel * first approach will be faster. 299af75078fSIntel * As number of outgoing ports (and/or input segments) will grow, 300af75078fSIntel * second way will become more preferable. 301af75078fSIntel * 302af75078fSIntel * @param pkt 303af75078fSIntel * Input packet mbuf. 304af75078fSIntel * @param use_clone 305af75078fSIntel * Control which of the two approaches described above should be used: 306af75078fSIntel * - 0 - use second approach: 307af75078fSIntel * Don't "clone" input packet. 308af75078fSIntel * Prepend new header directly to the input packet 309af75078fSIntel * - 1 - use first approach: 310af75078fSIntel * Make a "clone" of input packet first. 311af75078fSIntel * Prepend new header to the clone of the input packet 312af75078fSIntel * @return 313af75078fSIntel * - The pointer to the new outgoing packet. 314af75078fSIntel * - NULL if operation failed. 315af75078fSIntel */ 316af75078fSIntel static inline struct rte_mbuf * 317af75078fSIntel mcast_out_pkt(struct rte_mbuf *pkt, int use_clone) 318af75078fSIntel { 319af75078fSIntel struct rte_mbuf *hdr; 320af75078fSIntel 321af75078fSIntel /* Create new mbuf for the header. */ 322af75078fSIntel if (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL)) 323af75078fSIntel return (NULL); 324af75078fSIntel 325af75078fSIntel /* If requested, then make a new clone packet. */ 326af75078fSIntel if (use_clone != 0 && 327af75078fSIntel unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) { 328af75078fSIntel rte_pktmbuf_free(hdr); 329af75078fSIntel return (NULL); 330af75078fSIntel } 331af75078fSIntel 332af75078fSIntel /* prepend new header */ 333af75078fSIntel hdr->pkt.next = pkt; 334af75078fSIntel 335af75078fSIntel 336af75078fSIntel /* update header's fields */ 337af75078fSIntel hdr->pkt.pkt_len = (uint16_t)(hdr->pkt.data_len + pkt->pkt.pkt_len); 338af75078fSIntel hdr->pkt.nb_segs = (uint8_t)(pkt->pkt.nb_segs + 1); 339af75078fSIntel 340af75078fSIntel /* copy metadata from source packet*/ 341af75078fSIntel hdr->pkt.in_port = pkt->pkt.in_port; 34242d71416SIntel hdr->pkt.vlan_macip = pkt->pkt.vlan_macip; 343af75078fSIntel hdr->pkt.hash = pkt->pkt.hash; 344af75078fSIntel 345af75078fSIntel hdr->ol_flags = pkt->ol_flags; 346af75078fSIntel 347af75078fSIntel __rte_mbuf_sanity_check(hdr, RTE_MBUF_PKT, 1); 348af75078fSIntel return (hdr); 349af75078fSIntel } 350af75078fSIntel 351af75078fSIntel /* 352af75078fSIntel * Write new Ethernet header to the outgoing packet, 353af75078fSIntel * and put it into the outgoing queue for the given port. 354af75078fSIntel */ 355af75078fSIntel static inline void 356af75078fSIntel mcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr, 357af75078fSIntel struct lcore_queue_conf *qconf, uint8_t port) 358af75078fSIntel { 359af75078fSIntel struct ether_hdr *ethdr; 360af75078fSIntel uint16_t len; 361af75078fSIntel 362af75078fSIntel /* Construct Ethernet header. */ 363af75078fSIntel ethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(*ethdr)); 364af75078fSIntel RTE_MBUF_ASSERT(ethdr != NULL); 365af75078fSIntel 366af75078fSIntel ether_addr_copy(dest_addr, ðdr->d_addr); 367af75078fSIntel ether_addr_copy(&ports_eth_addr[port], ðdr->s_addr); 368af75078fSIntel ethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4); 369af75078fSIntel 370af75078fSIntel /* Put new packet into the output queue */ 371af75078fSIntel len = qconf->tx_mbufs[port].len; 372af75078fSIntel qconf->tx_mbufs[port].m_table[len] = pkt; 373af75078fSIntel qconf->tx_mbufs[port].len = ++len; 374af75078fSIntel 375af75078fSIntel /* Transmit packets */ 376af75078fSIntel if (unlikely(MAX_PKT_BURST == len)) 377af75078fSIntel send_burst(qconf, port); 378af75078fSIntel } 379af75078fSIntel 380af75078fSIntel /* Multicast forward of the input packet */ 381af75078fSIntel static inline void 382af75078fSIntel mcast_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf) 383af75078fSIntel { 384af75078fSIntel struct rte_mbuf *mc; 385af75078fSIntel struct ipv4_hdr *iphdr; 386af75078fSIntel uint32_t dest_addr, port_mask, port_num, use_clone; 387af75078fSIntel int32_t hash; 388af75078fSIntel uint8_t port; 389af75078fSIntel union { 390af75078fSIntel uint64_t as_int; 391af75078fSIntel struct ether_addr as_addr; 392af75078fSIntel } dst_eth_addr; 393af75078fSIntel 394af75078fSIntel /* Remove the Ethernet header from the input packet */ 395af75078fSIntel iphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr)); 396af75078fSIntel RTE_MBUF_ASSERT(iphdr != NULL); 397af75078fSIntel 398af75078fSIntel dest_addr = rte_be_to_cpu_32(iphdr->dst_addr); 399af75078fSIntel 400af75078fSIntel /* 401af75078fSIntel * Check that it is a valid multicast address and 402af75078fSIntel * we have some active ports assigned to it. 403af75078fSIntel */ 404af75078fSIntel if(!IS_IPV4_MCAST(dest_addr) || 405af75078fSIntel (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 || 406af75078fSIntel (port_mask = hash & enabled_port_mask) == 0) { 407af75078fSIntel rte_pktmbuf_free(m); 408af75078fSIntel return; 409af75078fSIntel } 410af75078fSIntel 411af75078fSIntel /* Calculate number of destination ports. */ 412af75078fSIntel port_num = bitcnt(port_mask); 413af75078fSIntel 414af75078fSIntel /* Should we use rte_pktmbuf_clone() or not. */ 415af75078fSIntel use_clone = (port_num <= MCAST_CLONE_PORTS && 416af75078fSIntel m->pkt.nb_segs <= MCAST_CLONE_SEGS); 417af75078fSIntel 418af75078fSIntel /* Mark all packet's segments as referenced port_num times */ 419af75078fSIntel if (use_clone == 0) 420af75078fSIntel rte_pktmbuf_refcnt_update(m, (uint16_t)port_num); 421af75078fSIntel 422af75078fSIntel /* construct destination ethernet address */ 423af75078fSIntel dst_eth_addr.as_int = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr); 424af75078fSIntel 425af75078fSIntel for (port = 0; use_clone != port_mask; port_mask >>= 1, port++) { 426af75078fSIntel 427af75078fSIntel /* Prepare output packet and send it out. */ 428af75078fSIntel if ((port_mask & 1) != 0) { 429af75078fSIntel if (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL)) 430af75078fSIntel mcast_send_pkt(mc, &dst_eth_addr.as_addr, 431af75078fSIntel qconf, port); 432af75078fSIntel else if (use_clone == 0) 433af75078fSIntel rte_pktmbuf_free(m); 434af75078fSIntel } 435af75078fSIntel } 436af75078fSIntel 437af75078fSIntel /* 438af75078fSIntel * If we making clone packets, then, for the last destination port, 439af75078fSIntel * we can overwrite input packet's metadata. 440af75078fSIntel */ 441af75078fSIntel if (use_clone != 0) 442af75078fSIntel mcast_send_pkt(m, &dst_eth_addr.as_addr, qconf, port); 443af75078fSIntel else 444af75078fSIntel rte_pktmbuf_free(m); 445af75078fSIntel } 446af75078fSIntel 447af75078fSIntel /* Send burst of outgoing packet, if timeout expires. */ 448af75078fSIntel static inline void 449af75078fSIntel send_timeout_burst(struct lcore_queue_conf *qconf) 450af75078fSIntel { 451af75078fSIntel uint64_t cur_tsc; 452af75078fSIntel uint8_t portid; 453*5c95261dSIntel const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US; 454af75078fSIntel 455af75078fSIntel cur_tsc = rte_rdtsc(); 456*5c95261dSIntel if (likely (cur_tsc < qconf->tx_tsc + drain_tsc)) 457af75078fSIntel return; 458af75078fSIntel 459af75078fSIntel for (portid = 0; portid < MAX_PORTS; portid++) { 460af75078fSIntel if (qconf->tx_mbufs[portid].len != 0) 461af75078fSIntel send_burst(qconf, portid); 462af75078fSIntel } 463af75078fSIntel qconf->tx_tsc = cur_tsc; 464af75078fSIntel } 465af75078fSIntel 466af75078fSIntel /* main processing loop */ 467af75078fSIntel static __attribute__((noreturn)) int 468af75078fSIntel main_loop(__rte_unused void *dummy) 469af75078fSIntel { 470af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 4716441b9f6SIntel unsigned lcore_id; 472af75078fSIntel int i, j, nb_rx; 473af75078fSIntel uint8_t portid; 474af75078fSIntel struct lcore_queue_conf *qconf; 475af75078fSIntel 476af75078fSIntel lcore_id = rte_lcore_id(); 477af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 478af75078fSIntel 479af75078fSIntel 480af75078fSIntel if (qconf->n_rx_queue == 0) { 481af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, "lcore %u has nothing to do\n", 482af75078fSIntel lcore_id); 483af75078fSIntel while(1); 484af75078fSIntel } 485af75078fSIntel 486af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, "entering main loop on lcore %u\n", 487af75078fSIntel lcore_id); 488af75078fSIntel 489af75078fSIntel for (i = 0; i < qconf->n_rx_queue; i++) { 490af75078fSIntel 491af75078fSIntel portid = qconf->rx_queue_list[i]; 492af75078fSIntel RTE_LOG(INFO, IPv4_MULTICAST, " -- lcoreid=%u portid=%d\n", 493af75078fSIntel lcore_id, (int) portid); 494af75078fSIntel } 495af75078fSIntel 496af75078fSIntel while (1) { 497af75078fSIntel 498af75078fSIntel /* 499af75078fSIntel * Read packet from RX queues 500af75078fSIntel */ 501af75078fSIntel for (i = 0; i < qconf->n_rx_queue; i++) { 502af75078fSIntel 503af75078fSIntel portid = qconf->rx_queue_list[i]; 504af75078fSIntel nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst, 505af75078fSIntel MAX_PKT_BURST); 506af75078fSIntel 507af75078fSIntel /* Prefetch first packets */ 508af75078fSIntel for (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) { 509af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod( 510af75078fSIntel pkts_burst[j], void *)); 511af75078fSIntel } 512af75078fSIntel 513af75078fSIntel /* Prefetch and forward already prefetched packets */ 514af75078fSIntel for (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) { 515af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod(pkts_burst[ 516af75078fSIntel j + PREFETCH_OFFSET], void *)); 517af75078fSIntel mcast_forward(pkts_burst[j], qconf); 518af75078fSIntel } 519af75078fSIntel 520af75078fSIntel /* Forward remaining prefetched packets */ 521af75078fSIntel for (; j < nb_rx; j++) { 522af75078fSIntel mcast_forward(pkts_burst[j], qconf); 523af75078fSIntel } 524af75078fSIntel } 525af75078fSIntel 526af75078fSIntel /* Send out packets from TX queues */ 527af75078fSIntel send_timeout_burst(qconf); 528af75078fSIntel } 529af75078fSIntel } 530af75078fSIntel 531af75078fSIntel /* display usage */ 532af75078fSIntel static void 533af75078fSIntel print_usage(const char *prgname) 534af75078fSIntel { 535af75078fSIntel printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n" 536af75078fSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n" 537af75078fSIntel " -q NQ: number of queue (=ports) per lcore (default is 1)\n", 538af75078fSIntel prgname); 539af75078fSIntel } 540af75078fSIntel 541af75078fSIntel static uint32_t 542af75078fSIntel parse_portmask(const char *portmask) 543af75078fSIntel { 544af75078fSIntel char *end = NULL; 545af75078fSIntel unsigned long pm; 546af75078fSIntel 547af75078fSIntel /* parse hexadecimal string */ 548af75078fSIntel pm = strtoul(portmask, &end, 16); 549af75078fSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0')) 550af75078fSIntel return 0; 551af75078fSIntel 552af75078fSIntel return ((uint32_t)pm); 553af75078fSIntel } 554af75078fSIntel 555af75078fSIntel static int 556af75078fSIntel parse_nqueue(const char *q_arg) 557af75078fSIntel { 558af75078fSIntel char *end = NULL; 559af75078fSIntel unsigned long n; 560af75078fSIntel 561af75078fSIntel /* parse numerical string */ 562af75078fSIntel errno = 0; 563af75078fSIntel n = strtoul(q_arg, &end, 0); 564af75078fSIntel if (errno != 0 || end == NULL || *end != '\0' || 565af75078fSIntel n == 0 || n >= MAX_RX_QUEUE_PER_LCORE) 566af75078fSIntel return (-1); 567af75078fSIntel 568af75078fSIntel return (n); 569af75078fSIntel } 570af75078fSIntel 571af75078fSIntel /* Parse the argument given in the command line of the application */ 572af75078fSIntel static int 573af75078fSIntel parse_args(int argc, char **argv) 574af75078fSIntel { 575af75078fSIntel int opt, ret; 576af75078fSIntel char **argvopt; 577af75078fSIntel int option_index; 578af75078fSIntel char *prgname = argv[0]; 579af75078fSIntel static struct option lgopts[] = { 580af75078fSIntel {NULL, 0, 0, 0} 581af75078fSIntel }; 582af75078fSIntel 583af75078fSIntel argvopt = argv; 584af75078fSIntel 585af75078fSIntel while ((opt = getopt_long(argc, argvopt, "p:q:", 586af75078fSIntel lgopts, &option_index)) != EOF) { 587af75078fSIntel 588af75078fSIntel switch (opt) { 589af75078fSIntel /* portmask */ 590af75078fSIntel case 'p': 591af75078fSIntel enabled_port_mask = parse_portmask(optarg); 592af75078fSIntel if (enabled_port_mask == 0) { 593af75078fSIntel printf("invalid portmask\n"); 594af75078fSIntel print_usage(prgname); 595af75078fSIntel return -1; 596af75078fSIntel } 597af75078fSIntel break; 598af75078fSIntel 599af75078fSIntel /* nqueue */ 600af75078fSIntel case 'q': 601af75078fSIntel rx_queue_per_lcore = parse_nqueue(optarg); 602af75078fSIntel if (rx_queue_per_lcore < 0) { 603af75078fSIntel printf("invalid queue number\n"); 604af75078fSIntel print_usage(prgname); 605af75078fSIntel return -1; 606af75078fSIntel } 607af75078fSIntel break; 608af75078fSIntel 609af75078fSIntel default: 610af75078fSIntel print_usage(prgname); 611af75078fSIntel return -1; 612af75078fSIntel } 613af75078fSIntel } 614af75078fSIntel 615af75078fSIntel if (optind >= 0) 616af75078fSIntel argv[optind-1] = prgname; 617af75078fSIntel 618af75078fSIntel ret = optind-1; 619af75078fSIntel optind = 0; /* reset getopt lib */ 620af75078fSIntel return ret; 621af75078fSIntel } 622af75078fSIntel 623af75078fSIntel static void 624af75078fSIntel print_ethaddr(const char *name, struct ether_addr *eth_addr) 625af75078fSIntel { 626af75078fSIntel printf("%s%02X:%02X:%02X:%02X:%02X:%02X", name, 627af75078fSIntel eth_addr->addr_bytes[0], 628af75078fSIntel eth_addr->addr_bytes[1], 629af75078fSIntel eth_addr->addr_bytes[2], 630af75078fSIntel eth_addr->addr_bytes[3], 631af75078fSIntel eth_addr->addr_bytes[4], 632af75078fSIntel eth_addr->addr_bytes[5]); 633af75078fSIntel } 634af75078fSIntel 635af75078fSIntel static int 636af75078fSIntel init_mcast_hash(void) 637af75078fSIntel { 638af75078fSIntel uint32_t i; 639af75078fSIntel 640e60f71ebSIntel mcast_hash_params.socket_id = rte_socket_id(); 641af75078fSIntel mcast_hash = rte_fbk_hash_create(&mcast_hash_params); 642af75078fSIntel if (mcast_hash == NULL){ 643af75078fSIntel return -1; 644af75078fSIntel } 645af75078fSIntel 646af75078fSIntel for (i = 0; i < N_MCAST_GROUPS; i ++){ 647af75078fSIntel if (rte_fbk_hash_add_key(mcast_hash, 648af75078fSIntel mcast_group_table[i].ip, 649af75078fSIntel mcast_group_table[i].port_mask) < 0) { 650af75078fSIntel return -1; 651af75078fSIntel } 652af75078fSIntel } 653af75078fSIntel 654af75078fSIntel return 0; 655af75078fSIntel } 656af75078fSIntel 657d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 658d3641ae8SIntel static void 659d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask) 660d3641ae8SIntel { 661d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */ 662d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 663d3641ae8SIntel uint8_t portid, count, all_ports_up, print_flag = 0; 664d3641ae8SIntel struct rte_eth_link link; 665d3641ae8SIntel 666d3641ae8SIntel printf("\nChecking link status"); 667d3641ae8SIntel fflush(stdout); 668d3641ae8SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 669d3641ae8SIntel all_ports_up = 1; 670d3641ae8SIntel for (portid = 0; portid < port_num; portid++) { 671d3641ae8SIntel if ((port_mask & (1 << portid)) == 0) 672d3641ae8SIntel continue; 673d3641ae8SIntel memset(&link, 0, sizeof(link)); 674d3641ae8SIntel rte_eth_link_get_nowait(portid, &link); 675d3641ae8SIntel /* print link status if flag set */ 676d3641ae8SIntel if (print_flag == 1) { 677d3641ae8SIntel if (link.link_status) 678d3641ae8SIntel printf("Port %d Link Up - speed %u " 679d3641ae8SIntel "Mbps - %s\n", (uint8_t)portid, 680d3641ae8SIntel (unsigned)link.link_speed, 681d3641ae8SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 682d3641ae8SIntel ("full-duplex") : ("half-duplex\n")); 683d3641ae8SIntel else 684d3641ae8SIntel printf("Port %d Link Down\n", 685d3641ae8SIntel (uint8_t)portid); 686d3641ae8SIntel continue; 687d3641ae8SIntel } 688d3641ae8SIntel /* clear all_ports_up flag if any link down */ 689d3641ae8SIntel if (link.link_status == 0) { 690d3641ae8SIntel all_ports_up = 0; 691d3641ae8SIntel break; 692d3641ae8SIntel } 693d3641ae8SIntel } 694d3641ae8SIntel /* after finally printing all link status, get out */ 695d3641ae8SIntel if (print_flag == 1) 696d3641ae8SIntel break; 697d3641ae8SIntel 698d3641ae8SIntel if (all_ports_up == 0) { 699d3641ae8SIntel printf("."); 700d3641ae8SIntel fflush(stdout); 701d3641ae8SIntel rte_delay_ms(CHECK_INTERVAL); 702d3641ae8SIntel } 703d3641ae8SIntel 704d3641ae8SIntel /* set the print_flag if all ports up or timeout */ 705d3641ae8SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 706d3641ae8SIntel print_flag = 1; 707d3641ae8SIntel printf("done\n"); 708d3641ae8SIntel } 709d3641ae8SIntel } 710d3641ae8SIntel } 711d3641ae8SIntel 712af75078fSIntel int 713af75078fSIntel MAIN(int argc, char **argv) 714af75078fSIntel { 715af75078fSIntel struct lcore_queue_conf *qconf; 716af75078fSIntel int ret; 717af75078fSIntel uint16_t queueid; 718af75078fSIntel unsigned lcore_id = 0, rx_lcore_id = 0;; 719af75078fSIntel uint32_t n_tx_queue, nb_lcores; 720af75078fSIntel uint8_t portid; 721af75078fSIntel 722af75078fSIntel /* init EAL */ 723af75078fSIntel ret = rte_eal_init(argc, argv); 724af75078fSIntel if (ret < 0) 725af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid EAL parameters\n"); 726af75078fSIntel argc -= ret; 727af75078fSIntel argv += ret; 728af75078fSIntel 729af75078fSIntel /* parse application arguments (after the EAL ones) */ 730af75078fSIntel ret = parse_args(argc, argv); 731af75078fSIntel if (ret < 0) 732af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid IPV4_MULTICAST parameters\n"); 733af75078fSIntel 734af75078fSIntel /* create the mbuf pools */ 735af75078fSIntel packet_pool = rte_mempool_create("packet_pool", NB_PKT_MBUF, 736af75078fSIntel PKT_MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private), 737af75078fSIntel rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL, 738e60f71ebSIntel rte_socket_id(), 0); 739af75078fSIntel 740af75078fSIntel if (packet_pool == NULL) 741af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init packet mbuf pool\n"); 742af75078fSIntel 743af75078fSIntel header_pool = rte_mempool_create("header_pool", NB_HDR_MBUF, 744af75078fSIntel HDR_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, 745e60f71ebSIntel rte_socket_id(), 0); 746af75078fSIntel 747af75078fSIntel if (header_pool == NULL) 748af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init header mbuf pool\n"); 749af75078fSIntel 750af75078fSIntel clone_pool = rte_mempool_create("clone_pool", NB_CLONE_MBUF, 751af75078fSIntel CLONE_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, 752e60f71ebSIntel rte_socket_id(), 0); 753af75078fSIntel 754af75078fSIntel if (clone_pool == NULL) 755af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot init clone mbuf pool\n"); 756af75078fSIntel 757af75078fSIntel /* init driver */ 75869d22b8eSIntel if (rte_pmd_init_all() < 0) 75969d22b8eSIntel rte_exit(EXIT_FAILURE, "Cannot init pmd\n"); 760af75078fSIntel 761af75078fSIntel if (rte_eal_pci_probe() < 0) 762af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot probe PCI\n"); 763af75078fSIntel 764af75078fSIntel nb_ports = rte_eth_dev_count(); 765af75078fSIntel if (nb_ports == 0) 766af75078fSIntel rte_exit(EXIT_FAILURE, "No physical ports!\n"); 767af75078fSIntel if (nb_ports > MAX_PORTS) 768af75078fSIntel nb_ports = MAX_PORTS; 769af75078fSIntel 770af75078fSIntel nb_lcores = rte_lcore_count(); 771af75078fSIntel 772af75078fSIntel /* initialize all ports */ 773af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 774af75078fSIntel /* skip ports that are not enabled */ 775af75078fSIntel if ((enabled_port_mask & (1 << portid)) == 0) { 776af75078fSIntel printf("Skipping disabled port %d\n", portid); 777af75078fSIntel continue; 778af75078fSIntel } 779af75078fSIntel 780af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 781af75078fSIntel 782af75078fSIntel /* get the lcore_id for this port */ 783af75078fSIntel while (rte_lcore_is_enabled(rx_lcore_id) == 0 || 784af75078fSIntel qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) { 785af75078fSIntel 786af75078fSIntel rx_lcore_id ++; 787af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 788af75078fSIntel 789af75078fSIntel if (rx_lcore_id >= RTE_MAX_LCORE) 790af75078fSIntel rte_exit(EXIT_FAILURE, "Not enough cores\n"); 791af75078fSIntel } 792af75078fSIntel qconf->rx_queue_list[qconf->n_rx_queue] = portid; 793af75078fSIntel qconf->n_rx_queue++; 794af75078fSIntel 795af75078fSIntel /* init port */ 796af75078fSIntel printf("Initializing port %d on lcore %u... ", portid, 797af75078fSIntel rx_lcore_id); 798af75078fSIntel fflush(stdout); 799af75078fSIntel 800af75078fSIntel n_tx_queue = nb_lcores; 801af75078fSIntel if (n_tx_queue > MAX_TX_QUEUE_PER_PORT) 802af75078fSIntel n_tx_queue = MAX_TX_QUEUE_PER_PORT; 803af75078fSIntel ret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue, 804af75078fSIntel &port_conf); 805af75078fSIntel if (ret < 0) 806af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%d\n", 807af75078fSIntel ret, portid); 808af75078fSIntel 809af75078fSIntel rte_eth_macaddr_get(portid, &ports_eth_addr[portid]); 810af75078fSIntel print_ethaddr(" Address:", &ports_eth_addr[portid]); 811af75078fSIntel printf(", "); 812af75078fSIntel 813af75078fSIntel /* init one RX queue */ 814af75078fSIntel queueid = 0; 815af75078fSIntel printf("rxq=%hu ", queueid); 816af75078fSIntel fflush(stdout); 817af75078fSIntel ret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd, 818e60f71ebSIntel rte_eth_dev_socket_id(portid), &rx_conf, 819af75078fSIntel packet_pool); 820af75078fSIntel if (ret < 0) 821af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, port=%d\n", 822af75078fSIntel ret, portid); 823af75078fSIntel 824af75078fSIntel /* init one TX queue per couple (lcore,port) */ 825af75078fSIntel queueid = 0; 826af75078fSIntel 827af75078fSIntel RTE_LCORE_FOREACH(lcore_id) { 828af75078fSIntel if (rte_lcore_is_enabled(lcore_id) == 0) 829af75078fSIntel continue; 830af75078fSIntel printf("txq=%u,%hu ", lcore_id, queueid); 831af75078fSIntel fflush(stdout); 832af75078fSIntel ret = rte_eth_tx_queue_setup(portid, queueid, nb_txd, 833e60f71ebSIntel rte_lcore_to_socket_id(lcore_id), &tx_conf); 834af75078fSIntel if (ret < 0) 835af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d, " 836af75078fSIntel "port=%d\n", ret, portid); 837af75078fSIntel 838af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 839af75078fSIntel qconf->tx_queue_id[portid] = queueid; 840af75078fSIntel queueid++; 841af75078fSIntel } 842af75078fSIntel 843af75078fSIntel /* Start device */ 844af75078fSIntel ret = rte_eth_dev_start(portid); 845af75078fSIntel if (ret < 0) 846af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%d\n", 847af75078fSIntel ret, portid); 848af75078fSIntel 849d3641ae8SIntel printf("done:\n"); 850af75078fSIntel } 851af75078fSIntel 852d3641ae8SIntel check_all_ports_link_status(nb_ports, enabled_port_mask); 853af75078fSIntel 854af75078fSIntel /* initialize the multicast hash */ 855af75078fSIntel int retval = init_mcast_hash(); 856af75078fSIntel if (retval != 0) 857af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot build the multicast hash\n"); 858af75078fSIntel 859af75078fSIntel /* launch per-lcore init on every lcore */ 860af75078fSIntel rte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER); 861af75078fSIntel RTE_LCORE_FOREACH_SLAVE(lcore_id) { 862af75078fSIntel if (rte_eal_wait_lcore(lcore_id) < 0) 863af75078fSIntel return -1; 864af75078fSIntel } 865af75078fSIntel 866af75078fSIntel return 0; 867af75078fSIntel } 868