xref: /dpdk/examples/ip_pipeline/examples/rss.cli (revision 9077d5a44ee859f63a1fe535036855df4dd8a33f) 
1; SPDX-License-Identifier: BSD-3-Clause
2; Copyright(c) 2010-2018 Intel Corporation
3
4; This setup demonstrates the usage of NIC Receive Side Scaling (RSS) feature.
5; Each NIC splits the input traffic into 4 RX queues, with each of its RX queues
6; being handled by a different pipeline:
7;
8;                                                    +-----------+    +----------+
9;                       +--------------------------->|           |    |          |
10;                       |       +------------------->| PIPELINE0 +--->|  LINK 0  |--->
11;                       |       |     +------------->| (CORE A)  |    |    TX    |
12;                       |       |     |     +------->|           |    |          |
13;                       |       |     |     |        +-----------+    +----------+
14;    +----------+       |       |     |     |
15;    |          |-------+       |     |     |
16;--->|  LINK 0  |-----------+   |     |     |
17;    |    RX    |---------+ |   |     |     |
18;    |          |-------+ | |   |     |     |
19;    +----------+       | | |   |     |     |        +-----------+    +----------+
20;                       | | +---|-----|-----|------->|           |    |          |
21;    +----------+       | |     | +---|-----|------->| PIPELINE1 +--->|  LINK 1  |--->
22;    |          |-------|-|-----+ |   | +---|------->| (CORE B)  |    |    TX    |
23;--->|  LINK 1  |-------|-|-------+   | |   | +----->|           |    |          |
24;    |    RX    |-------|-|-------+   | |   | |      +-----------+    +----------+
25;    |          |-------|-|-----+ |   | |   | |
26;    +----------+       | |     | |   | |   | |
27;                       | |     | |   | |   | |
28;    +----------+       | |     | |   | |   | |
29;    |          |-------|-|-----|-|---+ |   | |
30;--->|  LINK 2  |-------|-|-----|-|-----+   | |      +-----------+    +----------+
31;    |    RX    |-----+ | +-----|-|---------|-|----->|           |    |          |
32;    |          |---+ | |       | +---------|-|----->| PIPELINE2 +--->|  LINK 2  |--->
33;    +----------+   | +-|-------|-----------|-|----->| (CORE C)  |    |    TX    |
34;                   |   |       |           | | +--->|           |    |          |
35;    +----------+   |   |       |           | | |    +-----------+    +----------+
36;    |          |---|---|-------|-----------+ | |
37;--->|  LINK 3  |---|---|-------|-------------+ |
38;    |    RX    |---|---|-------|---------------+
39;    |          |---|---|-------|-----------+
40;    +----------+   |   |       |           |
41;                   |   |       |           |        +-----------+    +----------+
42;                   |   +-------|-----------|------->|           |    |          |
43;                   |           +-----------|------->| PIPELINE3 +--->|  LINK 3  |--->
44;                   +-----------------------|------->| (CORE D)  |    |    TX    |
45;                                           +------->|           |    |          |
46;                                                    +-----------+    +----------+
47;
48;
49
50mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
51
52link LINK0 dev 0000:02:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
53link LINK1 dev 0000:02:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
54link LINK2 dev 0000:06:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
55link LINK3 dev 0000:06:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3
56
57pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0
58pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0
59pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0
60pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0
61pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0
62pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0
63pipeline PIPELINE0 table match stub
64pipeline PIPELINE0 port in 0 table 0
65pipeline PIPELINE0 port in 1 table 0
66pipeline PIPELINE0 port in 2 table 0
67pipeline PIPELINE0 port in 3 table 0
68pipeline PIPELINE0 table 0 rule add match default action fwd port 0
69
70pipeline PIPELINE1 period 10 offset_port_id 0 cpu 0
71pipeline PIPELINE1 port in bsz 32 link LINK0 rxq 1
72pipeline PIPELINE1 port in bsz 32 link LINK1 rxq 1
73pipeline PIPELINE1 port in bsz 32 link LINK2 rxq 1
74pipeline PIPELINE1 port in bsz 32 link LINK3 rxq 1
75pipeline PIPELINE1 port out bsz 32 link LINK1 txq 0
76pipeline PIPELINE1 table match stub
77pipeline PIPELINE1 port in 0 table 0
78pipeline PIPELINE1 port in 1 table 0
79pipeline PIPELINE1 port in 2 table 0
80pipeline PIPELINE1 port in 3 table 0
81pipeline PIPELINE1 table 0 rule add match default action fwd port 0
82
83pipeline PIPELINE2 period 10 offset_port_id 0 cpu 0
84pipeline PIPELINE2 port in bsz 32 link LINK0 rxq 2
85pipeline PIPELINE2 port in bsz 32 link LINK1 rxq 2
86pipeline PIPELINE2 port in bsz 32 link LINK2 rxq 2
87pipeline PIPELINE2 port in bsz 32 link LINK3 rxq 2
88pipeline PIPELINE2 port out bsz 32 link LINK2 txq 0
89pipeline PIPELINE2 table match stub
90pipeline PIPELINE2 port in 0 table 0
91pipeline PIPELINE2 port in 1 table 0
92pipeline PIPELINE2 port in 2 table 0
93pipeline PIPELINE2 port in 3 table 0
94pipeline PIPELINE2 table 0 rule add match default action fwd port 0
95
96pipeline PIPELINE3 period 10 offset_port_id 0 cpu 0
97pipeline PIPELINE3 port in bsz 32 link LINK0 rxq 3
98pipeline PIPELINE3 port in bsz 32 link LINK1 rxq 3
99pipeline PIPELINE3 port in bsz 32 link LINK2 rxq 3
100pipeline PIPELINE3 port in bsz 32 link LINK3 rxq 3
101pipeline PIPELINE3 port out bsz 32 link LINK3 txq 0
102pipeline PIPELINE3 table match stub
103pipeline PIPELINE3 port in 0 table 0
104pipeline PIPELINE3 port in 1 table 0
105pipeline PIPELINE3 port in 2 table 0
106pipeline PIPELINE3 port in 3 table 0
107pipeline PIPELINE3 table 0 rule add match default action fwd port 0
108
109thread 1 pipeline PIPELINE0 enable
110thread 2 pipeline PIPELINE1 enable
111thread 3 pipeline PIPELINE2 enable
112thread 4 pipeline PIPELINE3 enable
113