1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 5 #include <getopt.h> 6 #include <stdint.h> 7 #include <stdio.h> 8 #include <signal.h> 9 #include <sched.h> 10 11 #include "pipeline_common.h" 12 13 struct config_data cdata = { 14 .num_packets = (1L << 25), /* do ~32M packets */ 15 .num_fids = 512, 16 .queue_type = RTE_SCHED_TYPE_ATOMIC, 17 .next_qid = {-1}, 18 .qid = {-1}, 19 .num_stages = 1, 20 .worker_cq_depth = 16 21 }; 22 23 static bool 24 core_in_use(unsigned int lcore_id) { 25 return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] || 26 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]); 27 } 28 29 /* 30 * Parse the coremask given as argument (hexadecimal string) and fill 31 * the global configuration (core role and core count) with the parsed 32 * value. 33 */ 34 static int xdigit2val(unsigned char c) 35 { 36 int val; 37 38 if (isdigit(c)) 39 val = c - '0'; 40 else if (isupper(c)) 41 val = c - 'A' + 10; 42 else 43 val = c - 'a' + 10; 44 return val; 45 } 46 47 static uint64_t 48 parse_coremask(const char *coremask) 49 { 50 int i, j, idx = 0; 51 unsigned int count = 0; 52 char c; 53 int val; 54 uint64_t mask = 0; 55 const int32_t BITS_HEX = 4; 56 57 if (coremask == NULL) 58 return -1; 59 /* Remove all blank characters ahead and after . 60 * Remove 0x/0X if exists. 61 */ 62 while (isblank(*coremask)) 63 coremask++; 64 if (coremask[0] == '0' && ((coremask[1] == 'x') 65 || (coremask[1] == 'X'))) 66 coremask += 2; 67 i = strlen(coremask); 68 while ((i > 0) && isblank(coremask[i - 1])) 69 i--; 70 if (i == 0) 71 return -1; 72 73 for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) { 74 c = coremask[i]; 75 if (isxdigit(c) == 0) { 76 /* invalid characters */ 77 return -1; 78 } 79 val = xdigit2val(c); 80 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) { 81 if ((1 << j) & val) { 82 mask |= (1UL << idx); 83 count++; 84 } 85 } 86 } 87 for (; i >= 0; i--) 88 if (coremask[i] != '0') 89 return -1; 90 if (count == 0) 91 return -1; 92 return mask; 93 } 94 95 static struct option long_options[] = { 96 {"workers", required_argument, 0, 'w'}, 97 {"packets", required_argument, 0, 'n'}, 98 {"atomic-flows", required_argument, 0, 'f'}, 99 {"num_stages", required_argument, 0, 's'}, 100 {"rx-mask", required_argument, 0, 'r'}, 101 {"tx-mask", required_argument, 0, 't'}, 102 {"sched-mask", required_argument, 0, 'e'}, 103 {"cq-depth", required_argument, 0, 'c'}, 104 {"work-cycles", required_argument, 0, 'W'}, 105 {"mempool-size", required_argument, 0, 'm'}, 106 {"queue-priority", no_argument, 0, 'P'}, 107 {"parallel", no_argument, 0, 'p'}, 108 {"ordered", no_argument, 0, 'o'}, 109 {"quiet", no_argument, 0, 'q'}, 110 {"use-atq", no_argument, 0, 'a'}, 111 {"dump", no_argument, 0, 'D'}, 112 {0, 0, 0, 0} 113 }; 114 115 static void 116 usage(void) 117 { 118 const char *usage_str = 119 " Usage: eventdev_demo [options]\n" 120 " Options:\n" 121 " -n, --packets=N Send N packets (default ~32M), 0 implies no limit\n" 122 " -f, --atomic-flows=N Use N random flows from 1 to N (default 16)\n" 123 " -s, --num_stages=N Use N atomic stages (default 1)\n" 124 " -r, --rx-mask=core mask Run NIC rx on CPUs in core mask\n" 125 " -w, --worker-mask=core mask Run worker on CPUs in core mask\n" 126 " -t, --tx-mask=core mask Run NIC tx on CPUs in core mask\n" 127 " -e --sched-mask=core mask Run scheduler on CPUs in core mask\n" 128 " -c --cq-depth=N Worker CQ depth (default 16)\n" 129 " -W --work-cycles=N Worker cycles (default 0)\n" 130 " -P --queue-priority Enable scheduler queue prioritization\n" 131 " -o, --ordered Use ordered scheduling\n" 132 " -p, --parallel Use parallel scheduling\n" 133 " -q, --quiet Minimize printed output\n" 134 " -a, --use-atq Use all type queues\n" 135 " -m, --mempool-size=N Dictate the mempool size\n" 136 " -D, --dump Print detailed statistics before exit" 137 "\n"; 138 fprintf(stderr, "%s", usage_str); 139 exit(1); 140 } 141 142 static void 143 parse_app_args(int argc, char **argv) 144 { 145 /* Parse cli options*/ 146 int option_index; 147 int c; 148 opterr = 0; 149 uint64_t rx_lcore_mask = 0; 150 uint64_t tx_lcore_mask = 0; 151 uint64_t sched_lcore_mask = 0; 152 uint64_t worker_lcore_mask = 0; 153 int i; 154 155 for (;;) { 156 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:m:paoPqDW:", 157 long_options, &option_index); 158 if (c == -1) 159 break; 160 161 int popcnt = 0; 162 switch (c) { 163 case 'n': 164 cdata.num_packets = (int64_t)atol(optarg); 165 if (cdata.num_packets == 0) 166 cdata.num_packets = INT64_MAX; 167 break; 168 case 'f': 169 cdata.num_fids = (unsigned int)atoi(optarg); 170 break; 171 case 's': 172 cdata.num_stages = (unsigned int)atoi(optarg); 173 break; 174 case 'c': 175 cdata.worker_cq_depth = (unsigned int)atoi(optarg); 176 break; 177 case 'W': 178 cdata.worker_cycles = (unsigned int)atoi(optarg); 179 break; 180 case 'P': 181 cdata.enable_queue_priorities = 1; 182 break; 183 case 'o': 184 cdata.queue_type = RTE_SCHED_TYPE_ORDERED; 185 break; 186 case 'p': 187 cdata.queue_type = RTE_SCHED_TYPE_PARALLEL; 188 break; 189 case 'a': 190 cdata.all_type_queues = 1; 191 break; 192 case 'q': 193 cdata.quiet = 1; 194 break; 195 case 'D': 196 cdata.dump_dev = 1; 197 break; 198 case 'w': 199 worker_lcore_mask = parse_coremask(optarg); 200 break; 201 case 'r': 202 rx_lcore_mask = parse_coremask(optarg); 203 popcnt = __builtin_popcountll(rx_lcore_mask); 204 fdata->rx_single = (popcnt == 1); 205 break; 206 case 't': 207 tx_lcore_mask = parse_coremask(optarg); 208 popcnt = __builtin_popcountll(tx_lcore_mask); 209 fdata->tx_single = (popcnt == 1); 210 break; 211 case 'e': 212 sched_lcore_mask = parse_coremask(optarg); 213 popcnt = __builtin_popcountll(sched_lcore_mask); 214 fdata->sched_single = (popcnt == 1); 215 break; 216 case 'm': 217 cdata.num_mbuf = (uint64_t)atol(optarg); 218 break; 219 default: 220 usage(); 221 } 222 } 223 224 cdata.worker_lcore_mask = worker_lcore_mask; 225 cdata.sched_lcore_mask = sched_lcore_mask; 226 cdata.rx_lcore_mask = rx_lcore_mask; 227 cdata.tx_lcore_mask = tx_lcore_mask; 228 229 if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES) 230 usage(); 231 232 for (i = 0; i < MAX_NUM_CORE; i++) { 233 fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i)); 234 fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i)); 235 fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i)); 236 fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i)); 237 238 if (fdata->worker_core[i]) 239 cdata.num_workers++; 240 if (core_in_use(i)) 241 cdata.active_cores++; 242 } 243 } 244 245 /* 246 * Initializes a given port using global settings and with the RX buffers 247 * coming from the mbuf_pool passed as a parameter. 248 */ 249 static inline int 250 port_init(uint8_t port, struct rte_mempool *mbuf_pool) 251 { 252 struct rte_eth_rxconf rx_conf; 253 static const struct rte_eth_conf port_conf_default = { 254 .rxmode = { 255 .mq_mode = ETH_MQ_RX_RSS, 256 .max_rx_pkt_len = ETHER_MAX_LEN, 257 }, 258 .rx_adv_conf = { 259 .rss_conf = { 260 .rss_hf = ETH_RSS_IP | 261 ETH_RSS_TCP | 262 ETH_RSS_UDP, 263 } 264 } 265 }; 266 const uint16_t rx_rings = 1, tx_rings = 1; 267 const uint16_t rx_ring_size = 512, tx_ring_size = 512; 268 struct rte_eth_conf port_conf = port_conf_default; 269 int retval; 270 uint16_t q; 271 struct rte_eth_dev_info dev_info; 272 struct rte_eth_txconf txconf; 273 274 if (!rte_eth_dev_is_valid_port(port)) 275 return -1; 276 277 rte_eth_dev_info_get(port, &dev_info); 278 if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 279 port_conf.txmode.offloads |= 280 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 281 rx_conf = dev_info.default_rxconf; 282 rx_conf.offloads = port_conf.rxmode.offloads; 283 284 port_conf.rx_adv_conf.rss_conf.rss_hf &= 285 dev_info.flow_type_rss_offloads; 286 if (port_conf.rx_adv_conf.rss_conf.rss_hf != 287 port_conf_default.rx_adv_conf.rss_conf.rss_hf) { 288 printf("Port %u modified RSS hash function based on hardware support," 289 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 290 port, 291 port_conf_default.rx_adv_conf.rss_conf.rss_hf, 292 port_conf.rx_adv_conf.rss_conf.rss_hf); 293 } 294 295 /* Configure the Ethernet device. */ 296 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf); 297 if (retval != 0) 298 return retval; 299 300 /* Allocate and set up 1 RX queue per Ethernet port. */ 301 for (q = 0; q < rx_rings; q++) { 302 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size, 303 rte_eth_dev_socket_id(port), &rx_conf, 304 mbuf_pool); 305 if (retval < 0) 306 return retval; 307 } 308 309 txconf = dev_info.default_txconf; 310 txconf.offloads = port_conf_default.txmode.offloads; 311 /* Allocate and set up 1 TX queue per Ethernet port. */ 312 for (q = 0; q < tx_rings; q++) { 313 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size, 314 rte_eth_dev_socket_id(port), &txconf); 315 if (retval < 0) 316 return retval; 317 } 318 319 /* Start the Ethernet port. */ 320 retval = rte_eth_dev_start(port); 321 if (retval < 0) 322 return retval; 323 324 /* Display the port MAC address. */ 325 struct ether_addr addr; 326 rte_eth_macaddr_get(port, &addr); 327 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8 328 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n", 329 (unsigned int)port, 330 addr.addr_bytes[0], addr.addr_bytes[1], 331 addr.addr_bytes[2], addr.addr_bytes[3], 332 addr.addr_bytes[4], addr.addr_bytes[5]); 333 334 /* Enable RX in promiscuous mode for the Ethernet device. */ 335 rte_eth_promiscuous_enable(port); 336 337 return 0; 338 } 339 340 static int 341 init_ports(uint16_t num_ports) 342 { 343 uint16_t portid; 344 345 if (!cdata.num_mbuf) 346 cdata.num_mbuf = 16384 * num_ports; 347 348 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool", 349 /* mbufs */ cdata.num_mbuf, 350 /* cache_size */ 512, 351 /* priv_size*/ 0, 352 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE, 353 rte_socket_id()); 354 355 RTE_ETH_FOREACH_DEV(portid) 356 if (port_init(portid, mp) != 0) 357 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n", 358 portid); 359 360 return 0; 361 } 362 363 static void 364 do_capability_setup(uint8_t eventdev_id) 365 { 366 int ret; 367 uint16_t i; 368 uint8_t generic_pipeline = 0; 369 uint8_t burst = 0; 370 371 RTE_ETH_FOREACH_DEV(i) { 372 uint32_t caps = 0; 373 374 ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, i, &caps); 375 if (ret) 376 rte_exit(EXIT_FAILURE, 377 "Invalid capability for Tx adptr port %d\n", i); 378 generic_pipeline |= !(caps & 379 RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT); 380 } 381 382 struct rte_event_dev_info eventdev_info; 383 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 384 385 rte_event_dev_info_get(eventdev_id, &eventdev_info); 386 burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 : 387 0; 388 389 if (generic_pipeline) 390 set_worker_generic_setup_data(&fdata->cap, burst); 391 else 392 set_worker_tx_enq_setup_data(&fdata->cap, burst); 393 } 394 395 static void 396 signal_handler(int signum) 397 { 398 static uint8_t once; 399 uint16_t portid; 400 401 if (fdata->done) 402 rte_exit(1, "Exiting on signal %d\n", signum); 403 if ((signum == SIGINT || signum == SIGTERM) && !once) { 404 printf("\n\nSignal %d received, preparing to exit...\n", 405 signum); 406 if (cdata.dump_dev) 407 rte_event_dev_dump(0, stdout); 408 once = 1; 409 fdata->done = 1; 410 rte_smp_wmb(); 411 412 RTE_ETH_FOREACH_DEV(portid) { 413 rte_event_eth_rx_adapter_stop(portid); 414 rte_event_eth_tx_adapter_stop(portid); 415 rte_eth_dev_stop(portid); 416 } 417 418 rte_eal_mp_wait_lcore(); 419 420 RTE_ETH_FOREACH_DEV(portid) { 421 rte_eth_dev_close(portid); 422 } 423 424 rte_event_dev_close(0); 425 } 426 if (signum == SIGTSTP) 427 rte_event_dev_dump(0, stdout); 428 } 429 430 static inline uint64_t 431 port_stat(int dev_id, int32_t p) 432 { 433 char statname[64]; 434 snprintf(statname, sizeof(statname), "port_%u_rx", p); 435 return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL); 436 } 437 438 int 439 main(int argc, char **argv) 440 { 441 struct worker_data *worker_data; 442 uint16_t num_ports; 443 int lcore_id; 444 int err; 445 446 signal(SIGINT, signal_handler); 447 signal(SIGTERM, signal_handler); 448 signal(SIGTSTP, signal_handler); 449 450 err = rte_eal_init(argc, argv); 451 if (err < 0) 452 rte_panic("Invalid EAL arguments\n"); 453 454 argc -= err; 455 argv += err; 456 457 fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0); 458 if (fdata == NULL) 459 rte_panic("Out of memory\n"); 460 461 /* Parse cli options*/ 462 parse_app_args(argc, argv); 463 464 num_ports = rte_eth_dev_count_avail(); 465 if (num_ports == 0) 466 rte_panic("No ethernet ports found\n"); 467 468 const unsigned int cores_needed = cdata.active_cores; 469 470 if (!cdata.quiet) { 471 printf(" Config:\n"); 472 printf("\tports: %u\n", num_ports); 473 printf("\tworkers: %u\n", cdata.num_workers); 474 printf("\tpackets: %"PRIi64"\n", cdata.num_packets); 475 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities); 476 if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED) 477 printf("\tqid0 type: ordered\n"); 478 if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC) 479 printf("\tqid0 type: atomic\n"); 480 printf("\tCores available: %u\n", rte_lcore_count()); 481 printf("\tCores used: %u\n", cores_needed); 482 } 483 484 if (rte_lcore_count() < cores_needed) 485 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(), 486 cores_needed); 487 488 const unsigned int ndevs = rte_event_dev_count(); 489 if (ndevs == 0) 490 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n"); 491 if (ndevs > 1) 492 fprintf(stderr, "Warning: More than one eventdev, using idx 0"); 493 494 495 do_capability_setup(0); 496 fdata->cap.check_opt(); 497 498 worker_data = rte_calloc(0, cdata.num_workers, 499 sizeof(worker_data[0]), 0); 500 if (worker_data == NULL) 501 rte_panic("rte_calloc failed\n"); 502 503 int dev_id = fdata->cap.evdev_setup(worker_data); 504 if (dev_id < 0) 505 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n"); 506 507 init_ports(num_ports); 508 fdata->cap.adptr_setup(num_ports); 509 510 int worker_idx = 0; 511 RTE_LCORE_FOREACH_SLAVE(lcore_id) { 512 if (lcore_id >= MAX_NUM_CORE) 513 break; 514 515 if (!fdata->rx_core[lcore_id] && 516 !fdata->worker_core[lcore_id] && 517 !fdata->tx_core[lcore_id] && 518 !fdata->sched_core[lcore_id]) 519 continue; 520 521 if (fdata->rx_core[lcore_id]) 522 printf( 523 "[%s()] lcore %d executing NIC Rx\n", 524 __func__, lcore_id); 525 526 if (fdata->tx_core[lcore_id]) 527 printf( 528 "[%s()] lcore %d executing NIC Tx\n", 529 __func__, lcore_id); 530 531 if (fdata->sched_core[lcore_id]) 532 printf("[%s()] lcore %d executing scheduler\n", 533 __func__, lcore_id); 534 535 if (fdata->worker_core[lcore_id]) 536 printf( 537 "[%s()] lcore %d executing worker, using eventdev port %u\n", 538 __func__, lcore_id, 539 worker_data[worker_idx].port_id); 540 541 err = rte_eal_remote_launch(fdata->cap.worker, 542 &worker_data[worker_idx], lcore_id); 543 if (err) { 544 rte_panic("Failed to launch worker on core %d\n", 545 lcore_id); 546 continue; 547 } 548 if (fdata->worker_core[lcore_id]) 549 worker_idx++; 550 } 551 552 lcore_id = rte_lcore_id(); 553 554 if (core_in_use(lcore_id)) 555 fdata->cap.worker(&worker_data[worker_idx++]); 556 557 rte_eal_mp_wait_lcore(); 558 559 if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) != 560 (uint64_t)-ENOTSUP)) { 561 printf("\nPort Workload distribution:\n"); 562 uint32_t i; 563 uint64_t tot_pkts = 0; 564 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0}; 565 for (i = 0; i < cdata.num_workers; i++) { 566 pkts_per_wkr[i] = 567 port_stat(dev_id, worker_data[i].port_id); 568 tot_pkts += pkts_per_wkr[i]; 569 } 570 for (i = 0; i < cdata.num_workers; i++) { 571 float pc = pkts_per_wkr[i] * 100 / 572 ((float)tot_pkts); 573 printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n", 574 i, pc, pkts_per_wkr[i]); 575 } 576 577 } 578 579 return 0; 580 } 581