xref: /dpdk/examples/eventdev_pipeline/main.c (revision 198b5448433ed329becaf47003faf038132fbb7f)
16d239dd5SPavan Nikhilesh /* SPDX-License-Identifier: BSD-3-Clause
26d239dd5SPavan Nikhilesh  * Copyright(c) 2016-2017 Intel Corporation
36d239dd5SPavan Nikhilesh  */
46d239dd5SPavan Nikhilesh 
56d239dd5SPavan Nikhilesh #include <getopt.h>
66d239dd5SPavan Nikhilesh #include <stdint.h>
76d239dd5SPavan Nikhilesh #include <stdio.h>
86d239dd5SPavan Nikhilesh #include <signal.h>
96d239dd5SPavan Nikhilesh #include <sched.h>
106d239dd5SPavan Nikhilesh 
116d239dd5SPavan Nikhilesh #include "pipeline_common.h"
126d239dd5SPavan Nikhilesh 
1378de15bbSTimothy Redaelli struct fastpath_data *fdata;
1478de15bbSTimothy Redaelli 
156d239dd5SPavan Nikhilesh struct config_data cdata = {
166d239dd5SPavan Nikhilesh 	.num_packets = (1L << 25), /* do ~32M packets */
176d239dd5SPavan Nikhilesh 	.num_fids = 512,
186d239dd5SPavan Nikhilesh 	.queue_type = RTE_SCHED_TYPE_ATOMIC,
196d239dd5SPavan Nikhilesh 	.next_qid = {-1},
206d239dd5SPavan Nikhilesh 	.qid = {-1},
216d239dd5SPavan Nikhilesh 	.num_stages = 1,
226d239dd5SPavan Nikhilesh 	.worker_cq_depth = 16
236d239dd5SPavan Nikhilesh };
246d239dd5SPavan Nikhilesh 
25*198b5448SFeifei Wang static void
26*198b5448SFeifei Wang dump_core_info(unsigned int lcore_id, struct worker_data *data,
27*198b5448SFeifei Wang 		unsigned int worker_idx)
28*198b5448SFeifei Wang {
29*198b5448SFeifei Wang 	if (fdata->rx_core[lcore_id])
30*198b5448SFeifei Wang 		printf(
31*198b5448SFeifei Wang 			"[%s()] lcore %d executing NIC Rx\n",
32*198b5448SFeifei Wang 			__func__, lcore_id);
33*198b5448SFeifei Wang 
34*198b5448SFeifei Wang 	if (fdata->tx_core[lcore_id])
35*198b5448SFeifei Wang 		printf(
36*198b5448SFeifei Wang 			"[%s()] lcore %d executing NIC Tx\n",
37*198b5448SFeifei Wang 			__func__, lcore_id);
38*198b5448SFeifei Wang 
39*198b5448SFeifei Wang 	if (fdata->sched_core[lcore_id])
40*198b5448SFeifei Wang 		printf(
41*198b5448SFeifei Wang 			"[%s()] lcore %d executing scheduler\n",
42*198b5448SFeifei Wang 			__func__, lcore_id);
43*198b5448SFeifei Wang 
44*198b5448SFeifei Wang 	if (fdata->worker_core[lcore_id])
45*198b5448SFeifei Wang 		printf(
46*198b5448SFeifei Wang 			"[%s()] lcore %d executing worker, using eventdev port %u\n",
47*198b5448SFeifei Wang 			__func__, lcore_id,
48*198b5448SFeifei Wang 			data[worker_idx].port_id);
49*198b5448SFeifei Wang }
50*198b5448SFeifei Wang 
516d239dd5SPavan Nikhilesh static bool
526d239dd5SPavan Nikhilesh core_in_use(unsigned int lcore_id) {
536d239dd5SPavan Nikhilesh 	return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
546d239dd5SPavan Nikhilesh 		fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
556d239dd5SPavan Nikhilesh }
566d239dd5SPavan Nikhilesh 
576d239dd5SPavan Nikhilesh /*
586d239dd5SPavan Nikhilesh  * Parse the coremask given as argument (hexadecimal string) and fill
596d239dd5SPavan Nikhilesh  * the global configuration (core role and core count) with the parsed
606d239dd5SPavan Nikhilesh  * value.
616d239dd5SPavan Nikhilesh  */
626d239dd5SPavan Nikhilesh static int xdigit2val(unsigned char c)
636d239dd5SPavan Nikhilesh {
646d239dd5SPavan Nikhilesh 	int val;
656d239dd5SPavan Nikhilesh 
666d239dd5SPavan Nikhilesh 	if (isdigit(c))
676d239dd5SPavan Nikhilesh 		val = c - '0';
686d239dd5SPavan Nikhilesh 	else if (isupper(c))
696d239dd5SPavan Nikhilesh 		val = c - 'A' + 10;
706d239dd5SPavan Nikhilesh 	else
716d239dd5SPavan Nikhilesh 		val = c - 'a' + 10;
726d239dd5SPavan Nikhilesh 	return val;
736d239dd5SPavan Nikhilesh }
746d239dd5SPavan Nikhilesh 
756d239dd5SPavan Nikhilesh static uint64_t
766d239dd5SPavan Nikhilesh parse_coremask(const char *coremask)
776d239dd5SPavan Nikhilesh {
786d239dd5SPavan Nikhilesh 	int i, j, idx = 0;
796d239dd5SPavan Nikhilesh 	unsigned int count = 0;
806d239dd5SPavan Nikhilesh 	char c;
816d239dd5SPavan Nikhilesh 	int val;
826d239dd5SPavan Nikhilesh 	uint64_t mask = 0;
836d239dd5SPavan Nikhilesh 	const int32_t BITS_HEX = 4;
846d239dd5SPavan Nikhilesh 
856d239dd5SPavan Nikhilesh 	if (coremask == NULL)
866d239dd5SPavan Nikhilesh 		return -1;
876d239dd5SPavan Nikhilesh 	/* Remove all blank characters ahead and after .
886d239dd5SPavan Nikhilesh 	 * Remove 0x/0X if exists.
896d239dd5SPavan Nikhilesh 	 */
906d239dd5SPavan Nikhilesh 	while (isblank(*coremask))
916d239dd5SPavan Nikhilesh 		coremask++;
926d239dd5SPavan Nikhilesh 	if (coremask[0] == '0' && ((coremask[1] == 'x')
936d239dd5SPavan Nikhilesh 		|| (coremask[1] == 'X')))
946d239dd5SPavan Nikhilesh 		coremask += 2;
956d239dd5SPavan Nikhilesh 	i = strlen(coremask);
966d239dd5SPavan Nikhilesh 	while ((i > 0) && isblank(coremask[i - 1]))
976d239dd5SPavan Nikhilesh 		i--;
986d239dd5SPavan Nikhilesh 	if (i == 0)
996d239dd5SPavan Nikhilesh 		return -1;
1006d239dd5SPavan Nikhilesh 
1016d239dd5SPavan Nikhilesh 	for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
1026d239dd5SPavan Nikhilesh 		c = coremask[i];
1036d239dd5SPavan Nikhilesh 		if (isxdigit(c) == 0) {
1046d239dd5SPavan Nikhilesh 			/* invalid characters */
1056d239dd5SPavan Nikhilesh 			return -1;
1066d239dd5SPavan Nikhilesh 		}
1076d239dd5SPavan Nikhilesh 		val = xdigit2val(c);
1086d239dd5SPavan Nikhilesh 		for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
1096d239dd5SPavan Nikhilesh 			if ((1 << j) & val) {
110ff0f1040SHarry van Haaren 				mask |= (1ULL << idx);
1116d239dd5SPavan Nikhilesh 				count++;
1126d239dd5SPavan Nikhilesh 			}
1136d239dd5SPavan Nikhilesh 		}
1146d239dd5SPavan Nikhilesh 	}
1156d239dd5SPavan Nikhilesh 	for (; i >= 0; i--)
1166d239dd5SPavan Nikhilesh 		if (coremask[i] != '0')
1176d239dd5SPavan Nikhilesh 			return -1;
1186d239dd5SPavan Nikhilesh 	if (count == 0)
1196d239dd5SPavan Nikhilesh 		return -1;
1206d239dd5SPavan Nikhilesh 	return mask;
1216d239dd5SPavan Nikhilesh }
1226d239dd5SPavan Nikhilesh 
1236d239dd5SPavan Nikhilesh static struct option long_options[] = {
1246d239dd5SPavan Nikhilesh 	{"workers", required_argument, 0, 'w'},
1256d239dd5SPavan Nikhilesh 	{"packets", required_argument, 0, 'n'},
1266d239dd5SPavan Nikhilesh 	{"atomic-flows", required_argument, 0, 'f'},
1276d239dd5SPavan Nikhilesh 	{"num_stages", required_argument, 0, 's'},
1286d239dd5SPavan Nikhilesh 	{"rx-mask", required_argument, 0, 'r'},
1296d239dd5SPavan Nikhilesh 	{"tx-mask", required_argument, 0, 't'},
1306d239dd5SPavan Nikhilesh 	{"sched-mask", required_argument, 0, 'e'},
1316d239dd5SPavan Nikhilesh 	{"cq-depth", required_argument, 0, 'c'},
1326d239dd5SPavan Nikhilesh 	{"work-cycles", required_argument, 0, 'W'},
1336d239dd5SPavan Nikhilesh 	{"mempool-size", required_argument, 0, 'm'},
1346d239dd5SPavan Nikhilesh 	{"queue-priority", no_argument, 0, 'P'},
1356d239dd5SPavan Nikhilesh 	{"parallel", no_argument, 0, 'p'},
1366d239dd5SPavan Nikhilesh 	{"ordered", no_argument, 0, 'o'},
1376d239dd5SPavan Nikhilesh 	{"quiet", no_argument, 0, 'q'},
1386d239dd5SPavan Nikhilesh 	{"use-atq", no_argument, 0, 'a'},
1396d239dd5SPavan Nikhilesh 	{"dump", no_argument, 0, 'D'},
1406d239dd5SPavan Nikhilesh 	{0, 0, 0, 0}
1416d239dd5SPavan Nikhilesh };
1426d239dd5SPavan Nikhilesh 
1436d239dd5SPavan Nikhilesh static void
1446d239dd5SPavan Nikhilesh usage(void)
1456d239dd5SPavan Nikhilesh {
1466d239dd5SPavan Nikhilesh 	const char *usage_str =
1476d239dd5SPavan Nikhilesh 		"  Usage: eventdev_demo [options]\n"
1486d239dd5SPavan Nikhilesh 		"  Options:\n"
1496d239dd5SPavan Nikhilesh 		"  -n, --packets=N              Send N packets (default ~32M), 0 implies no limit\n"
1506d239dd5SPavan Nikhilesh 		"  -f, --atomic-flows=N         Use N random flows from 1 to N (default 16)\n"
1516d239dd5SPavan Nikhilesh 		"  -s, --num_stages=N           Use N atomic stages (default 1)\n"
1526d239dd5SPavan Nikhilesh 		"  -r, --rx-mask=core mask      Run NIC rx on CPUs in core mask\n"
1536d239dd5SPavan Nikhilesh 		"  -w, --worker-mask=core mask  Run worker on CPUs in core mask\n"
1546d239dd5SPavan Nikhilesh 		"  -t, --tx-mask=core mask      Run NIC tx on CPUs in core mask\n"
1556d239dd5SPavan Nikhilesh 		"  -e  --sched-mask=core mask   Run scheduler on CPUs in core mask\n"
1566d239dd5SPavan Nikhilesh 		"  -c  --cq-depth=N             Worker CQ depth (default 16)\n"
1576d239dd5SPavan Nikhilesh 		"  -W  --work-cycles=N          Worker cycles (default 0)\n"
1586d239dd5SPavan Nikhilesh 		"  -P  --queue-priority         Enable scheduler queue prioritization\n"
1596d239dd5SPavan Nikhilesh 		"  -o, --ordered                Use ordered scheduling\n"
1606d239dd5SPavan Nikhilesh 		"  -p, --parallel               Use parallel scheduling\n"
1616d239dd5SPavan Nikhilesh 		"  -q, --quiet                  Minimize printed output\n"
1626d239dd5SPavan Nikhilesh 		"  -a, --use-atq                Use all type queues\n"
1636d239dd5SPavan Nikhilesh 		"  -m, --mempool-size=N         Dictate the mempool size\n"
1646d239dd5SPavan Nikhilesh 		"  -D, --dump                   Print detailed statistics before exit"
1656d239dd5SPavan Nikhilesh 		"\n";
1666d239dd5SPavan Nikhilesh 	fprintf(stderr, "%s", usage_str);
1676d239dd5SPavan Nikhilesh 	exit(1);
1686d239dd5SPavan Nikhilesh }
1696d239dd5SPavan Nikhilesh 
1706d239dd5SPavan Nikhilesh static void
1716d239dd5SPavan Nikhilesh parse_app_args(int argc, char **argv)
1726d239dd5SPavan Nikhilesh {
1736d239dd5SPavan Nikhilesh 	/* Parse cli options*/
1746d239dd5SPavan Nikhilesh 	int option_index;
1756d239dd5SPavan Nikhilesh 	int c;
1766d239dd5SPavan Nikhilesh 	opterr = 0;
1776d239dd5SPavan Nikhilesh 	uint64_t rx_lcore_mask = 0;
1786d239dd5SPavan Nikhilesh 	uint64_t tx_lcore_mask = 0;
1796d239dd5SPavan Nikhilesh 	uint64_t sched_lcore_mask = 0;
1806d239dd5SPavan Nikhilesh 	uint64_t worker_lcore_mask = 0;
1816d239dd5SPavan Nikhilesh 	int i;
1826d239dd5SPavan Nikhilesh 
1836d239dd5SPavan Nikhilesh 	for (;;) {
1846d239dd5SPavan Nikhilesh 		c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:m:paoPqDW:",
1856d239dd5SPavan Nikhilesh 				long_options, &option_index);
1866d239dd5SPavan Nikhilesh 		if (c == -1)
1876d239dd5SPavan Nikhilesh 			break;
1886d239dd5SPavan Nikhilesh 
1896d239dd5SPavan Nikhilesh 		int popcnt = 0;
1906d239dd5SPavan Nikhilesh 		switch (c) {
1916d239dd5SPavan Nikhilesh 		case 'n':
1926d239dd5SPavan Nikhilesh 			cdata.num_packets = (int64_t)atol(optarg);
1936d239dd5SPavan Nikhilesh 			if (cdata.num_packets == 0)
1946d239dd5SPavan Nikhilesh 				cdata.num_packets = INT64_MAX;
1956d239dd5SPavan Nikhilesh 			break;
1966d239dd5SPavan Nikhilesh 		case 'f':
1976d239dd5SPavan Nikhilesh 			cdata.num_fids = (unsigned int)atoi(optarg);
1986d239dd5SPavan Nikhilesh 			break;
1996d239dd5SPavan Nikhilesh 		case 's':
2006d239dd5SPavan Nikhilesh 			cdata.num_stages = (unsigned int)atoi(optarg);
2016d239dd5SPavan Nikhilesh 			break;
2026d239dd5SPavan Nikhilesh 		case 'c':
2036d239dd5SPavan Nikhilesh 			cdata.worker_cq_depth = (unsigned int)atoi(optarg);
2046d239dd5SPavan Nikhilesh 			break;
2056d239dd5SPavan Nikhilesh 		case 'W':
2066d239dd5SPavan Nikhilesh 			cdata.worker_cycles = (unsigned int)atoi(optarg);
2076d239dd5SPavan Nikhilesh 			break;
2086d239dd5SPavan Nikhilesh 		case 'P':
2096d239dd5SPavan Nikhilesh 			cdata.enable_queue_priorities = 1;
2106d239dd5SPavan Nikhilesh 			break;
2116d239dd5SPavan Nikhilesh 		case 'o':
2126d239dd5SPavan Nikhilesh 			cdata.queue_type = RTE_SCHED_TYPE_ORDERED;
2136d239dd5SPavan Nikhilesh 			break;
2146d239dd5SPavan Nikhilesh 		case 'p':
2156d239dd5SPavan Nikhilesh 			cdata.queue_type = RTE_SCHED_TYPE_PARALLEL;
2166d239dd5SPavan Nikhilesh 			break;
2176d239dd5SPavan Nikhilesh 		case 'a':
2186d239dd5SPavan Nikhilesh 			cdata.all_type_queues = 1;
2196d239dd5SPavan Nikhilesh 			break;
2206d239dd5SPavan Nikhilesh 		case 'q':
2216d239dd5SPavan Nikhilesh 			cdata.quiet = 1;
2226d239dd5SPavan Nikhilesh 			break;
2236d239dd5SPavan Nikhilesh 		case 'D':
2246d239dd5SPavan Nikhilesh 			cdata.dump_dev = 1;
2256d239dd5SPavan Nikhilesh 			break;
2266d239dd5SPavan Nikhilesh 		case 'w':
2276d239dd5SPavan Nikhilesh 			worker_lcore_mask = parse_coremask(optarg);
2286d239dd5SPavan Nikhilesh 			break;
2296d239dd5SPavan Nikhilesh 		case 'r':
2306d239dd5SPavan Nikhilesh 			rx_lcore_mask = parse_coremask(optarg);
2316d239dd5SPavan Nikhilesh 			popcnt = __builtin_popcountll(rx_lcore_mask);
2326d239dd5SPavan Nikhilesh 			fdata->rx_single = (popcnt == 1);
2336d239dd5SPavan Nikhilesh 			break;
2346d239dd5SPavan Nikhilesh 		case 't':
2356d239dd5SPavan Nikhilesh 			tx_lcore_mask = parse_coremask(optarg);
2366d239dd5SPavan Nikhilesh 			popcnt = __builtin_popcountll(tx_lcore_mask);
2376d239dd5SPavan Nikhilesh 			fdata->tx_single = (popcnt == 1);
2386d239dd5SPavan Nikhilesh 			break;
2396d239dd5SPavan Nikhilesh 		case 'e':
2406d239dd5SPavan Nikhilesh 			sched_lcore_mask = parse_coremask(optarg);
2416d239dd5SPavan Nikhilesh 			popcnt = __builtin_popcountll(sched_lcore_mask);
2426d239dd5SPavan Nikhilesh 			fdata->sched_single = (popcnt == 1);
2436d239dd5SPavan Nikhilesh 			break;
2446d239dd5SPavan Nikhilesh 		case 'm':
2456d239dd5SPavan Nikhilesh 			cdata.num_mbuf = (uint64_t)atol(optarg);
2466d239dd5SPavan Nikhilesh 			break;
2476d239dd5SPavan Nikhilesh 		default:
2486d239dd5SPavan Nikhilesh 			usage();
2496d239dd5SPavan Nikhilesh 		}
2506d239dd5SPavan Nikhilesh 	}
2516d239dd5SPavan Nikhilesh 
2526d239dd5SPavan Nikhilesh 	cdata.worker_lcore_mask = worker_lcore_mask;
2536d239dd5SPavan Nikhilesh 	cdata.sched_lcore_mask = sched_lcore_mask;
2546d239dd5SPavan Nikhilesh 	cdata.rx_lcore_mask = rx_lcore_mask;
2556d239dd5SPavan Nikhilesh 	cdata.tx_lcore_mask = tx_lcore_mask;
2566d239dd5SPavan Nikhilesh 
2576d239dd5SPavan Nikhilesh 	if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
2586d239dd5SPavan Nikhilesh 		usage();
2596d239dd5SPavan Nikhilesh 
2606d239dd5SPavan Nikhilesh 	for (i = 0; i < MAX_NUM_CORE; i++) {
261ff0f1040SHarry van Haaren 		fdata->rx_core[i] = !!(rx_lcore_mask & (1ULL << i));
262ff0f1040SHarry van Haaren 		fdata->tx_core[i] = !!(tx_lcore_mask & (1ULL << i));
263ff0f1040SHarry van Haaren 		fdata->sched_core[i] = !!(sched_lcore_mask & (1ULL << i));
264ff0f1040SHarry van Haaren 		fdata->worker_core[i] = !!(worker_lcore_mask & (1ULL << i));
2656d239dd5SPavan Nikhilesh 
2666d239dd5SPavan Nikhilesh 		if (fdata->worker_core[i])
2676d239dd5SPavan Nikhilesh 			cdata.num_workers++;
2683d159134SFeifei Wang 		if (core_in_use(i)) {
2693d159134SFeifei Wang 			if (!rte_lcore_is_enabled(i)) {
2703d159134SFeifei Wang 				printf("lcore %d is not enabled in lcore list\n",
2713d159134SFeifei Wang 					i);
2723d159134SFeifei Wang 				rte_exit(EXIT_FAILURE,
2733d159134SFeifei Wang 					"check lcore params failed\n");
2743d159134SFeifei Wang 			}
2756d239dd5SPavan Nikhilesh 			cdata.active_cores++;
2766d239dd5SPavan Nikhilesh 		}
2776d239dd5SPavan Nikhilesh 	}
2783d159134SFeifei Wang }
2796d239dd5SPavan Nikhilesh 
2806d239dd5SPavan Nikhilesh static void
2818728ccf3SThomas Monjalon do_capability_setup(uint8_t eventdev_id)
2826d239dd5SPavan Nikhilesh {
283085edac2SPavan Nikhilesh 	int ret;
2848728ccf3SThomas Monjalon 	uint16_t i;
285085edac2SPavan Nikhilesh 	uint8_t generic_pipeline = 0;
2866d239dd5SPavan Nikhilesh 	uint8_t burst = 0;
2876d239dd5SPavan Nikhilesh 
2888728ccf3SThomas Monjalon 	RTE_ETH_FOREACH_DEV(i) {
289085edac2SPavan Nikhilesh 		uint32_t caps = 0;
2906d239dd5SPavan Nikhilesh 
291085edac2SPavan Nikhilesh 		ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, i, &caps);
292085edac2SPavan Nikhilesh 		if (ret)
293085edac2SPavan Nikhilesh 			rte_exit(EXIT_FAILURE,
294085edac2SPavan Nikhilesh 				"Invalid capability for Tx adptr port %d\n", i);
295085edac2SPavan Nikhilesh 		generic_pipeline |= !(caps &
296085edac2SPavan Nikhilesh 				RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT);
2976d239dd5SPavan Nikhilesh 	}
2986d239dd5SPavan Nikhilesh 
2996d239dd5SPavan Nikhilesh 	struct rte_event_dev_info eventdev_info;
3006d239dd5SPavan Nikhilesh 	memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
3016d239dd5SPavan Nikhilesh 
3026d239dd5SPavan Nikhilesh 	rte_event_dev_info_get(eventdev_id, &eventdev_info);
3036d239dd5SPavan Nikhilesh 	burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 :
3046d239dd5SPavan Nikhilesh 		0;
3056d239dd5SPavan Nikhilesh 
306085edac2SPavan Nikhilesh 	if (generic_pipeline)
3076d239dd5SPavan Nikhilesh 		set_worker_generic_setup_data(&fdata->cap, burst);
3086d239dd5SPavan Nikhilesh 	else
309085edac2SPavan Nikhilesh 		set_worker_tx_enq_setup_data(&fdata->cap, burst);
3106d239dd5SPavan Nikhilesh }
3116d239dd5SPavan Nikhilesh 
3126d239dd5SPavan Nikhilesh static void
3136d239dd5SPavan Nikhilesh signal_handler(int signum)
3146d239dd5SPavan Nikhilesh {
315085edac2SPavan Nikhilesh 	static uint8_t once;
316085edac2SPavan Nikhilesh 	uint16_t portid;
317085edac2SPavan Nikhilesh 
3186d239dd5SPavan Nikhilesh 	if (fdata->done)
3196d239dd5SPavan Nikhilesh 		rte_exit(1, "Exiting on signal %d\n", signum);
320085edac2SPavan Nikhilesh 	if ((signum == SIGINT || signum == SIGTERM) && !once) {
3216d239dd5SPavan Nikhilesh 		printf("\n\nSignal %d received, preparing to exit...\n",
3226d239dd5SPavan Nikhilesh 				signum);
323085edac2SPavan Nikhilesh 		if (cdata.dump_dev)
324085edac2SPavan Nikhilesh 			rte_event_dev_dump(0, stdout);
325085edac2SPavan Nikhilesh 		once = 1;
3266d239dd5SPavan Nikhilesh 		fdata->done = 1;
327085edac2SPavan Nikhilesh 		rte_smp_wmb();
328085edac2SPavan Nikhilesh 
329085edac2SPavan Nikhilesh 		RTE_ETH_FOREACH_DEV(portid) {
330085edac2SPavan Nikhilesh 			rte_event_eth_rx_adapter_stop(portid);
331085edac2SPavan Nikhilesh 			rte_event_eth_tx_adapter_stop(portid);
332b55efbabSIvan Ilchenko 			if (rte_eth_dev_stop(portid) < 0)
333b55efbabSIvan Ilchenko 				printf("Failed to stop port %u", portid);
334085edac2SPavan Nikhilesh 		}
335085edac2SPavan Nikhilesh 
336085edac2SPavan Nikhilesh 		rte_eal_mp_wait_lcore();
337085edac2SPavan Nikhilesh 
3386d239dd5SPavan Nikhilesh 	}
3396d239dd5SPavan Nikhilesh 	if (signum == SIGTSTP)
3406d239dd5SPavan Nikhilesh 		rte_event_dev_dump(0, stdout);
3416d239dd5SPavan Nikhilesh }
3426d239dd5SPavan Nikhilesh 
3436d239dd5SPavan Nikhilesh static inline uint64_t
3446d239dd5SPavan Nikhilesh port_stat(int dev_id, int32_t p)
3456d239dd5SPavan Nikhilesh {
3466d239dd5SPavan Nikhilesh 	char statname[64];
3476d239dd5SPavan Nikhilesh 	snprintf(statname, sizeof(statname), "port_%u_rx", p);
3486d239dd5SPavan Nikhilesh 	return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
3496d239dd5SPavan Nikhilesh }
3506d239dd5SPavan Nikhilesh 
3516d239dd5SPavan Nikhilesh int
3526d239dd5SPavan Nikhilesh main(int argc, char **argv)
3536d239dd5SPavan Nikhilesh {
3546d239dd5SPavan Nikhilesh 	struct worker_data *worker_data;
355d9a42a69SThomas Monjalon 	uint16_t num_ports;
35666af142fSPavan Nikhilesh 	uint16_t portid;
3576d239dd5SPavan Nikhilesh 	int lcore_id;
3586d239dd5SPavan Nikhilesh 	int err;
3596d239dd5SPavan Nikhilesh 
3606d239dd5SPavan Nikhilesh 	signal(SIGINT, signal_handler);
3616d239dd5SPavan Nikhilesh 	signal(SIGTERM, signal_handler);
3626d239dd5SPavan Nikhilesh 	signal(SIGTSTP, signal_handler);
3636d239dd5SPavan Nikhilesh 
3646d239dd5SPavan Nikhilesh 	err = rte_eal_init(argc, argv);
3656d239dd5SPavan Nikhilesh 	if (err < 0)
3666d239dd5SPavan Nikhilesh 		rte_panic("Invalid EAL arguments\n");
3676d239dd5SPavan Nikhilesh 
3686d239dd5SPavan Nikhilesh 	argc -= err;
3696d239dd5SPavan Nikhilesh 	argv += err;
3706d239dd5SPavan Nikhilesh 
3716d239dd5SPavan Nikhilesh 	fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
3726d239dd5SPavan Nikhilesh 	if (fdata == NULL)
3736d239dd5SPavan Nikhilesh 		rte_panic("Out of memory\n");
3746d239dd5SPavan Nikhilesh 
3756d239dd5SPavan Nikhilesh 	/* Parse cli options*/
3766d239dd5SPavan Nikhilesh 	parse_app_args(argc, argv);
3776d239dd5SPavan Nikhilesh 
378d9a42a69SThomas Monjalon 	num_ports = rte_eth_dev_count_avail();
3796d239dd5SPavan Nikhilesh 	if (num_ports == 0)
3806d239dd5SPavan Nikhilesh 		rte_panic("No ethernet ports found\n");
3816d239dd5SPavan Nikhilesh 
3826d239dd5SPavan Nikhilesh 	const unsigned int cores_needed = cdata.active_cores;
3836d239dd5SPavan Nikhilesh 
3846d239dd5SPavan Nikhilesh 	if (!cdata.quiet) {
3856d239dd5SPavan Nikhilesh 		printf("  Config:\n");
3866d239dd5SPavan Nikhilesh 		printf("\tports: %u\n", num_ports);
3876d239dd5SPavan Nikhilesh 		printf("\tworkers: %u\n", cdata.num_workers);
3886d239dd5SPavan Nikhilesh 		printf("\tpackets: %"PRIi64"\n", cdata.num_packets);
3896d239dd5SPavan Nikhilesh 		printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
3906d239dd5SPavan Nikhilesh 		if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED)
3916d239dd5SPavan Nikhilesh 			printf("\tqid0 type: ordered\n");
3926d239dd5SPavan Nikhilesh 		if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC)
3936d239dd5SPavan Nikhilesh 			printf("\tqid0 type: atomic\n");
3946d239dd5SPavan Nikhilesh 		printf("\tCores available: %u\n", rte_lcore_count());
3956d239dd5SPavan Nikhilesh 		printf("\tCores used: %u\n", cores_needed);
3966d239dd5SPavan Nikhilesh 	}
3976d239dd5SPavan Nikhilesh 
3986d239dd5SPavan Nikhilesh 	if (rte_lcore_count() < cores_needed)
3996d239dd5SPavan Nikhilesh 		rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
4006d239dd5SPavan Nikhilesh 				cores_needed);
4016d239dd5SPavan Nikhilesh 
4026d239dd5SPavan Nikhilesh 	const unsigned int ndevs = rte_event_dev_count();
4036d239dd5SPavan Nikhilesh 	if (ndevs == 0)
4046d239dd5SPavan Nikhilesh 		rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
4056d239dd5SPavan Nikhilesh 	if (ndevs > 1)
4066d239dd5SPavan Nikhilesh 		fprintf(stderr, "Warning: More than one eventdev, using idx 0");
4076d239dd5SPavan Nikhilesh 
4086d239dd5SPavan Nikhilesh 
4098728ccf3SThomas Monjalon 	do_capability_setup(0);
4106d239dd5SPavan Nikhilesh 	fdata->cap.check_opt();
4116d239dd5SPavan Nikhilesh 
4126d239dd5SPavan Nikhilesh 	worker_data = rte_calloc(0, cdata.num_workers,
4136d239dd5SPavan Nikhilesh 			sizeof(worker_data[0]), 0);
4146d239dd5SPavan Nikhilesh 	if (worker_data == NULL)
4156d239dd5SPavan Nikhilesh 		rte_panic("rte_calloc failed\n");
4166d239dd5SPavan Nikhilesh 
417085edac2SPavan Nikhilesh 	int dev_id = fdata->cap.evdev_setup(worker_data);
4186d239dd5SPavan Nikhilesh 	if (dev_id < 0)
4196d239dd5SPavan Nikhilesh 		rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
4206d239dd5SPavan Nikhilesh 
4216d239dd5SPavan Nikhilesh 	fdata->cap.adptr_setup(num_ports);
4226d239dd5SPavan Nikhilesh 
42366af142fSPavan Nikhilesh 	/* Start the Ethernet port. */
42466af142fSPavan Nikhilesh 	RTE_ETH_FOREACH_DEV(portid) {
42566af142fSPavan Nikhilesh 		err = rte_eth_dev_start(portid);
42666af142fSPavan Nikhilesh 		if (err < 0)
42766af142fSPavan Nikhilesh 			rte_exit(EXIT_FAILURE, "Error starting ethdev %d\n",
42866af142fSPavan Nikhilesh 					portid);
42966af142fSPavan Nikhilesh 	}
43066af142fSPavan Nikhilesh 
4316d239dd5SPavan Nikhilesh 	int worker_idx = 0;
432cb056611SStephen Hemminger 	RTE_LCORE_FOREACH_WORKER(lcore_id) {
4336d239dd5SPavan Nikhilesh 		if (lcore_id >= MAX_NUM_CORE)
4346d239dd5SPavan Nikhilesh 			break;
4356d239dd5SPavan Nikhilesh 
4366d239dd5SPavan Nikhilesh 		if (!fdata->rx_core[lcore_id] &&
4376d239dd5SPavan Nikhilesh 			!fdata->worker_core[lcore_id] &&
4386d239dd5SPavan Nikhilesh 			!fdata->tx_core[lcore_id] &&
4396d239dd5SPavan Nikhilesh 			!fdata->sched_core[lcore_id])
4406d239dd5SPavan Nikhilesh 			continue;
4416d239dd5SPavan Nikhilesh 
442*198b5448SFeifei Wang 		dump_core_info(lcore_id, worker_data, worker_idx);
4436d239dd5SPavan Nikhilesh 
4446d239dd5SPavan Nikhilesh 		err = rte_eal_remote_launch(fdata->cap.worker,
4456d239dd5SPavan Nikhilesh 				&worker_data[worker_idx], lcore_id);
4466d239dd5SPavan Nikhilesh 		if (err) {
4476d239dd5SPavan Nikhilesh 			rte_panic("Failed to launch worker on core %d\n",
4486d239dd5SPavan Nikhilesh 					lcore_id);
4496d239dd5SPavan Nikhilesh 			continue;
4506d239dd5SPavan Nikhilesh 		}
4516d239dd5SPavan Nikhilesh 		if (fdata->worker_core[lcore_id])
4526d239dd5SPavan Nikhilesh 			worker_idx++;
4536d239dd5SPavan Nikhilesh 	}
4546d239dd5SPavan Nikhilesh 
4556d239dd5SPavan Nikhilesh 	lcore_id = rte_lcore_id();
4566d239dd5SPavan Nikhilesh 
457*198b5448SFeifei Wang 	if (core_in_use(lcore_id)) {
458*198b5448SFeifei Wang 		dump_core_info(lcore_id, worker_data, worker_idx);
459*198b5448SFeifei Wang 		fdata->cap.worker(&worker_data[worker_idx]);
460*198b5448SFeifei Wang 
461*198b5448SFeifei Wang 		if (fdata->worker_core[lcore_id])
462*198b5448SFeifei Wang 			worker_idx++;
463*198b5448SFeifei Wang 	}
4646d239dd5SPavan Nikhilesh 
4656d239dd5SPavan Nikhilesh 	rte_eal_mp_wait_lcore();
4666d239dd5SPavan Nikhilesh 
4676d239dd5SPavan Nikhilesh 	if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
4686d239dd5SPavan Nikhilesh 			(uint64_t)-ENOTSUP)) {
4696d239dd5SPavan Nikhilesh 		printf("\nPort Workload distribution:\n");
4706d239dd5SPavan Nikhilesh 		uint32_t i;
4716d239dd5SPavan Nikhilesh 		uint64_t tot_pkts = 0;
4726d239dd5SPavan Nikhilesh 		uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
4736d239dd5SPavan Nikhilesh 		for (i = 0; i < cdata.num_workers; i++) {
4746d239dd5SPavan Nikhilesh 			pkts_per_wkr[i] =
4756d239dd5SPavan Nikhilesh 				port_stat(dev_id, worker_data[i].port_id);
4766d239dd5SPavan Nikhilesh 			tot_pkts += pkts_per_wkr[i];
4776d239dd5SPavan Nikhilesh 		}
4786d239dd5SPavan Nikhilesh 		for (i = 0; i < cdata.num_workers; i++) {
4796d239dd5SPavan Nikhilesh 			float pc = pkts_per_wkr[i]  * 100 /
4806d239dd5SPavan Nikhilesh 				((float)tot_pkts);
4816d239dd5SPavan Nikhilesh 			printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
4826d239dd5SPavan Nikhilesh 					i, pc, pkts_per_wkr[i]);
4836d239dd5SPavan Nikhilesh 		}
4846d239dd5SPavan Nikhilesh 
4856d239dd5SPavan Nikhilesh 	}
4866d239dd5SPavan Nikhilesh 
4872c434431SHarry van Haaren 	RTE_ETH_FOREACH_DEV(portid) {
4882c434431SHarry van Haaren 		rte_eth_dev_close(portid);
4892c434431SHarry van Haaren 	}
4902c434431SHarry van Haaren 
4912c434431SHarry van Haaren 	rte_event_dev_stop(0);
4922c434431SHarry van Haaren 	rte_event_dev_close(0);
4932c434431SHarry van Haaren 
4942c434431SHarry van Haaren 	rte_eal_cleanup();
4952c434431SHarry van Haaren 
4966d239dd5SPavan Nikhilesh 	return 0;
4976d239dd5SPavan Nikhilesh }
498