1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_REGEX_RXP_H_ 6 #define RTE_PMD_MLX5_REGEX_RXP_H_ 7 8 #define MLX5_RXP_MAX_JOB_LENGTH 16384 9 #define MLX5_RXP_MAX_SUBSETS 4095 10 #define MLX5_RXP_CSR_NUM_ENTRIES 31 11 12 #define MLX5_RXP_CTRL_TYPE_MASK 7 13 #define MLX5_RXP_CTRL_TYPE_JOB_DESCRIPTOR 0 14 #define MLX5_RXP_CTRL_TYPE_RESPONSE_DESCRIPTOR 1 15 #define MLX5_RXP_CTRL_TYPE_MEMORY_WRITE 4 16 #define MLX5_RXP_CSR_CTRL_DISABLE_L2C (1 << 7) 17 18 #define MLX5_RXP_CTRL_JOB_DESC_SOF 0x0010 19 #define MLX5_RXP_CTRL_JOB_DESC_EOF 0x0020 20 #define MLX5_RXP_CTRL_JOB_DESC_HPM_ENABLE 0x0100 21 #define MLX5_RXP_CTRL_JOB_DESC_ANYMATCH_ENABLE 0x0200 22 #define MLX5_RXP_CTRL_JOB_DESC_FLAGS (MLX5_RXP_CTRL_JOB_DESC_SOF | \ 23 MLX5_RXP_CTRL_JOB_DESC_EOF | \ 24 MLX5_RXP_CTRL_JOB_DESC_HPM_ENABLE | \ 25 MLX5_RXP_CTRL_JOB_DESC_ANYMATCH_ENABLE) 26 27 #define MLX5_RXP_CTRL_VALID 0x8000 28 29 #define MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS (1 << 3) 30 #define MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS (1 << 4) 31 #define MLX5_RXP_RESP_STATUS_MAX_LATENCY (1 << 5) 32 #define MLX5_RXP_RESP_STATUS_MAX_MATCH (1 << 6) 33 #define MLX5_RXP_RESP_STATUS_MAX_PREFIX (1 << 7) 34 #define MLX5_RXP_RESP_STATUS_HPM (1 << 8) 35 #define MLX5_RXP_RESP_STATUS_ANYMATCH (1 << 9) 36 #define MLX5_RXP_RESP_STATUS_PMI_SOJ (1 << 13) 37 #define MLX5_RXP_RESP_STATUS_PMI_EOJ (1 << 14) 38 39 /* This describes the header the RXP expects for any search data. */ 40 struct mlx5_rxp_job_desc { 41 uint32_t job_id; 42 uint16_t ctrl; 43 uint16_t len; 44 uint16_t subset[4]; 45 } __rte_packed; 46 47 struct mlx5_rxp_response_desc { 48 uint32_t job_id; 49 uint16_t status; 50 uint8_t detected_match_count; 51 uint8_t match_count; 52 uint16_t primary_thread_count; 53 uint16_t instruction_count; 54 uint16_t latency_count; 55 uint16_t pmi_min_byte_ptr; 56 } __rte_packed; 57 58 struct mlx5_rxp_match_tuple { 59 uint32_t rule_id; 60 uint16_t start_ptr; 61 uint16_t length; 62 } __rte_packed; 63 64 struct mlx5_rxp_response { 65 struct mlx5_rxp_response_desc header; 66 struct mlx5_rxp_match_tuple matches[0]; 67 }; 68 69 #define MLX5_RXP_MAX_MATCHES 254 70 71 #define MLX5_RXP_CTL_RULES_PGM 1 72 #define MLX5_RXP_CTL_RULES_PGM_INCR 2 73 74 #define MLX5_RXP_ROF_ENTRY_INST 0 75 #define MLX5_RXP_ROF_ENTRY_EQ 1 76 #define MLX5_RXP_ROF_ENTRY_GTE 2 77 #define MLX5_RXP_ROF_ENTRY_LTE 3 78 #define MLX5_RXP_ROF_ENTRY_CHECKSUM 4 79 #define MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM 5 80 #define MLX5_RXP_ROF_ENTRY_IM 6 81 #define MLX5_RXP_ROF_ENTRY_EM 7 82 #define MLX5_RXP_ROF_ENTRY_TYPE_MAX 7 83 84 #define MLX5_RXP_INST_OFFSET 3 85 #define MLX5_RXP_INST_BLOCK_SIZE 8 86 #define MLX5_MAX_SIZE_RES_DES (sizeof(struct mlx5_rxp_response_desc)) 87 #define MLX5_MAX_DB_SIZE (1u << 27u) 88 #define MLX5_MAX_SIZE_MATCH_RESP (254 * sizeof(struct mlx5_rxp_match_tuple)) 89 #define MLX5_RXP_SQ_NOT_BUSY false 90 #define MLX5_RXP_SQ_BUSY true 91 92 93 struct mlx5_rxp_ctl_hdr { 94 uint16_t cmd; 95 uint32_t len; 96 }; 97 98 struct mlx5_rxp_rof_entry { 99 uint8_t type; 100 uint32_t addr; 101 uint64_t value; 102 }; 103 104 struct mlx5_rxp_rof { 105 uint32_t rof_version; 106 char *timestamp; 107 char *rxp_compiler_version; 108 uint32_t rof_revision; 109 uint32_t number_of_entries; 110 struct mlx5_rxp_rof_entry *rof_entries; 111 }; 112 113 struct mlx5_rxp_ctl_rules_pgm { 114 struct mlx5_rxp_ctl_hdr hdr; 115 uint32_t count; 116 struct mlx5_rxp_rof_entry rules[0]; 117 } __rte_packed; 118 119 /* RXP programming mode setting. */ 120 enum mlx5_rxp_program_mode { 121 MLX5_RXP_MODE_NOT_DEFINED = 0, 122 MLX5_RXP_SHARED_PROG_MODE, 123 MLX5_RXP_PRIVATE_PROG_MODE, 124 }; 125 126 #define MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT 3000 /* Poll timeout in ms. */ 127 #define MLX5_RXP_INITIALIZATION_TIMEOUT 60000 /* Initialize timeout in ms. */ 128 #define MLX5_RXP_MAX_ENGINES 2u /* Number of RXP engines. */ 129 #define MLX5_RXP_EM_COUNT 1u /* Extra External Memories to use. */ 130 #define MLX5_RXP_DB_NOT_ASSIGNED 0xFF 131 132 struct mlx5_regex_umem { 133 struct mlx5dv_devx_umem *umem; 134 uint32_t id; 135 uint64_t offset; 136 }; 137 138 #endif /* RTE_PMD_MLX5_REGEX_RXP_H_ */ 139