1cf9b3c36SYuval Avnery /* SPDX-License-Identifier: BSD-3-Clause 2cf9b3c36SYuval Avnery * Copyright 2020 Mellanox Technologies, Ltd 3cf9b3c36SYuval Avnery */ 4cf9b3c36SYuval Avnery 5cf9b3c36SYuval Avnery #ifndef MLX5_REGEX_H 6cf9b3c36SYuval Avnery #define MLX5_REGEX_H 7cf9b3c36SYuval Avnery 89428310aSOri Kam #include <rte_regexdev.h> 99428310aSOri Kam 10*e3dbbf71SOri Kam struct mlx5_regex_sq { 11*e3dbbf71SOri Kam uint32_t nb_desc; /* Number of desc for this object. */ 12*e3dbbf71SOri Kam }; 13*e3dbbf71SOri Kam 14*e3dbbf71SOri Kam struct mlx5_regex_qp { 15*e3dbbf71SOri Kam uint32_t flags; /* QP user flags. */ 16*e3dbbf71SOri Kam uint32_t nb_desc; /* Total number of desc for this qp. */ 17*e3dbbf71SOri Kam struct mlx5_regex_sq *sqs; /* Pointer to sq array. */ 18*e3dbbf71SOri Kam }; 19*e3dbbf71SOri Kam 20cfc672a9SOri Kam struct mlx5_regex_priv { 21cfc672a9SOri Kam TAILQ_ENTRY(mlx5_regex_priv) next; 22cfc672a9SOri Kam struct ibv_context *ctx; /* Device context. */ 23cfc672a9SOri Kam struct rte_pci_device *pci_dev; 24cfc672a9SOri Kam struct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */ 25*e3dbbf71SOri Kam uint16_t nb_queues; /* Number of queues. */ 26*e3dbbf71SOri Kam struct mlx5_regex_qp *qps; /* Pointer to the qp array. */ 27*e3dbbf71SOri Kam uint16_t nb_max_matches; /* Max number of matches. */ 28cfc672a9SOri Kam }; 29c126512bSOri Kam 30c126512bSOri Kam /* mlx5_rxp.c */ 31c126512bSOri Kam int mlx5_regex_info_get(struct rte_regexdev *dev, 32c126512bSOri Kam struct rte_regexdev_info *info); 33*e3dbbf71SOri Kam int mlx5_regex_configure(struct rte_regexdev *dev, 34*e3dbbf71SOri Kam const struct rte_regexdev_config *cfg); 35c126512bSOri Kam 369428310aSOri Kam /* mlx5_regex_devx.c */ 379428310aSOri Kam int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id, 389428310aSOri Kam uint32_t addr, uint32_t data); 399428310aSOri Kam int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id, 409428310aSOri Kam uint32_t addr, uint32_t *data); 419428310aSOri Kam 42cf9b3c36SYuval Avnery #endif /* MLX5_REGEX_H */ 43