1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_pci.h> 9 #include <rte_regexdev.h> 10 #include <rte_regexdev_core.h> 11 #include <rte_regexdev_driver.h> 12 #include <rte_bus_pci.h> 13 14 #include <mlx5_common.h> 15 #include <mlx5_common_mr.h> 16 #include <mlx5_glue.h> 17 #include <mlx5_devx_cmds.h> 18 #include <mlx5_prm.h> 19 20 #include "mlx5_regex.h" 21 #include "mlx5_regex_utils.h" 22 #include "mlx5_rxp_csrs.h" 23 24 #define MLX5_REGEX_DRIVER_NAME regex_mlx5 25 26 int mlx5_regex_logtype; 27 28 TAILQ_HEAD(regex_mem_event, mlx5_regex_priv) mlx5_mem_event_list = 29 TAILQ_HEAD_INITIALIZER(mlx5_mem_event_list); 30 static pthread_mutex_t mem_event_list_lock = PTHREAD_MUTEX_INITIALIZER; 31 32 const struct rte_regexdev_ops mlx5_regexdev_ops = { 33 .dev_info_get = mlx5_regex_info_get, 34 .dev_configure = mlx5_regex_configure, 35 .dev_db_import = mlx5_regex_rules_db_import, 36 .dev_qp_setup = mlx5_regex_qp_setup, 37 .dev_start = mlx5_regex_start, 38 .dev_stop = mlx5_regex_stop, 39 .dev_close = mlx5_regex_close, 40 }; 41 42 int 43 mlx5_regex_start(struct rte_regexdev *dev __rte_unused) 44 { 45 return 0; 46 } 47 48 int 49 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused) 50 { 51 return 0; 52 } 53 54 int 55 mlx5_regex_close(struct rte_regexdev *dev __rte_unused) 56 { 57 return 0; 58 } 59 60 static int 61 mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines) 62 { 63 uint32_t fpga_ident = 0; 64 int err; 65 int i; 66 67 for (i = 0; i < num_engines; i++) { 68 err = mlx5_devx_regex_register_read(ctx, i, 69 MLX5_RXP_CSR_IDENTIFIER, 70 &fpga_ident); 71 fpga_ident = (fpga_ident & (0x0000FFFF)); 72 if (err || fpga_ident != MLX5_RXP_IDENTIFIER) { 73 DRV_LOG(ERR, "Failed setup RXP %d err %d database " 74 "memory 0x%x", i, err, fpga_ident); 75 if (!err) 76 err = EINVAL; 77 return err; 78 } 79 } 80 return 0; 81 } 82 83 static void 84 mlx5_regex_get_name(char *name, struct rte_device *dev) 85 { 86 sprintf(name, "mlx5_regex_%s", dev->name); 87 } 88 89 /** 90 * Callback for memory event. 91 * 92 * @param event_type 93 * Memory event type. 94 * @param addr 95 * Address of memory. 96 * @param len 97 * Size of memory. 98 */ 99 static void 100 mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 101 size_t len, void *arg __rte_unused) 102 { 103 struct mlx5_regex_priv *priv; 104 105 /* Must be called from the primary process. */ 106 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 107 switch (event_type) { 108 case RTE_MEM_EVENT_FREE: 109 pthread_mutex_lock(&mem_event_list_lock); 110 /* Iterate all the existing mlx5 devices. */ 111 TAILQ_FOREACH(priv, &mlx5_mem_event_list, mem_event_cb) 112 mlx5_free_mr_by_addr(&priv->mr_scache, 113 mlx5_os_get_ctx_device_name 114 (priv->cdev->ctx), 115 addr, len); 116 pthread_mutex_unlock(&mem_event_list_lock); 117 break; 118 case RTE_MEM_EVENT_ALLOC: 119 default: 120 break; 121 } 122 } 123 124 static int 125 mlx5_regex_dev_probe(struct mlx5_common_device *cdev) 126 { 127 struct mlx5_regex_priv *priv = NULL; 128 struct mlx5_hca_attr attr; 129 char name[RTE_REGEXDEV_NAME_MAX_LEN]; 130 int ret; 131 uint32_t val; 132 133 ret = mlx5_devx_cmd_query_hca_attr(cdev->ctx, &attr); 134 if (ret) { 135 DRV_LOG(ERR, "Unable to read HCA capabilities."); 136 rte_errno = ENOTSUP; 137 return -rte_errno; 138 } else if (((!attr.regex) && (!attr.mmo_regex_sq_en) && 139 (!attr.mmo_regex_qp_en)) || attr.regexp_num_of_engines == 0) { 140 DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe " 141 "old FW/OFED version?"); 142 rte_errno = ENOTSUP; 143 return -rte_errno; 144 } 145 if (mlx5_regex_engines_status(cdev->ctx, 2)) { 146 DRV_LOG(ERR, "RegEx engine error."); 147 rte_errno = ENOMEM; 148 return -rte_errno; 149 } 150 priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv), 151 RTE_CACHE_LINE_SIZE); 152 if (!priv) { 153 DRV_LOG(ERR, "Failed to allocate private memory."); 154 rte_errno = ENOMEM; 155 return -rte_errno; 156 } 157 priv->mmo_regex_qp_cap = attr.mmo_regex_qp_en; 158 priv->mmo_regex_sq_cap = attr.mmo_regex_sq_en; 159 priv->qp_ts_format = attr.qp_ts_format; 160 priv->cdev = cdev; 161 priv->nb_engines = 2; /* attr.regexp_num_of_engines */ 162 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, 0, 163 MLX5_RXP_CSR_IDENTIFIER, &val); 164 if (ret) { 165 DRV_LOG(ERR, "CSR read failed!"); 166 goto dev_error; 167 } 168 if (val == MLX5_RXP_BF2_IDENTIFIER) 169 priv->is_bf2 = 1; 170 /* Default RXP programming mode to Shared. */ 171 priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE; 172 mlx5_regex_get_name(name, cdev->dev); 173 priv->regexdev = rte_regexdev_register(name); 174 if (priv->regexdev == NULL) { 175 DRV_LOG(ERR, "Failed to register RegEx device."); 176 rte_errno = rte_errno ? rte_errno : EINVAL; 177 goto dev_error; 178 } 179 /* 180 * This PMD always claims the write memory barrier on UAR 181 * registers writings, it is safe to allocate UAR with any 182 * memory mapping type. 183 */ 184 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1); 185 if (!priv->uar) { 186 DRV_LOG(ERR, "can't allocate uar."); 187 rte_errno = ENOMEM; 188 goto error; 189 } 190 priv->pd = mlx5_glue->alloc_pd(priv->cdev->ctx); 191 if (!priv->pd) { 192 DRV_LOG(ERR, "can't allocate pd."); 193 rte_errno = ENOMEM; 194 goto error; 195 } 196 priv->regexdev->dev_ops = &mlx5_regexdev_ops; 197 priv->regexdev->enqueue = mlx5_regexdev_enqueue; 198 #ifdef HAVE_MLX5_UMR_IMKEY 199 if (!attr.umr_indirect_mkey_disabled && 200 !attr.umr_modify_entity_size_disabled) 201 priv->has_umr = 1; 202 if (priv->has_umr) 203 priv->regexdev->enqueue = mlx5_regexdev_enqueue_gga; 204 #endif 205 priv->regexdev->dequeue = mlx5_regexdev_dequeue; 206 priv->regexdev->device = cdev->dev; 207 priv->regexdev->data->dev_private = priv; 208 priv->regexdev->state = RTE_REGEXDEV_READY; 209 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 210 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 211 ret = mlx5_mr_btree_init(&priv->mr_scache.cache, 212 MLX5_MR_BTREE_CACHE_N * 2, 213 rte_socket_id()); 214 if (ret) { 215 DRV_LOG(ERR, "MR init tree failed."); 216 rte_errno = ENOMEM; 217 goto error; 218 } 219 /* Register callback function for global shared MR cache management. */ 220 if (TAILQ_EMPTY(&mlx5_mem_event_list)) 221 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 222 mlx5_regex_mr_mem_event_cb, 223 NULL); 224 /* Add device to memory callback list. */ 225 pthread_mutex_lock(&mem_event_list_lock); 226 TAILQ_INSERT_TAIL(&mlx5_mem_event_list, priv, mem_event_cb); 227 pthread_mutex_unlock(&mem_event_list_lock); 228 DRV_LOG(INFO, "RegEx GGA is %s.", 229 priv->has_umr ? "supported" : "unsupported"); 230 return 0; 231 232 error: 233 if (priv->pd) 234 mlx5_glue->dealloc_pd(priv->pd); 235 if (priv->uar) 236 mlx5_glue->devx_free_uar(priv->uar); 237 if (priv->regexdev) 238 rte_regexdev_unregister(priv->regexdev); 239 dev_error: 240 if (priv) 241 rte_free(priv); 242 return -rte_errno; 243 } 244 245 static int 246 mlx5_regex_dev_remove(struct mlx5_common_device *cdev) 247 { 248 char name[RTE_REGEXDEV_NAME_MAX_LEN]; 249 struct rte_regexdev *dev; 250 struct mlx5_regex_priv *priv = NULL; 251 252 mlx5_regex_get_name(name, cdev->dev); 253 dev = rte_regexdev_get_device_by_name(name); 254 if (!dev) 255 return 0; 256 priv = dev->data->dev_private; 257 if (priv) { 258 /* Remove from memory callback device list. */ 259 pthread_mutex_lock(&mem_event_list_lock); 260 TAILQ_REMOVE(&mlx5_mem_event_list, priv, mem_event_cb); 261 pthread_mutex_unlock(&mem_event_list_lock); 262 if (TAILQ_EMPTY(&mlx5_mem_event_list)) 263 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", 264 NULL); 265 if (priv->mr_scache.cache.table) 266 mlx5_mr_release_cache(&priv->mr_scache); 267 if (priv->pd) 268 mlx5_glue->dealloc_pd(priv->pd); 269 if (priv->uar) 270 mlx5_glue->devx_free_uar(priv->uar); 271 if (priv->regexdev) 272 rte_regexdev_unregister(priv->regexdev); 273 rte_free(priv); 274 } 275 return 0; 276 } 277 278 static const struct rte_pci_id mlx5_regex_pci_id_map[] = { 279 { 280 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 281 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 282 }, 283 { 284 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 285 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF) 286 }, 287 { 288 .vendor_id = 0 289 } 290 }; 291 292 static struct mlx5_class_driver mlx5_regex_driver = { 293 .drv_class = MLX5_CLASS_REGEX, 294 .name = RTE_STR(MLX5_REGEX_DRIVER_NAME), 295 .id_table = mlx5_regex_pci_id_map, 296 .probe = mlx5_regex_dev_probe, 297 .remove = mlx5_regex_dev_remove, 298 }; 299 300 RTE_INIT(rte_mlx5_regex_init) 301 { 302 mlx5_common_init(); 303 if (mlx5_glue) 304 mlx5_class_driver_register(&mlx5_regex_driver); 305 } 306 307 RTE_LOG_REGISTER_DEFAULT(mlx5_regex_logtype, NOTICE) 308 RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__); 309 RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map); 310 RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 311