1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <rte_malloc.h> 6 #include <rte_log.h> 7 #include <rte_errno.h> 8 #include <rte_pci.h> 9 #include <rte_regexdev.h> 10 #include <rte_regexdev_core.h> 11 #include <rte_regexdev_driver.h> 12 13 #include <mlx5_common_pci.h> 14 #include <mlx5_glue.h> 15 #include <mlx5_devx_cmds.h> 16 #include <mlx5_prm.h> 17 18 #include "mlx5_regex.h" 19 #include "mlx5_regex_utils.h" 20 #include "mlx5_rxp_csrs.h" 21 22 #define MLX5_REGEX_DRIVER_NAME regex_mlx5 23 #define MLX5_REGEX_LOG_NAME pmd.regex.mlx5 24 25 int mlx5_regex_logtype; 26 27 const struct rte_regexdev_ops mlx5_regexdev_ops = { 28 .dev_info_get = mlx5_regex_info_get, 29 .dev_configure = mlx5_regex_configure, 30 .dev_db_import = mlx5_regex_rules_db_import, 31 .dev_qp_setup = mlx5_regex_qp_setup, 32 .dev_start = mlx5_regex_start, 33 .dev_stop = mlx5_regex_stop, 34 .dev_close = mlx5_regex_close, 35 }; 36 37 int 38 mlx5_regex_start(struct rte_regexdev *dev __rte_unused) 39 { 40 return 0; 41 } 42 43 int 44 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused) 45 { 46 return 0; 47 } 48 49 int 50 mlx5_regex_close(struct rte_regexdev *dev __rte_unused) 51 { 52 return 0; 53 } 54 55 static struct ibv_device * 56 mlx5_regex_get_ib_device_match(struct rte_pci_addr *addr) 57 { 58 int n; 59 struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n); 60 struct ibv_device *ibv_match = NULL; 61 62 if (!ibv_list) { 63 rte_errno = ENOSYS; 64 return NULL; 65 } 66 while (n-- > 0) { 67 struct rte_pci_addr pci_addr; 68 69 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name); 70 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &pci_addr)) 71 continue; 72 if (rte_pci_addr_cmp(addr, &pci_addr)) 73 continue; 74 ibv_match = ibv_list[n]; 75 break; 76 } 77 if (!ibv_match) 78 rte_errno = ENOENT; 79 mlx5_glue->free_device_list(ibv_list); 80 return ibv_match; 81 } 82 static int 83 mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines) 84 { 85 uint32_t fpga_ident = 0; 86 int err; 87 int i; 88 89 for (i = 0; i < num_engines; i++) { 90 err = mlx5_devx_regex_register_read(ctx, i, 91 MLX5_RXP_CSR_IDENTIFIER, 92 &fpga_ident); 93 fpga_ident = (fpga_ident & (0x0000FFFF)); 94 if (err || fpga_ident != MLX5_RXP_IDENTIFIER) { 95 DRV_LOG(ERR, "Failed setup RXP %d err %d database " 96 "memory 0x%x", i, err, fpga_ident); 97 if (!err) 98 err = EINVAL; 99 return err; 100 } 101 } 102 return 0; 103 } 104 105 static void 106 mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused) 107 { 108 sprintf(name, "mlx5_regex_%02x:%02x.%02x", pci_dev->addr.bus, 109 pci_dev->addr.devid, pci_dev->addr.function); 110 } 111 112 static int 113 mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 114 struct rte_pci_device *pci_dev) 115 { 116 struct ibv_device *ibv; 117 struct mlx5_regex_priv *priv = NULL; 118 struct ibv_context *ctx = NULL; 119 struct mlx5_hca_attr attr; 120 char name[RTE_REGEXDEV_NAME_MAX_LEN]; 121 int ret; 122 uint32_t val; 123 124 ibv = mlx5_regex_get_ib_device_match(&pci_dev->addr); 125 if (!ibv) { 126 DRV_LOG(ERR, "No matching IB device for PCI slot " 127 PCI_PRI_FMT ".", pci_dev->addr.domain, 128 pci_dev->addr.bus, pci_dev->addr.devid, 129 pci_dev->addr.function); 130 return -rte_errno; 131 } 132 DRV_LOG(INFO, "PCI information matches for device \"%s\".", 133 ibv->name); 134 ctx = mlx5_glue->dv_open_device(ibv); 135 if (!ctx) { 136 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); 137 rte_errno = ENODEV; 138 return -rte_errno; 139 } 140 ret = mlx5_devx_cmd_query_hca_attr(ctx, &attr); 141 if (ret) { 142 DRV_LOG(ERR, "Unable to read HCA capabilities."); 143 rte_errno = ENOTSUP; 144 goto dev_error; 145 } else if (!attr.regex || attr.regexp_num_of_engines == 0) { 146 DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe " 147 "old FW/OFED version?"); 148 rte_errno = ENOTSUP; 149 goto dev_error; 150 } 151 if (mlx5_regex_engines_status(ctx, 2)) { 152 DRV_LOG(ERR, "RegEx engine error."); 153 rte_errno = ENOMEM; 154 goto dev_error; 155 } 156 priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv), 157 RTE_CACHE_LINE_SIZE); 158 if (!priv) { 159 DRV_LOG(ERR, "Failed to allocate private memory."); 160 rte_errno = ENOMEM; 161 goto dev_error; 162 } 163 priv->ctx = ctx; 164 priv->nb_engines = 2; /* attr.regexp_num_of_engines */ 165 ret = mlx5_devx_regex_register_read(priv->ctx, 0, 166 MLX5_RXP_CSR_IDENTIFIER, &val); 167 if (ret) { 168 DRV_LOG(ERR, "CSR read failed!"); 169 return -1; 170 } 171 if (val == MLX5_RXP_BF2_IDENTIFIER) 172 priv->is_bf2 = 1; 173 /* Default RXP programming mode to Shared. */ 174 priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE; 175 mlx5_regex_get_name(name, pci_dev); 176 priv->regexdev = rte_regexdev_register(name); 177 if (priv->regexdev == NULL) { 178 DRV_LOG(ERR, "Failed to register RegEx device."); 179 rte_errno = rte_errno ? rte_errno : EINVAL; 180 goto error; 181 } 182 /* 183 * This PMD always claims the write memory barrier on UAR 184 * registers writings, it is safe to allocate UAR with any 185 * memory mapping type. 186 */ 187 priv->uar = mlx5_devx_alloc_uar(ctx, -1); 188 if (!priv->uar) { 189 DRV_LOG(ERR, "can't allocate uar."); 190 rte_errno = ENOMEM; 191 goto error; 192 } 193 priv->pd = mlx5_glue->alloc_pd(ctx); 194 if (!priv->pd) { 195 DRV_LOG(ERR, "can't allocate pd."); 196 rte_errno = ENOMEM; 197 goto error; 198 } 199 priv->regexdev->dev_ops = &mlx5_regexdev_ops; 200 priv->regexdev->enqueue = mlx5_regexdev_enqueue; 201 priv->regexdev->dequeue = mlx5_regexdev_dequeue; 202 priv->regexdev->device = (struct rte_device *)pci_dev; 203 priv->regexdev->data->dev_private = priv; 204 priv->regexdev->state = RTE_REGEXDEV_READY; 205 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; 206 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; 207 ret = mlx5_mr_btree_init(&priv->mr_scache.cache, 208 MLX5_MR_BTREE_CACHE_N * 2, 209 rte_socket_id()); 210 if (ret) { 211 DRV_LOG(ERR, "MR init tree failed."); 212 rte_errno = ENOMEM; 213 goto error; 214 } 215 return 0; 216 217 error: 218 if (priv->pd) 219 mlx5_glue->dealloc_pd(priv->pd); 220 if (priv->uar) 221 mlx5_glue->devx_free_uar(priv->uar); 222 if (priv->regexdev) 223 rte_regexdev_unregister(priv->regexdev); 224 dev_error: 225 if (ctx) 226 mlx5_glue->close_device(ctx); 227 if (priv) 228 rte_free(priv); 229 return -rte_errno; 230 } 231 232 static int 233 mlx5_regex_pci_remove(struct rte_pci_device *pci_dev) 234 { 235 char name[RTE_REGEXDEV_NAME_MAX_LEN]; 236 struct rte_regexdev *dev; 237 struct mlx5_regex_priv *priv = NULL; 238 239 mlx5_regex_get_name(name, pci_dev); 240 dev = rte_regexdev_get_device_by_name(name); 241 if (!dev) 242 return 0; 243 priv = dev->data->dev_private; 244 if (priv) { 245 if (priv->pd) 246 mlx5_glue->dealloc_pd(priv->pd); 247 if (priv->uar) 248 mlx5_glue->devx_free_uar(priv->uar); 249 if (priv->regexdev) 250 rte_regexdev_unregister(priv->regexdev); 251 if (priv->ctx) 252 mlx5_glue->close_device(priv->ctx); 253 if (priv->regexdev) 254 rte_regexdev_unregister(priv->regexdev); 255 rte_free(priv); 256 } 257 return 0; 258 } 259 260 static const struct rte_pci_id mlx5_regex_pci_id_map[] = { 261 { 262 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 263 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 264 }, 265 { 266 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 267 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF) 268 }, 269 { 270 .vendor_id = 0 271 } 272 }; 273 274 static struct mlx5_pci_driver mlx5_regex_driver = { 275 .driver_class = MLX5_CLASS_REGEX, 276 .pci_driver = { 277 .driver = { 278 .name = RTE_STR(MLX5_REGEX_DRIVER_NAME), 279 }, 280 .id_table = mlx5_regex_pci_id_map, 281 .probe = mlx5_regex_pci_probe, 282 .remove = mlx5_regex_pci_remove, 283 .drv_flags = 0, 284 }, 285 }; 286 287 RTE_INIT(rte_mlx5_regex_init) 288 { 289 mlx5_common_init(); 290 if (mlx5_glue) 291 mlx5_pci_driver_register(&mlx5_regex_driver); 292 } 293 294 RTE_LOG_REGISTER(mlx5_regex_logtype, MLX5_REGEX_LOG_NAME, NOTICE) 295 RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__); 296 RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map); 297 RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 298