1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2019 Intel Corporation 3 */ 4 5 #include "opae_intel_max10.h" 6 #include <libfdt.h> 7 #include "opae_osdep.h" 8 9 #ifndef TAILQ_FOREACH_SAFE 10 #define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ 11 for ((var) = TAILQ_FIRST((head)); \ 12 (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ 13 (var) = (tvar)) 14 #endif 15 16 int max10_sys_read(struct intel_max10_device *dev, 17 unsigned int offset, unsigned int *val) 18 { 19 if (!dev || !dev->ops->reg_read) 20 return -ENODEV; 21 22 return dev->ops->reg_read(dev, dev->csr->base + offset, val); 23 } 24 25 int max10_sys_write(struct intel_max10_device *dev, 26 unsigned int offset, unsigned int val) 27 { 28 if (!dev || !dev->ops->reg_write) 29 return -ENODEV; 30 31 return dev->ops->reg_write(dev, dev->csr->base + offset, val); 32 } 33 34 int max10_reg_read(struct intel_max10_device *dev, 35 unsigned int offset, unsigned int *val) 36 { 37 if (!dev || !dev->ops->reg_read) 38 return -ENODEV; 39 40 return dev->ops->reg_read(dev, offset, val); 41 } 42 43 int max10_reg_write(struct intel_max10_device *dev, 44 unsigned int offset, unsigned int val) 45 { 46 if (!dev || !dev->ops->reg_write) 47 return -ENODEV; 48 49 return dev->ops->reg_write(dev, offset, val); 50 } 51 52 int max10_sys_update_bits(struct intel_max10_device *dev, unsigned int offset, 53 unsigned int msk, unsigned int val) 54 { 55 int ret = 0; 56 unsigned int temp = 0; 57 58 ret = max10_sys_read(dev, offset, &temp); 59 if (ret < 0) 60 return ret; 61 62 temp &= ~msk; 63 temp |= val & msk; 64 65 return max10_sys_write(dev, offset, temp); 66 } 67 68 static int n3000_bulk_raw_write(struct intel_max10_device *dev, uint32_t addr, 69 void *buf, uint32_t len) 70 { 71 uint32_t v = 0; 72 uint32_t i = 0; 73 char *p = buf; 74 int ret = 0; 75 76 len = IFPGA_ALIGN(len, 4); 77 78 for (i = 0; i < len; i += 4) { 79 v = *(uint32_t *)(p + i); 80 ret = max10_reg_write(dev, addr + i, v); 81 if (ret < 0) { 82 dev_err(dev, 83 "Failed to write to staging area 0x%08x [e:%d]\n", 84 addr + i, ret); 85 return ret; 86 } 87 } 88 89 return 0; 90 } 91 92 static int n3000_bulk_raw_read(struct intel_max10_device *dev, 93 uint32_t addr, void *buf, uint32_t len) 94 { 95 u32 v, i; 96 char *p = buf; 97 int ret; 98 99 len = IFPGA_ALIGN(len, 4); 100 101 for (i = 0; i < len; i += 4) { 102 ret = max10_reg_read(dev, addr + i, &v); 103 if (ret < 0) { 104 dev_err(dev, 105 "Failed to write to staging area 0x%08x [e:%d]\n", 106 addr + i, ret); 107 return ret; 108 } 109 *(u32 *)(p + i) = v; 110 } 111 112 return 0; 113 } 114 115 static int n3000_flash_read(struct intel_max10_device *dev, 116 u32 addr, void *buf, u32 size) 117 { 118 if (!dev->raw_blk_ops.read_blk) 119 return -ENODEV; 120 121 return dev->raw_blk_ops.read_blk(dev, addr, buf, size); 122 } 123 124 static int n3000_flash_write(struct intel_max10_device *dev, 125 u32 addr, void *buf, u32 size) 126 { 127 if (!dev->raw_blk_ops.write_blk) 128 return -ENODEV; 129 130 return dev->raw_blk_ops.write_blk(dev, addr, buf, size); 131 } 132 133 static u32 134 pmci_get_write_space(struct intel_max10_device *dev, u32 size) 135 { 136 u32 count, val; 137 int ret; 138 139 ret = opae_readl_poll_timeout(dev->mmio + PMCI_FLASH_CTRL, val, 140 GET_FIELD(PMCI_FLASH_FIFO_SPACE, val) == 141 PMCI_FIFO_MAX_WORDS, 142 PMCI_FLASH_INT_US, PMCI_FLASH_TIMEOUT_US); 143 if (ret == -ETIMEDOUT) 144 return 0; 145 146 count = GET_FIELD(PMCI_FLASH_FIFO_SPACE, val) * 4; 147 148 return (size > count) ? count : size; 149 } 150 151 static void pmci_write_fifo(void __iomem *base, char *buf, size_t count) 152 { 153 size_t i; 154 u32 val; 155 156 for (i = 0; i < count/4 ; i++) { 157 val = *(u32 *)(buf + i * 4); 158 writel(val, base); 159 } 160 } 161 162 static void pmci_read_fifo(void __iomem *base, char *buf, size_t count) 163 { 164 size_t i; 165 u32 val; 166 167 for (i = 0; i < count/4; i++) { 168 val = readl(base); 169 *(u32 *)(buf + i * 4) = val; 170 } 171 } 172 173 static int 174 __pmci_flash_bulk_write(struct intel_max10_device *dev, u32 addr, 175 void *buf, u32 size) 176 { 177 UNUSED(addr); 178 u32 blk_size, n_offset = 0; 179 180 while (size) { 181 blk_size = pmci_get_write_space(dev, size); 182 if (blk_size == 0) { 183 dev_err(pmci->dev, "get FIFO available size fail\n"); 184 return -EIO; 185 } 186 size -= blk_size; 187 pmci_write_fifo(dev->mmio + PMCI_FLASH_FIFO, (char *)buf + n_offset, 188 blk_size); 189 n_offset += blk_size; 190 } 191 192 return 0; 193 } 194 195 static int 196 pmci_flash_bulk_write(struct intel_max10_device *dev, u32 addr, 197 void *buf, u32 size) 198 { 199 int ret; 200 201 pthread_mutex_lock(dev->bmc_ops.mutex); 202 203 ret = __pmci_flash_bulk_write(dev, addr, buf, size); 204 205 pthread_mutex_unlock(dev->bmc_ops.mutex); 206 return ret; 207 } 208 209 static int 210 pmci_set_flash_host_mux(struct intel_max10_device *dev, bool request) 211 { 212 u32 ctrl; 213 int ret; 214 215 ret = max10_sys_update_bits(dev, 216 m10bmc_base(dev) + M10BMC_PMCI_FLASH_CTRL, 217 FLASH_HOST_REQUEST, 218 SET_FIELD(FLASH_HOST_REQUEST, request)); 219 if (ret) 220 return ret; 221 222 return opae_max10_read_poll_timeout(dev, m10bmc_base(dev) + M10BMC_PMCI_FLASH_CTRL, 223 ctrl, request ? (get_flash_mux(ctrl) == FLASH_MUX_HOST) : 224 (get_flash_mux(ctrl) != FLASH_MUX_HOST), 225 PMCI_FLASH_INT_US, PMCI_FLASH_TIMEOUT_US); 226 } 227 228 static int 229 pmci_get_mux(struct intel_max10_device *dev) 230 { 231 pthread_mutex_lock(dev->bmc_ops.mutex); 232 return pmci_set_flash_host_mux(dev, true); 233 } 234 235 static int 236 pmci_put_mux(struct intel_max10_device *dev) 237 { 238 int ret; 239 240 ret = pmci_set_flash_host_mux(dev, false); 241 pthread_mutex_unlock(dev->bmc_ops.mutex); 242 return ret; 243 } 244 245 static int 246 __pmci_flash_bulk_read(struct intel_max10_device *dev, u32 addr, 247 void *buf, u32 size) 248 { 249 u32 blk_size, offset = 0, val; 250 int ret; 251 252 while (size) { 253 blk_size = min_t(u32, size, PMCI_READ_BLOCK_SIZE); 254 255 opae_writel(addr + offset, dev->mmio + PMCI_FLASH_ADDR); 256 257 opae_writel(SET_FIELD(PMCI_FLASH_READ_COUNT, blk_size / 4) 258 | PMCI_FLASH_RD_MODE, 259 dev->mmio + PMCI_FLASH_CTRL); 260 261 ret = opae_readl_poll_timeout((dev->mmio + PMCI_FLASH_CTRL), 262 val, !(val & PMCI_FLASH_BUSY), 263 PMCI_FLASH_INT_US, 264 PMCI_FLASH_TIMEOUT_US); 265 if (ret) { 266 dev_err(dev, "%s timed out on reading flash 0x%xn", 267 __func__, val); 268 return ret; 269 } 270 271 pmci_read_fifo(dev->mmio + PMCI_FLASH_FIFO, (char *)buf + offset, 272 blk_size); 273 274 size -= blk_size; 275 offset += blk_size; 276 277 opae_writel(0, dev->mmio + PMCI_FLASH_CTRL); 278 } 279 280 return 0; 281 } 282 283 static int 284 pmci_flash_bulk_read(struct intel_max10_device *dev, u32 addr, 285 void *buf, u32 size) 286 { 287 int ret; 288 289 ret = pmci_get_mux(dev); 290 if (ret) 291 goto fail; 292 293 ret = __pmci_flash_bulk_read(dev, addr, buf, size); 294 if (ret) 295 goto fail; 296 297 return pmci_put_mux(dev); 298 299 fail: 300 pmci_put_mux(dev); 301 return ret; 302 } 303 304 static int pmci_check_flash_address(u32 start, u32 end) 305 { 306 if (start < PMCI_FLASH_START || end > PMCI_FLASH_END) 307 return -EINVAL; 308 309 return 0; 310 } 311 312 int opae_read_flash(struct intel_max10_device *dev, u32 addr, 313 u32 size, void *buf) 314 { 315 int ret; 316 317 if (!dev->bmc_ops.flash_read) 318 return -ENODEV; 319 320 if (!buf) 321 return -EINVAL; 322 323 if (dev->bmc_ops.check_flash_range) { 324 ret = dev->bmc_ops.check_flash_range(addr, addr + size); 325 if (ret) 326 return ret; 327 } else { 328 u32 top_addr = dev->staging_area_base + dev->staging_area_size; 329 if ((addr < dev->staging_area_base) || 330 ((addr + size) >= top_addr)) 331 return -EINVAL; 332 } 333 334 ret = dev->bmc_ops.flash_read(dev, addr, buf, size); 335 if (ret) 336 return ret; 337 338 return 0; 339 } 340 341 static int max10_spi_read(struct intel_max10_device *dev, 342 unsigned int addr, unsigned int *val) 343 { 344 if (!dev) 345 return -ENODEV; 346 347 dev_debug(dev, "%s: bus:0x%x, addr:0x%x\n", __func__, dev->bus, addr); 348 349 return spi_transaction_read(dev->spi_tran_dev, 350 addr, 4, (unsigned char *)val); 351 } 352 353 static int max10_spi_write(struct intel_max10_device *dev, 354 unsigned int addr, unsigned int val) 355 { 356 unsigned int tmp = val; 357 358 if (!dev) 359 return -ENODEV; 360 361 dev_debug(dev, "%s: bus:0x%x, reg:0x%x, val:0x%x\n", __func__, 362 dev->bus, addr, val); 363 364 return spi_transaction_write(dev->spi_tran_dev, 365 addr, 4, (unsigned char *)&tmp); 366 } 367 368 static int indirect_bus_clr_cmd(struct intel_max10_device *dev) 369 { 370 unsigned int cmd; 371 int ret; 372 373 opae_writel(0, dev->mmio + INDIRECT_CMD_OFF); 374 375 ret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd, 376 (!cmd), INDIRECT_INT_US, INDIRECT_TIMEOUT_US); 377 378 if (ret) 379 dev_err(dev, "%s timed out on clearing cmd 0x%x\n", 380 __func__, cmd); 381 382 return ret; 383 } 384 385 static int max10_indirect_reg_read(struct intel_max10_device *dev, 386 unsigned int addr, unsigned int *val) 387 { 388 unsigned int cmd; 389 int ret; 390 391 if (!dev) 392 return -ENODEV; 393 394 pthread_mutex_lock(dev->bmc_ops.mutex); 395 396 cmd = opae_readl(dev->mmio + INDIRECT_CMD_OFF); 397 if (cmd) 398 dev_warn(dev, "%s non-zero cmd 0x%x\n", __func__, cmd); 399 400 opae_writel(addr, dev->mmio + INDIRECT_ADDR_OFF); 401 402 opae_writel(INDIRECT_CMD_RD, dev->mmio + INDIRECT_CMD_OFF); 403 404 ret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd, 405 (cmd & INDIRECT_CMD_ACK), INDIRECT_INT_US, 406 INDIRECT_TIMEOUT_US); 407 408 *val = opae_readl(dev->mmio + INDIRECT_RD_OFF); 409 410 if (ret) 411 dev_err(dev, "%s timed out on reg 0x%x cmd 0x%x\n", 412 __func__, addr, cmd); 413 414 if (indirect_bus_clr_cmd(dev)) 415 ret = -ETIME; 416 417 pthread_mutex_unlock(dev->bmc_ops.mutex); 418 419 return ret; 420 } 421 422 static int max10_indirect_reg_write(struct intel_max10_device *dev, 423 unsigned int addr, unsigned int val) 424 { 425 unsigned int cmd; 426 int ret; 427 428 if (!dev) 429 return -ENODEV; 430 431 pthread_mutex_lock(dev->bmc_ops.mutex); 432 433 cmd = readl(dev->mmio + INDIRECT_CMD_OFF); 434 435 if (cmd) 436 dev_warn(dev, "%s non-zero cmd 0x%x\n", __func__, cmd); 437 438 opae_writel(val, dev->mmio + INDIRECT_WR_OFF); 439 440 opae_writel(addr, dev->mmio + INDIRECT_ADDR_OFF); 441 442 writel(INDIRECT_CMD_WR, dev->mmio + INDIRECT_CMD_OFF); 443 444 ret = opae_readl_poll_timeout((dev->mmio + INDIRECT_CMD_OFF), cmd, 445 (cmd & INDIRECT_CMD_ACK), INDIRECT_INT_US, 446 INDIRECT_TIMEOUT_US); 447 448 if (ret) 449 dev_err(dev, "%s timed out on reg 0x%x cmd 0x%x\n", 450 __func__, addr, cmd); 451 452 if (indirect_bus_clr_cmd(dev)) 453 ret = -ETIME; 454 455 pthread_mutex_unlock(dev->bmc_ops.mutex); 456 457 return ret; 458 } 459 460 const struct m10bmc_regmap m10bmc_pmci_regmap = { 461 .reg_write = max10_indirect_reg_write, 462 .reg_read = max10_indirect_reg_read, 463 }; 464 465 const struct m10bmc_regmap m10bmc_n3000_regmap = { 466 .reg_write = max10_spi_write, 467 .reg_read = max10_spi_read, 468 }; 469 470 static struct max10_compatible_id max10_id_table[] = { 471 {.compatible = MAX10_PAC,}, 472 {.compatible = MAX10_PAC_N3000,}, 473 {.compatible = MAX10_PAC_END,} 474 }; 475 476 static struct max10_compatible_id *max10_match_compatible(const char *fdt_root) 477 { 478 struct max10_compatible_id *id = max10_id_table; 479 480 for (; strcmp(id->compatible, MAX10_PAC_END); id++) { 481 if (fdt_node_check_compatible(fdt_root, 0, id->compatible)) 482 continue; 483 484 return id; 485 } 486 487 return NULL; 488 } 489 490 static inline bool 491 is_max10_pac_n3000(struct intel_max10_device *max10) 492 { 493 return max10->id && !strcmp(max10->id->compatible, 494 MAX10_PAC_N3000); 495 } 496 497 static void max10_check_capability(struct intel_max10_device *max10) 498 { 499 if (!max10->fdt_root) 500 return; 501 502 if (is_max10_pac_n3000(max10)) { 503 max10->flags |= MAX10_FLAGS_NO_I2C2 | 504 MAX10_FLAGS_NO_BMCIMG_FLASH; 505 dev_info(max10, "found %s card\n", max10->id->compatible); 506 } else 507 max10->flags |= MAX10_FLAGS_MAC_CACHE; 508 } 509 510 static int altera_nor_flash_read(struct intel_max10_device *dev, 511 u32 offset, void *buffer, u32 len) 512 { 513 int word_len; 514 int i; 515 unsigned int *buf = (unsigned int *)buffer; 516 unsigned int value; 517 int ret; 518 519 if (!dev || !buffer || len <= 0) 520 return -ENODEV; 521 522 word_len = len/4; 523 524 for (i = 0; i < word_len; i++) { 525 ret = max10_reg_read(dev, offset + i*4, 526 &value); 527 if (ret) 528 return -EBUSY; 529 530 *buf++ = value; 531 } 532 533 return 0; 534 } 535 536 static int enable_nor_flash(struct intel_max10_device *dev, bool on) 537 { 538 unsigned int val = 0; 539 int ret; 540 541 ret = max10_sys_read(dev, RSU_REG, &val); 542 if (ret) { 543 dev_err(NULL "enabling flash error\n"); 544 return ret; 545 } 546 547 if (on) 548 val |= RSU_ENABLE; 549 else 550 val &= ~RSU_ENABLE; 551 552 return max10_sys_write(dev, RSU_REG, val); 553 } 554 555 static int init_max10_device_table(struct intel_max10_device *max10) 556 { 557 struct altera_spi_device *spi = NULL; 558 struct max10_compatible_id *id; 559 struct fdt_header hdr; 560 char *fdt_root = NULL; 561 u32 dtb_magic = 0; 562 u32 dt_size, dt_addr, val; 563 int ret = 0; 564 565 spi = (struct altera_spi_device *)max10->spi_master; 566 if (!spi) { 567 dev_err(max10, "spi master is not set\n"); 568 return -EINVAL; 569 } 570 if (spi->dtb) 571 dtb_magic = *(u32 *)spi->dtb; 572 573 if (dtb_magic != 0xEDFE0DD0) { 574 dev_info(max10, "read DTB from NOR flash\n"); 575 ret = max10_sys_read(max10, DT_AVAIL_REG, &val); 576 if (ret) { 577 dev_err(max10 "cannot read DT_AVAIL_REG\n"); 578 return ret; 579 } 580 581 if (!(val & DT_AVAIL)) { 582 dev_err(max10 "DT not available\n"); 583 return -EINVAL; 584 } 585 586 ret = max10_sys_read(max10, DT_BASE_ADDR_REG, &dt_addr); 587 if (ret) { 588 dev_info(max10 "cannot get base addr of device table\n"); 589 return ret; 590 } 591 592 ret = enable_nor_flash(max10, true); 593 if (ret) { 594 dev_err(max10 "fail to enable flash\n"); 595 return ret; 596 } 597 598 ret = altera_nor_flash_read(max10, dt_addr, &hdr, sizeof(hdr)); 599 if (ret) { 600 dev_err(max10 "read fdt header fail\n"); 601 goto disable_nor_flash; 602 } 603 604 ret = fdt_check_header(&hdr); 605 if (ret) { 606 dev_err(max10 "check fdt header fail\n"); 607 goto disable_nor_flash; 608 } 609 610 dt_size = fdt_totalsize(&hdr); 611 if (dt_size > DFT_MAX_SIZE) { 612 dev_err(max10 "invalid device table size\n"); 613 ret = -EINVAL; 614 goto disable_nor_flash; 615 } 616 617 fdt_root = opae_malloc(dt_size); 618 if (!fdt_root) { 619 ret = -ENOMEM; 620 goto disable_nor_flash; 621 } 622 623 ret = altera_nor_flash_read(max10, dt_addr, fdt_root, dt_size); 624 if (ret) { 625 opae_free(fdt_root); 626 fdt_root = NULL; 627 dev_err(max10 "cannot read device table\n"); 628 goto disable_nor_flash; 629 } 630 631 if (spi->dtb) { 632 if (*spi->dtb_sz_ptr < dt_size) { 633 dev_warn(max10, 634 "share memory for dtb is smaller than required %u\n", 635 dt_size); 636 } else { 637 *spi->dtb_sz_ptr = dt_size; 638 } 639 /* store dtb data into share memory */ 640 memcpy(spi->dtb, fdt_root, *spi->dtb_sz_ptr); 641 } 642 643 disable_nor_flash: 644 enable_nor_flash(max10, false); 645 } else { 646 if (*spi->dtb_sz_ptr > 0) { 647 dev_info(max10, "read DTB from shared memory\n"); 648 fdt_root = opae_malloc(*spi->dtb_sz_ptr); 649 if (fdt_root) 650 memcpy(fdt_root, spi->dtb, *spi->dtb_sz_ptr); 651 else 652 ret = -ENOMEM; 653 } 654 } 655 656 if (fdt_root) { 657 id = max10_match_compatible(fdt_root); 658 if (!id) { 659 dev_err(max10 "max10 compatible not found\n"); 660 ret = -ENODEV; 661 } else { 662 max10->flags |= MAX10_FLAGS_DEVICE_TABLE; 663 max10->id = id; 664 max10->fdt_root = fdt_root; 665 } 666 } 667 668 return ret; 669 } 670 671 static u64 fdt_get_number(const fdt32_t *cell, int size) 672 { 673 u64 r = 0; 674 675 while (size--) 676 r = (r << 32) | fdt32_to_cpu(*cell++); 677 678 return r; 679 } 680 681 static int fdt_get_reg(const void *fdt, int node, unsigned int idx, 682 u64 *start, u64 *size) 683 { 684 const fdt32_t *prop, *end; 685 int na = 0, ns = 0, len = 0, parent; 686 687 parent = fdt_parent_offset(fdt, node); 688 if (parent < 0) 689 return parent; 690 691 prop = fdt_getprop(fdt, parent, "#address-cells", NULL); 692 na = prop ? fdt32_to_cpu(*prop) : 2; 693 694 prop = fdt_getprop(fdt, parent, "#size-cells", NULL); 695 ns = prop ? fdt32_to_cpu(*prop) : 2; 696 697 prop = fdt_getprop(fdt, node, "reg", &len); 698 if (!prop) 699 return -FDT_ERR_NOTFOUND; 700 701 end = prop + len/sizeof(*prop); 702 prop = prop + (na + ns) * idx; 703 704 if (prop + na + ns > end) 705 return -FDT_ERR_NOTFOUND; 706 707 *start = fdt_get_number(prop, na); 708 *size = fdt_get_number(prop + na, ns); 709 710 return 0; 711 } 712 713 static int __fdt_stringlist_search(const void *fdt, int offset, 714 const char *prop, const char *string) 715 { 716 int length, len, index = 0; 717 const char *list, *end; 718 719 list = fdt_getprop(fdt, offset, prop, &length); 720 if (!list) 721 return length; 722 723 len = strlen(string) + 1; 724 end = list + length; 725 726 while (list < end) { 727 length = strnlen(list, end - list) + 1; 728 729 if (list + length > end) 730 return -FDT_ERR_BADVALUE; 731 732 if (length == len && memcmp(list, string, length) == 0) 733 return index; 734 735 list += length; 736 index++; 737 } 738 739 return -FDT_ERR_NOTFOUND; 740 } 741 742 static int fdt_get_named_reg(const void *fdt, int node, const char *name, 743 u64 *start, u64 *size) 744 { 745 int idx; 746 747 idx = __fdt_stringlist_search(fdt, node, "reg-names", name); 748 if (idx < 0) 749 return idx; 750 751 return fdt_get_reg(fdt, node, idx, start, size); 752 } 753 754 static void max10_sensor_uinit(struct intel_max10_device *dev) 755 { 756 struct opae_sensor_info *info, *next; 757 758 TAILQ_FOREACH_SAFE(info, &dev->opae_sensor_list, node, next) { 759 TAILQ_REMOVE(&dev->opae_sensor_list, info, node); 760 opae_free(info); 761 } 762 } 763 764 static bool sensor_reg_valid(struct sensor_reg *reg) 765 { 766 return !!reg->size; 767 } 768 769 static int max10_add_sensor(struct intel_max10_device *dev, 770 struct raw_sensor_info *info, struct opae_sensor_info *sensor) 771 { 772 int i; 773 int ret = 0; 774 unsigned int val; 775 776 if (!info || !sensor) 777 return -ENODEV; 778 779 sensor->id = info->id; 780 sensor->name = info->name; 781 sensor->type = info->type; 782 sensor->multiplier = info->multiplier; 783 784 for (i = SENSOR_REG_VALUE; i < SENSOR_REG_MAX; i++) { 785 if (!sensor_reg_valid(&info->regs[i])) 786 continue; 787 788 ret = max10_sys_read(dev, info->regs[i].regoff, &val); 789 if (ret) 790 break; 791 792 if (val == 0xdeadbeef) { 793 dev_debug(dev, "%s: sensor:%s invalid 0x%x at:%d\n", 794 __func__, sensor->name, val, i); 795 continue; 796 } 797 798 val *= info->multiplier; 799 800 switch (i) { 801 case SENSOR_REG_VALUE: 802 sensor->value_reg = info->regs[i].regoff; 803 sensor->flags |= OPAE_SENSOR_VALID; 804 break; 805 case SENSOR_REG_HIGH_WARN: 806 sensor->high_warn = val; 807 sensor->flags |= OPAE_SENSOR_HIGH_WARN_VALID; 808 break; 809 case SENSOR_REG_HIGH_FATAL: 810 sensor->high_fatal = val; 811 sensor->flags |= OPAE_SENSOR_HIGH_FATAL_VALID; 812 break; 813 case SENSOR_REG_LOW_WARN: 814 sensor->low_warn = val; 815 sensor->flags |= OPAE_SENSOR_LOW_WARN_VALID; 816 break; 817 case SENSOR_REG_LOW_FATAL: 818 sensor->low_fatal = val; 819 sensor->flags |= OPAE_SENSOR_LOW_FATAL_VALID; 820 break; 821 case SENSOR_REG_HYSTERESIS: 822 sensor->hysteresis = val; 823 sensor->flags |= OPAE_SENSOR_HYSTERESIS_VALID; 824 break; 825 } 826 } 827 828 return ret; 829 } 830 831 static int 832 max10_sensor_init(struct intel_max10_device *dev, int parent) 833 { 834 int i, ret = 0, offset = 0; 835 const fdt32_t *num; 836 const char *ptr; 837 u64 start, size; 838 struct raw_sensor_info *raw; 839 struct opae_sensor_info *sensor; 840 char *fdt_root = dev->fdt_root; 841 842 if (!fdt_root) { 843 dev_debug(dev, "skip sensor init as not find Device Tree\n"); 844 return 0; 845 } 846 847 fdt_for_each_subnode(offset, fdt_root, parent) { 848 ptr = fdt_get_name(fdt_root, offset, NULL); 849 if (!ptr) { 850 dev_err(dev, "failed to fdt get name\n"); 851 continue; 852 } 853 854 if (!strstr(ptr, "sensor")) { 855 dev_debug(dev, "%s is not a sensor node\n", ptr); 856 continue; 857 } 858 859 dev_debug(dev, "found sensor node %s\n", ptr); 860 861 raw = (struct raw_sensor_info *)opae_zmalloc(sizeof(*raw)); 862 if (!raw) { 863 ret = -ENOMEM; 864 goto free_sensor; 865 } 866 867 raw->name = fdt_getprop(fdt_root, offset, "sensor_name", NULL); 868 if (!raw->name) { 869 ret = -EINVAL; 870 goto free_sensor; 871 } 872 873 raw->type = fdt_getprop(fdt_root, offset, "type", NULL); 874 if (!raw->type) { 875 ret = -EINVAL; 876 goto free_sensor; 877 } 878 879 for (i = SENSOR_REG_VALUE; i < SENSOR_REG_MAX; i++) { 880 ret = fdt_get_named_reg(fdt_root, offset, 881 sensor_reg_name[i], &start, 882 &size); 883 if (ret) { 884 dev_debug(dev, "no found %d: sensor node %s, %s\n", 885 ret, ptr, sensor_reg_name[i]); 886 if (i == SENSOR_REG_VALUE) { 887 ret = -EINVAL; 888 goto free_sensor; 889 } 890 891 continue; 892 } 893 894 /* This is a hack to compatible with non-secure 895 * solution. If sensors are included in root node, 896 * then it's non-secure dtb, which use absolute addr 897 * of non-secure solution. 898 */ 899 if (parent) 900 raw->regs[i].regoff = start; 901 else 902 raw->regs[i].regoff = start - 903 MAX10_BASE_ADDR; 904 raw->regs[i].size = size; 905 } 906 907 num = fdt_getprop(fdt_root, offset, "id", NULL); 908 if (!num) { 909 ret = -EINVAL; 910 goto free_sensor; 911 } 912 913 raw->id = fdt32_to_cpu(*num); 914 num = fdt_getprop(fdt_root, offset, "multiplier", NULL); 915 raw->multiplier = num ? fdt32_to_cpu(*num) : 1; 916 917 dev_debug(dev, "found sensor from DTB: %s: %s: %u: %u\n", 918 raw->name, raw->type, 919 raw->id, raw->multiplier); 920 921 for (i = SENSOR_REG_VALUE; i < SENSOR_REG_MAX; i++) 922 dev_debug(dev, "sensor reg[%d]: %x: %zu\n", 923 i, raw->regs[i].regoff, 924 raw->regs[i].size); 925 926 sensor = opae_zmalloc(sizeof(*sensor)); 927 if (!sensor) { 928 ret = -EINVAL; 929 goto free_sensor; 930 } 931 932 if (max10_add_sensor(dev, raw, sensor)) { 933 ret = -EINVAL; 934 opae_free(sensor); 935 goto free_sensor; 936 } 937 938 if (sensor->flags & OPAE_SENSOR_VALID) { 939 TAILQ_INSERT_TAIL(&dev->opae_sensor_list, sensor, node); 940 dev_info(dev, "found valid sensor: %s\n", sensor->name); 941 } else 942 opae_free(sensor); 943 944 opae_free(raw); 945 } 946 947 return 0; 948 949 free_sensor: 950 if (raw) 951 opae_free(raw); 952 max10_sensor_uinit(dev); 953 return ret; 954 } 955 956 static int check_max10_version(struct intel_max10_device *dev) 957 { 958 unsigned int v; 959 960 if (!max10_reg_read(dev, MAX10_SEC_BASE_ADDR + MAX10_BUILD_VER, 961 &v)) { 962 if (v != 0xffffffff) { 963 dev_info(dev, "secure MAX10 detected\n"); 964 dev->flags |= MAX10_FLAGS_SECURE; 965 } else { 966 dev_info(dev, "non-secure MAX10 detected\n"); 967 } 968 return 0; 969 } 970 971 return -ENODEV; 972 } 973 974 static int max10_staging_area_init(struct intel_max10_device *dev) 975 { 976 char *fdt_root = dev->fdt_root; 977 int ret, offset = 0; 978 u64 start, size; 979 980 if (!fdt_root) { 981 dev_debug(dev, 982 "skip staging area init as not find Device Tree\n"); 983 return -ENODEV; 984 } 985 986 dev->staging_area_size = 0; 987 988 fdt_for_each_subnode(offset, fdt_root, 0) { 989 if (fdt_node_check_compatible(fdt_root, offset, 990 "ifpga-sec-mgr,staging-area")) 991 continue; 992 993 ret = fdt_get_reg(fdt_root, offset, 0, &start, &size); 994 if (ret) 995 return ret; 996 997 if ((start & 0x3) || (start > MAX_STAGING_AREA_BASE) || 998 (size > MAX_STAGING_AREA_SIZE)) 999 return -EINVAL; 1000 1001 dev->staging_area_base = start; 1002 dev->staging_area_size = size; 1003 1004 return ret; 1005 } 1006 1007 return -ENODEV; 1008 } 1009 1010 static int 1011 max10_secure_hw_init(struct intel_max10_device *dev) 1012 { 1013 int offset, sysmgr_offset = 0; 1014 char *fdt_root; 1015 1016 fdt_root = dev->fdt_root; 1017 if (!fdt_root) { 1018 dev_debug(dev, "skip init as not find Device Tree\n"); 1019 return 0; 1020 } 1021 1022 fdt_for_each_subnode(offset, fdt_root, 0) { 1023 if (!fdt_node_check_compatible(fdt_root, offset, 1024 "intel-max10,system-manager")) { 1025 sysmgr_offset = offset; 1026 break; 1027 } 1028 } 1029 1030 max10_check_capability(dev); 1031 1032 max10_sensor_init(dev, sysmgr_offset); 1033 1034 max10_staging_area_init(dev); 1035 1036 return 0; 1037 } 1038 1039 static int 1040 max10_non_secure_hw_init(struct intel_max10_device *dev) 1041 { 1042 max10_check_capability(dev); 1043 1044 max10_sensor_init(dev, 0); 1045 1046 return 0; 1047 } 1048 1049 int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned int *val) 1050 { 1051 int ret; 1052 unsigned int value; 1053 1054 /* read FPGA loading information */ 1055 ret = max10_sys_read(dev, dev->csr->fpga_page_info, &value); 1056 if (ret) { 1057 dev_err(dev, "fail to get FPGA loading info\n"); 1058 return ret; 1059 } 1060 1061 if (dev->type == M10_N3000) 1062 *val = value & 0x7; 1063 else if (dev->type == M10_N6000) { 1064 if (!GET_FIELD(PMCI_FPGA_CONFIGURED, value)) 1065 return -EINVAL; 1066 *val = GET_FIELD(PMCI_FPGA_BOOT_PAGE, value); 1067 } 1068 1069 return 0; 1070 } 1071 1072 int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int *val) 1073 { 1074 int ret; 1075 1076 ret = max10_sys_read(dev, dev->csr->build_version, val); 1077 if (ret) 1078 return ret; 1079 1080 return 0; 1081 } 1082 1083 int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned int *val) 1084 { 1085 int ret; 1086 1087 ret = max10_sys_read(dev, dev->csr->fw_version, val); 1088 if (ret) 1089 return ret; 1090 1091 return 0; 1092 } 1093 1094 static const struct m10bmc_csr m10bmc_spi_csr = { 1095 .base = MAX10_SEC_BASE_ADDR, 1096 .build_version = MAX10_BUILD_VER, 1097 .fw_version = NIOS2_FW_VERSION, 1098 .fpga_page_info = FPGA_PAGE_INFO, 1099 .doorbell = MAX10_DOORBELL, 1100 .auth_result = MAX10_AUTH_RESULT, 1101 }; 1102 1103 static const struct m10bmc_csr m10bmc_pmci_csr = { 1104 .base = M10BMC_PMCI_SYS_BASE, 1105 .build_version = M10BMC_PMCI_BUILD_VER, 1106 .fw_version = NIOS2_PMCI_FW_VERSION, 1107 .fpga_page_info = M10BMC_PMCI_FPGA_CONF_STS, 1108 .doorbell = M10BMC_PMCI_DOORBELL, 1109 .auth_result = M10BMC_PMCI_AUTH_RESULT, 1110 }; 1111 1112 static const struct max10_sensor_raw_data n6000bmc_temp_tbl[] = { 1113 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, 1114 "FPGA E-TILE Temperature #1" }, 1115 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, 1116 "FPGA E-TILE Temperature #2" }, 1117 { 0x45c, 0x460, 0x464, 0x0, 0x0, 500, 1118 "FPGA E-TILE Temperature #3" }, 1119 { 0x468, 0x46c, 0x470, 0x0, 0x0, 500, 1120 "FPGA E-TILE Temperature #4" }, 1121 { 0x474, 0x478, 0x47c, 0x0, 0x0, 500, 1122 "FPGA P-TILE Temperature" }, 1123 { 0x484, 0x488, 0x48c, 0x0, 0x0, 500, 1124 "FPGA FABRIC Digital Temperature#1" }, 1125 { 0x490, 0x494, 0x498, 0x0, 0x0, 500, 1126 "FPGA FABRIC Digital Temperature#2" }, 1127 { 0x49c, 0x4a0, 0x4a4, 0x0, 0x0, 500, 1128 "FPGA FABRIC Digital Temperature#3" }, 1129 { 0x4a8, 0x4ac, 0x4b0, 0x0, 0x0, 500, 1130 "FPGA FABRIC Digital Temperature#4" }, 1131 { 0x4b4, 0x4b8, 0x4bc, 0x0, 0x0, 500, 1132 "FPGA FABRIC Digital Temperature#5" }, 1133 { 0x4c0, 0x4c4, 0x4c8, 0x0, 0x0, 500, 1134 "FPGA FABRIC Remote Digital Temperature#1" }, 1135 { 0x4cc, 0x4d0, 0x4d4, 0x0, 0x0, 500, 1136 "FPGA FABRIC Remote Digital Temperature#2" }, 1137 { 0x4d8, 0x4dc, 0x4e0, 0x0, 0x0, 500, 1138 "FPGA FABRIC Remote Digital Temperature#3" }, 1139 { 0x4e4, 0x4e8, 0x4ec, 0x0, 0x0, 500, 1140 "FPGA FABRIC Remote Digital Temperature#4" }, 1141 { 0x4f0, 0x4f4, 0x4f8, 0x0, 0x0, 500, 1142 "Board Top Near FPGA Temperature" }, 1143 { 0x4fc, 0x500, 0x504, 0x52c, 0x0, 500, 1144 "Board Bottom Near CVL Temperature" }, 1145 { 0x508, 0x50c, 0x510, 0x52c, 0x0, 500, 1146 "Board Top East Near VRs Temperature" }, 1147 { 0x514, 0x518, 0x51c, 0x52c, 0x0, 500, 1148 "Columbiaville Die Temperature" }, 1149 { 0x520, 0x524, 0x528, 0x52c, 0x0, 500, 1150 "Board Rear Side Temperature" }, 1151 { 0x530, 0x534, 0x538, 0x52c, 0x0, 500, 1152 "Board Front Side Temperature" }, 1153 { 0x53c, 0x540, 0x544, 0x0, 0x0, 500, 1154 "QSFP1 Temperature" }, 1155 { 0x548, 0x54c, 0x550, 0x0, 0x0, 500, 1156 "QSFP2 Temperature" }, 1157 { 0x554, 0x0, 0x0, 0x0, 0x0, 500, 1158 "FPGA Core Voltage Phase 0 VR Temperature" }, 1159 { 0x560, 0x0, 0x0, 0x0, 0x0, 500, 1160 "FPGA Core Voltage Phase 1 VR Temperature" }, 1161 { 0x56c, 0x0, 0x0, 0x0, 0x0, 500, 1162 "FPGA Core Voltage Phase 2 VR Temperature" }, 1163 { 0x578, 0x0, 0x0, 0x0, 0x0, 500, 1164 "FPGA Core Voltage VR Controller Temperature" }, 1165 { 0x584, 0x0, 0x0, 0x0, 0x0, 500, 1166 "FPGA VCCH VR Temperature" }, 1167 { 0x590, 0x0, 0x0, 0x0, 0x0, 500, 1168 "FPGA VCC_1V2 VR Temperature" }, 1169 { 0x59c, 0x0, 0x0, 0x0, 0x0, 500, 1170 "FPGA VCCH, VCC_1V2 VR Controller Temperature" }, 1171 { 0x5a8, 0x0, 0x0, 0x0, 0x0, 500, 1172 "3V3 VR Temperature" }, 1173 { 0x5b4, 0x5b8, 0x5bc, 0x0, 0x0, 500, 1174 "CVL Core Voltage VR Temperature" }, 1175 { 0x5c4, 0x5c8, 0x5cc, 0x5c0, 0x0, 500, 1176 "FPGA P-Tile Temperature [Remote]" }, 1177 { 0x5d0, 0x5d4, 0x5d8, 0x5c0, 0x0, 500, 1178 "FPGA E-Tile Temperature [Remote]" }, 1179 { 0x5dc, 0x5e0, 0x5e4, 0x5c0, 0x0, 500, 1180 "FPGA SDM Temperature [Remote]" }, 1181 { 0x5e8, 0x5ec, 0x5f0, 0x5c0, 0x0, 500, 1182 "FPGA Corner Temperature [Remote]" }, 1183 }; 1184 1185 static const struct max10_sensor_data n6000bmc_tmp_data = { 1186 .type = SENSOR_TMP_NAME, 1187 .number = ARRAY_SIZE(n6000bmc_temp_tbl), 1188 .table = n6000bmc_temp_tbl, 1189 }; 1190 1191 static const struct max10_sensor_raw_data n6000bmc_in_tbl[] = { 1192 { 0x5f4, 0x0, 0x0, 0x0, 0x0, 1, 1193 "Inlet 12V PCIe Rail Voltage" }, 1194 { 0x60c, 0x0, 0x0, 0x0, 0x0, 1, 1195 "Inlet 12V Aux Rail Voltage" }, 1196 { 0x624, 0x0, 0x0, 0x0, 0x0, 1, 1197 "Inlet 3V3 PCIe Rail Voltage" }, 1198 { 0x63c, 0x0, 0x0, 0x0, 0x0, 1, 1199 "FPGA Core Voltage Rail Voltage" }, 1200 { 0x644, 0x0, 0x0, 0x0, 0x0, 1, 1201 "FPGA VCCH Rail Voltage" }, 1202 { 0x64c, 0x0, 0x0, 0x0, 0x0, 1, 1203 "FPGA VCC_1V2 Rail Voltage" }, 1204 { 0x654, 0x0, 0x0, 0x0, 0x0, 1, 1205 "FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" }, 1206 { 0x664, 0x0, 0x0, 0x0, 0x0, 1, 1207 "FPGA VCCIO_1V2 Voltage" }, 1208 { 0x674, 0x0, 0x0, 0x0, 0x0, 1, 1209 "CVL Non Core Rails Inlet Voltage" }, 1210 { 0x684, 0x0, 0x0, 0x0, 0x0, 1, 1211 "MAX10 & Board CLK PWR 3V3 Inlet Voltage" }, 1212 { 0x694, 0x0, 0x0, 0x0, 0x0, 1, 1213 "CVL Core Voltage Rail Voltage" }, 1214 { 0x6ac, 0x0, 0x0, 0x0, 0x0, 1, 1215 "Board 3V3 VR Voltage" }, 1216 { 0x6b4, 0x0, 0x0, 0x0, 0x0, 1, 1217 "QSFP 3V3 Rail Voltage" }, 1218 { 0x6c4, 0x0, 0x0, 0x0, 0x0, 1, 1219 "QSFP (Primary) Supply Rail Voltage" }, 1220 { 0x6c8, 0x0, 0x0, 0x0, 0x0, 1, 1221 "QSFP (Secondary) Supply Rail Voltage" }, 1222 { 0x6cc, 0x0, 0x0, 0x0, 0x0, 1, 1223 "VCCCLK_GXER_2V5 Voltage" }, 1224 { 0x6d0, 0x0, 0x0, 0x0, 0x0, 1, 1225 "AVDDH_1V1_CVL Voltage" }, 1226 { 0x6d4, 0x0, 0x0, 0x0, 0x0, 1, 1227 "VDDH_1V8_CVL Voltage" }, 1228 { 0x6d8, 0x0, 0x0, 0x0, 0x0, 1, 1229 "VCCA_PLL Voltage" }, 1230 { 0x6e0, 0x0, 0x0, 0x0, 0x0, 1, 1231 "VCCRT_GXER_0V9 Voltage" }, 1232 { 0x6e8, 0x0, 0x0, 0x0, 0x0, 1, 1233 "VCCRT_GXEL_0V9 Voltage" }, 1234 { 0x6f0, 0x0, 0x0, 0x0, 0x0, 1, 1235 "VCCH_GXPL_1V8 Voltage" }, 1236 { 0x6f4, 0x0, 0x0, 0x0, 0x0, 1, 1237 "VCCPT_1V8 Voltage" }, 1238 { 0x6fc, 0x0, 0x0, 0x0, 0x0, 1, 1239 "VCC_3V3_M10 Voltage" }, 1240 { 0x700, 0x0, 0x0, 0x0, 0x0, 1, 1241 "VCC_1V8_M10 Voltage" }, 1242 { 0x704, 0x0, 0x0, 0x0, 0x0, 1, 1243 "VCC_1V2_EMIF1_2_3 Voltage" }, 1244 { 0x70c, 0x0, 0x0, 0x0, 0x0, 1, 1245 "VCC_1V2_EMIF4_5 Voltage" }, 1246 { 0x714, 0x0, 0x0, 0x0, 0x0, 1, 1247 "VCCA_1V8 Voltage" }, 1248 { 0x718, 0x0, 0x0, 0x0, 0x0, 1, 1249 "VCCH_GXER_1V1 Voltage" }, 1250 { 0x71c, 0x0, 0x0, 0x0, 0x0, 1, 1251 "AVDD_ETH_0V9_CVL Voltage" }, 1252 { 0x720, 0x0, 0x0, 0x0, 0x0, 1, 1253 "AVDD_PCIE_0V9_CVL Voltage" }, 1254 }; 1255 1256 static const struct max10_sensor_data n6000bmc_in_data = { 1257 .type = SENSOR_IN_NAME, 1258 .number = ARRAY_SIZE(n6000bmc_in_tbl), 1259 .table = n6000bmc_in_tbl, 1260 }; 1261 1262 static const struct max10_sensor_raw_data n6000bmc_curr_tbl[] = { 1263 { 0x600, 0x604, 0x608, 0x0, 0x0, 1, 1264 "Inlet 12V PCIe Rail Current" }, 1265 { 0x618, 0x61c, 0x620, 0x0, 0x0, 1, 1266 "Inlet 12V Aux Rail Current" }, 1267 { 0x630, 0x634, 0x638, 0x0, 0x0, 1, 1268 "Inlet 3V3 PCIe Rail Current" }, 1269 { 0x640, 0x0, 0x0, 0x0, 0x0, 1, 1270 "FPGA Core Voltage Rail Current" }, 1271 { 0x648, 0x0, 0x0, 0x0, 0x0, 1, 1272 "FPGA VCCH Rail Current" }, 1273 { 0x650, 0x0, 0x0, 0x0, 0x0, 1, 1274 "FPGA VCC_1V2 Rail Current" }, 1275 { 0x658, 0x65c, 0x660, 0x0, 0x0, 1, 1276 "FPGA VCCH_GXER_1V1, VCCA_1V8 Current" }, 1277 { 0x668, 0x66c, 0x670, 0x0, 0x0, 1, 1278 "FPGA VCCIO_1V2 Current" }, 1279 { 0x678, 0x67c, 0x680, 0x0, 0x0, 1, 1280 "CVL Non Core Rails Inlet Current" }, 1281 { 0x688, 0x68c, 0x680, 0x0, 0x0, 1, 1282 "MAX10 & Board CLK PWR 3V3 Inlet Current" }, 1283 { 0x690, 0x0, 0x0, 0x0, 0x0, 1, 1284 "CVL Core Voltage Rail Current" }, 1285 { 0x6b0, 0x0, 0x0, 0x0, 0x0, 1, 1286 "Board 3V3 VR Current" }, 1287 { 0x6b8, 0x6bc, 0x670, 0x0, 0x0, 1, 1288 "QSFP 3V3 Rail Current" }, 1289 }; 1290 1291 static const struct max10_sensor_data n6000bmc_curr_data = { 1292 .type = SENSOR_CURR_NAME, 1293 .number = ARRAY_SIZE(n6000bmc_curr_tbl), 1294 .table = n6000bmc_curr_tbl, 1295 }; 1296 1297 static const struct max10_sensor_raw_data n6000bmc_power_tbl[] = { 1298 { 0x724, 0x0, 0x0, 0x0, 0x0, 1000, "Board Power" }, 1299 }; 1300 1301 static const struct max10_sensor_data n6000bmc_power_data = { 1302 .type = SENSOR_POWER_NAME, 1303 .number = ARRAY_SIZE(n6000bmc_power_tbl), 1304 .table = n6000bmc_power_tbl, 1305 }; 1306 1307 static const struct max10_sensor_board_data n6000bmc_sensor_board_data = { 1308 .tables = { 1309 [sensor_temp] = &n6000bmc_tmp_data, 1310 [sensor_in] = &n6000bmc_in_data, 1311 [sensor_curr] = &n6000bmc_curr_data, 1312 [sensor_power] = &n6000bmc_power_data, 1313 }, 1314 }; 1315 1316 static int get_sensor_data(struct intel_max10_device *dev, 1317 struct opae_sensor_info *sensor, 1318 unsigned int *value, 1319 unsigned int reg, 1320 unsigned int flags) 1321 { 1322 int ret; 1323 unsigned int data; 1324 1325 if (!reg) 1326 return 0; 1327 1328 ret = max10_sys_read(dev, reg, &data); 1329 if (ret) 1330 return ret; 1331 1332 if (data == SENSOR_INVALID) { 1333 dev_debug(dev, "%s: sensor:%s invalid 0x%x at:%d\n", 1334 __func__, sensor->name, data, reg); 1335 return ret; 1336 } 1337 1338 *value = data * sensor->multiplier; 1339 sensor->flags |= flags; 1340 1341 return 0; 1342 } 1343 1344 static int max10_parse_sensor_data(struct intel_max10_device *dev, 1345 const struct max10_sensor_data *sdata) 1346 { 1347 struct opae_sensor_info *sensor; 1348 const struct max10_sensor_raw_data *raw; 1349 const struct max10_sensor_raw_data *table = 1350 (const struct max10_sensor_raw_data *)sdata->table; 1351 unsigned int i; 1352 static unsigned int sensor_id; 1353 int ret = 0; 1354 1355 for (i = 0; i < sdata->number; i++) { 1356 raw = &table[i]; 1357 1358 sensor = opae_zmalloc(sizeof(*sensor)); 1359 if (!sensor) { 1360 ret = -EINVAL; 1361 goto free_sensor; 1362 } 1363 1364 sensor->type = sdata->type; 1365 sensor->id = sensor_id++; 1366 1367 if (!raw->reg_input) 1368 continue; 1369 1370 sensor->value_reg = raw->reg_input; 1371 sensor->multiplier = raw->multiplier; 1372 sensor->name = raw->label; 1373 1374 ret = get_sensor_data(dev, sensor, 1375 &sensor->high_warn, 1376 raw->reg_high_warn, 1377 OPAE_SENSOR_HIGH_WARN_VALID); 1378 if (ret) 1379 break; 1380 1381 ret = get_sensor_data(dev, sensor, 1382 &sensor->high_fatal, 1383 raw->reg_high_fatal, 1384 OPAE_SENSOR_HIGH_FATAL_VALID); 1385 if (ret) 1386 break; 1387 1388 ret = get_sensor_data(dev, sensor, 1389 &sensor->hysteresis, 1390 raw->reg_hyst, 1391 OPAE_SENSOR_HYSTERESIS_VALID); 1392 if (ret) 1393 break; 1394 1395 ret = get_sensor_data(dev, sensor, 1396 &sensor->low_warn, 1397 raw->reg_low_warn, 1398 OPAE_SENSOR_LOW_WARN_VALID); 1399 if (ret) 1400 break; 1401 1402 sensor->flags |= OPAE_SENSOR_VALID; 1403 1404 TAILQ_INSERT_TAIL(&dev->opae_sensor_list, sensor, node); 1405 dev_info(dev, "found valid sensor: %s\n", sensor->name); 1406 } 1407 1408 return ret; 1409 1410 free_sensor: 1411 max10_sensor_uinit(dev); 1412 return ret; 1413 } 1414 1415 static int max10_sensor_init_table(struct intel_max10_device *dev, 1416 const struct max10_sensor_board_data *data) 1417 { 1418 int ret = 0; 1419 unsigned int i; 1420 const struct max10_sensor_data *sdata; 1421 1422 for (i = 0; i < ARRAY_SIZE(data->tables); i++) { 1423 sdata = data->tables[i]; 1424 if (!sdata) 1425 continue; 1426 ret = max10_parse_sensor_data(dev, sdata); 1427 if (ret) 1428 break; 1429 } 1430 1431 return ret; 1432 } 1433 1434 int 1435 intel_max10_device_init(struct intel_max10_device *dev) 1436 { 1437 int ret = 0; 1438 1439 TAILQ_INIT(&dev->opae_sensor_list); 1440 1441 1442 if (dev->type == M10_N3000) { 1443 dev->ops = &m10bmc_n3000_regmap; 1444 dev->csr = &m10bmc_spi_csr; 1445 1446 dev->raw_blk_ops.write_blk = n3000_bulk_raw_write; 1447 dev->raw_blk_ops.read_blk = n3000_bulk_raw_read; 1448 dev->bmc_ops.flash_read = n3000_flash_read; 1449 dev->bmc_ops.flash_write = n3000_flash_write; 1450 1451 /* check the max10 version */ 1452 ret = check_max10_version(dev); 1453 if (ret) { 1454 dev_err(dev, "Failed to find max10 hardware!\n"); 1455 return ret; 1456 } 1457 1458 /* load the MAX10 device table */ 1459 ret = init_max10_device_table(dev); 1460 if (ret) { 1461 dev_err(dev, "Init max10 device table fail\n"); 1462 return ret; 1463 } 1464 1465 /* init max10 devices, like sensor*/ 1466 if (dev->flags & MAX10_FLAGS_SECURE) 1467 ret = max10_secure_hw_init(dev); 1468 else 1469 ret = max10_non_secure_hw_init(dev); 1470 if (ret) { 1471 dev_err(dev, "Failed to init max10 hardware!\n"); 1472 opae_free(dev->fdt_root); 1473 return ret; 1474 } 1475 } else if (dev->type == M10_N6000) { 1476 dev->ops = &m10bmc_pmci_regmap; 1477 dev->csr = &m10bmc_pmci_csr; 1478 dev->staging_area_size = MAX_STAGING_AREA_SIZE; 1479 dev->flags |= MAX10_FLAGS_SECURE; 1480 1481 dev->bmc_ops.flash_read = pmci_flash_bulk_read; 1482 dev->bmc_ops.flash_write = pmci_flash_bulk_write; 1483 dev->bmc_ops.check_flash_range = pmci_check_flash_address; 1484 1485 ret = max10_sensor_init_table(dev, &n6000bmc_sensor_board_data); 1486 if (ret) 1487 return ret; 1488 1489 pthread_mutex_init(&dev->bmc_ops.lock, NULL); 1490 if (!dev->bmc_ops.mutex) 1491 dev->bmc_ops.mutex = &dev->bmc_ops.lock; 1492 } 1493 1494 return ret; 1495 } 1496 1497 int intel_max10_device_remove(struct intel_max10_device *dev) 1498 { 1499 if (!dev) 1500 return 0; 1501 1502 pthread_mutex_destroy(&dev->bmc_ops.lock); 1503 1504 if (dev->type == M10_N3000) { 1505 max10_sensor_uinit(dev); 1506 1507 if (dev->fdt_root) 1508 opae_free(dev->fdt_root); 1509 } 1510 1511 return 0; 1512 } 1513