1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2018 Intel Corporation 3 */ 4 5 #ifndef _OPAE_IFPGA_HW_API_H_ 6 #define _OPAE_IFPGA_HW_API_H_ 7 8 #include "opae_hw_api.h" 9 10 /** 11 * struct feature_prop - data structure for feature property 12 * @feature_id: id of this feature. 13 * @prop_id: id of this property under this feature. 14 * @data: property value to set/get. 15 */ 16 struct feature_prop { 17 u64 feature_id; 18 u64 prop_id; 19 u64 data; 20 }; 21 22 #define IFPGA_FIU_ID_FME 0x0 23 #define IFPGA_FIU_ID_PORT 0x1 24 25 #define IFPGA_FME_FEATURE_ID_HEADER 0x0 26 #define IFPGA_FME_FEATURE_ID_THERMAL_MGMT 0x1 27 #define IFPGA_FME_FEATURE_ID_POWER_MGMT 0x2 28 #define IFPGA_FME_FEATURE_ID_GLOBAL_IPERF 0x3 29 #define IFPGA_FME_FEATURE_ID_GLOBAL_ERR 0x4 30 #define IFPGA_FME_FEATURE_ID_PR_MGMT 0x5 31 #define IFPGA_FME_FEATURE_ID_HSSI 0x6 32 #define IFPGA_FME_FEATURE_ID_GLOBAL_DPERF 0x7 33 34 #define IFPGA_PORT_FEATURE_ID_HEADER 0x0 35 #define IFPGA_PORT_FEATURE_ID_AFU 0xff 36 #define IFPGA_PORT_FEATURE_ID_ERROR 0x10 37 #define IFPGA_PORT_FEATURE_ID_UMSG 0x11 38 #define IFPGA_PORT_FEATURE_ID_UINT 0x12 39 #define IFPGA_PORT_FEATURE_ID_STP 0x13 40 41 /* 42 * PROP format (TOP + SUB + ID) 43 * 44 * (~0x0) means this field is unused. 45 */ 46 #define PROP_TOP GENMASK(31, 24) 47 #define PROP_TOP_UNUSED 0xff 48 #define PROP_SUB GENMASK(23, 16) 49 #define PROP_SUB_UNUSED 0xff 50 #define PROP_ID GENMASK(15, 0) 51 52 #define PROP(_top, _sub, _id) \ 53 (SET_FIELD(PROP_TOP, _top) | SET_FIELD(PROP_SUB, _sub) |\ 54 SET_FIELD(PROP_ID, _id)) 55 56 /* FME head feature's properties*/ 57 #define FME_HDR_PROP_REVISION 0x1 /* RDONLY */ 58 #define FME_HDR_PROP_PORTS_NUM 0x2 /* RDONLY */ 59 #define FME_HDR_PROP_CACHE_SIZE 0x3 /* RDONLY */ 60 #define FME_HDR_PROP_VERSION 0x4 /* RDONLY */ 61 #define FME_HDR_PROP_SOCKET_ID 0x5 /* RDONLY */ 62 #define FME_HDR_PROP_BITSTREAM_ID 0x6 /* RDONLY */ 63 #define FME_HDR_PROP_BITSTREAM_METADATA 0x7 /* RDONLY */ 64 #define FME_HDR_PROP_PORT_TYPE 0x8 /* RDWR */ 65 66 /* FME error reporting feature's properties */ 67 /* FME error reporting properties format */ 68 #define ERR_PROP(_top, _id) PROP(_top, 0xff, _id) 69 #define ERR_PROP_TOP_UNUSED PROP_TOP_UNUSED 70 #define ERR_PROP_TOP_FME_ERR 0x1 71 #define ERR_PROP_ROOT(_id) ERR_PROP(0xff, _id) 72 #define ERR_PROP_FME_ERR(_id) ERR_PROP(ERR_PROP_TOP_FME_ERR, _id) 73 74 #define FME_ERR_PROP_ERRORS ERR_PROP_FME_ERR(0x1) 75 #define FME_ERR_PROP_FIRST_ERROR ERR_PROP_FME_ERR(0x2) 76 #define FME_ERR_PROP_NEXT_ERROR ERR_PROP_FME_ERR(0x3) 77 #define FME_ERR_PROP_CLEAR ERR_PROP_FME_ERR(0x4) /* WO */ 78 #define FME_ERR_PROP_SEU_EMR_LOW ERR_PROP_FME_ERR(0x5) 79 #define FME_ERR_PROP_SEU_EMR_HIGH ERR_PROP_FME_ERR(0x6) 80 #define FME_ERR_PROP_REVISION ERR_PROP_ROOT(0x5) 81 #define FME_ERR_PROP_PCIE0_ERRORS ERR_PROP_ROOT(0x6) /* RW */ 82 #define FME_ERR_PROP_PCIE1_ERRORS ERR_PROP_ROOT(0x7) /* RW */ 83 #define FME_ERR_PROP_NONFATAL_ERRORS ERR_PROP_ROOT(0x8) 84 #define FME_ERR_PROP_CATFATAL_ERRORS ERR_PROP_ROOT(0x9) 85 #define FME_ERR_PROP_INJECT_ERRORS ERR_PROP_ROOT(0xa) /* RW */ 86 87 /* FME thermal feature's properties */ 88 #define FME_THERMAL_PROP_THRESHOLD1 0x1 /* RW */ 89 #define FME_THERMAL_PROP_THRESHOLD2 0x2 /* RW */ 90 #define FME_THERMAL_PROP_THRESHOLD_TRIP 0x3 /* RDONLY */ 91 #define FME_THERMAL_PROP_THRESHOLD1_REACHED 0x4 /* RDONLY */ 92 #define FME_THERMAL_PROP_THRESHOLD2_REACHED 0x5 /* RDONLY */ 93 #define FME_THERMAL_PROP_THRESHOLD1_POLICY 0x6 /* RW */ 94 #define FME_THERMAL_PROP_TEMPERATURE 0x7 /* RDONLY */ 95 #define FME_THERMAL_PROP_REVISION 0x8 /* RDONLY */ 96 97 /* FME power feature's properties */ 98 #define FME_PWR_PROP_CONSUMED 0x1 /* RDONLY */ 99 #define FME_PWR_PROP_THRESHOLD1 0x2 /* RW */ 100 #define FME_PWR_PROP_THRESHOLD2 0x3 /* RW */ 101 #define FME_PWR_PROP_THRESHOLD1_STATUS 0x4 /* RDONLY */ 102 #define FME_PWR_PROP_THRESHOLD2_STATUS 0x5 /* RDONLY */ 103 #define FME_PWR_PROP_RTL 0x6 /* RDONLY */ 104 #define FME_PWR_PROP_XEON_LIMIT 0x7 /* RDONLY */ 105 #define FME_PWR_PROP_FPGA_LIMIT 0x8 /* RDONLY */ 106 #define FME_PWR_PROP_REVISION 0x9 /* RDONLY */ 107 108 /* FME iperf/dperf PROP format */ 109 #define PERF_PROP_TOP_CACHE 0x1 110 #define PERF_PROP_TOP_VTD 0x2 111 #define PERF_PROP_TOP_FAB 0x3 112 #define PERF_PROP_TOP_UNUSED PROP_TOP_UNUSED 113 #define PERF_PROP_SUB_UNUSED PROP_SUB_UNUSED 114 115 #define PERF_PROP_ROOT(_id) PROP(0xff, 0xff, _id) 116 #define PERF_PROP_CACHE(_id) PROP(PERF_PROP_TOP_CACHE, 0xff, _id) 117 #define PERF_PROP_VTD(_sub, _id) PROP(PERF_PROP_TOP_VTD, _sub, _id) 118 #define PERF_PROP_VTD_ROOT(_id) PROP(PERF_PROP_TOP_VTD, 0xff, _id) 119 #define PERF_PROP_FAB(_sub, _id) PROP(PERF_PROP_TOP_FAB, _sub, _id) 120 #define PERF_PROP_FAB_ROOT(_id) PROP(PERF_PROP_TOP_FAB, 0xff, _id) 121 122 /* FME iperf feature's properties */ 123 #define FME_IPERF_PROP_CLOCK PERF_PROP_ROOT(0x1) 124 #define FME_IPERF_PROP_REVISION PERF_PROP_ROOT(0x2) 125 126 /* iperf CACHE properties */ 127 #define FME_IPERF_PROP_CACHE_FREEZE PERF_PROP_CACHE(0x1) /* RW */ 128 #define FME_IPERF_PROP_CACHE_READ_HIT PERF_PROP_CACHE(0x2) 129 #define FME_IPERF_PROP_CACHE_READ_MISS PERF_PROP_CACHE(0x3) 130 #define FME_IPERF_PROP_CACHE_WRITE_HIT PERF_PROP_CACHE(0x4) 131 #define FME_IPERF_PROP_CACHE_WRITE_MISS PERF_PROP_CACHE(0x5) 132 #define FME_IPERF_PROP_CACHE_HOLD_REQUEST PERF_PROP_CACHE(0x6) 133 #define FME_IPERF_PROP_CACHE_TX_REQ_STALL PERF_PROP_CACHE(0x7) 134 #define FME_IPERF_PROP_CACHE_RX_REQ_STALL PERF_PROP_CACHE(0x8) 135 #define FME_IPERF_PROP_CACHE_RX_EVICTION PERF_PROP_CACHE(0x9) 136 #define FME_IPERF_PROP_CACHE_DATA_WRITE_PORT_CONTENTION PERF_PROP_CACHE(0xa) 137 #define FME_IPERF_PROP_CACHE_TAG_WRITE_PORT_CONTENTION PERF_PROP_CACHE(0xb) 138 /* iperf VTD properties */ 139 #define FME_IPERF_PROP_VTD_FREEZE PERF_PROP_VTD_ROOT(0x1) /* RW */ 140 #define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_HIT PERF_PROP_VTD_ROOT(0x2) 141 #define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_HIT PERF_PROP_VTD_ROOT(0x3) 142 #define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_HIT PERF_PROP_VTD_ROOT(0x4) 143 #define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_HIT PERF_PROP_VTD_ROOT(0x5) 144 #define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_HIT PERF_PROP_VTD_ROOT(0x6) 145 #define FME_IPERF_PROP_VTD_SIP_RCC_HIT PERF_PROP_VTD_ROOT(0x7) 146 #define FME_IPERF_PROP_VTD_SIP_IOTLB_4K_MISS PERF_PROP_VTD_ROOT(0x8) 147 #define FME_IPERF_PROP_VTD_SIP_IOTLB_2M_MISS PERF_PROP_VTD_ROOT(0x9) 148 #define FME_IPERF_PROP_VTD_SIP_IOTLB_1G_MISS PERF_PROP_VTD_ROOT(0xa) 149 #define FME_IPERF_PROP_VTD_SIP_SLPWC_L3_MISS PERF_PROP_VTD_ROOT(0xb) 150 #define FME_IPERF_PROP_VTD_SIP_SLPWC_L4_MISS PERF_PROP_VTD_ROOT(0xc) 151 #define FME_IPERF_PROP_VTD_SIP_RCC_MISS PERF_PROP_VTD_ROOT(0xd) 152 #define FME_IPERF_PROP_VTD_PORT_READ_TRANSACTION(n) PERF_PROP_VTD(n, 0xe) 153 #define FME_IPERF_PROP_VTD_PORT_WRITE_TRANSACTION(n) PERF_PROP_VTD(n, 0xf) 154 #define FME_IPERF_PROP_VTD_PORT_DEVTLB_READ_HIT(n) PERF_PROP_VTD(n, 0x10) 155 #define FME_IPERF_PROP_VTD_PORT_DEVTLB_WRITE_HIT(n) PERF_PROP_VTD(n, 0x11) 156 #define FME_IPERF_PROP_VTD_PORT_DEVTLB_4K_FILL(n) PERF_PROP_VTD(n, 0x12) 157 #define FME_IPERF_PROP_VTD_PORT_DEVTLB_2M_FILL(n) PERF_PROP_VTD(n, 0x13) 158 #define FME_IPERF_PROP_VTD_PORT_DEVTLB_1G_FILL(n) PERF_PROP_VTD(n, 0x14) 159 /* iperf FAB properties */ 160 #define FME_IPERF_PROP_FAB_FREEZE PERF_PROP_FAB_ROOT(0x1) /* RW */ 161 #define FME_IPERF_PROP_FAB_PCIE0_READ PERF_PROP_FAB_ROOT(0x2) 162 #define FME_IPERF_PROP_FAB_PORT_PCIE0_READ(n) PERF_PROP_FAB(n, 0x2) 163 #define FME_IPERF_PROP_FAB_PCIE0_WRITE PERF_PROP_FAB_ROOT(0x3) 164 #define FME_IPERF_PROP_FAB_PORT_PCIE0_WRITE(n) PERF_PROP_FAB(n, 0x3) 165 #define FME_IPERF_PROP_FAB_PCIE1_READ PERF_PROP_FAB_ROOT(0x4) 166 #define FME_IPERF_PROP_FAB_PORT_PCIE1_READ(n) PERF_PROP_FAB(n, 0x4) 167 #define FME_IPERF_PROP_FAB_PCIE1_WRITE PERF_PROP_FAB_ROOT(0x5) 168 #define FME_IPERF_PROP_FAB_PORT_PCIE1_WRITE(n) PERF_PROP_FAB(n, 0x5) 169 #define FME_IPERF_PROP_FAB_UPI_READ PERF_PROP_FAB_ROOT(0x6) 170 #define FME_IPERF_PROP_FAB_PORT_UPI_READ(n) PERF_PROP_FAB(n, 0x6) 171 #define FME_IPERF_PROP_FAB_UPI_WRITE PERF_PROP_FAB_ROOT(0x7) 172 #define FME_IPERF_PROP_FAB_PORT_UPI_WRITE(n) PERF_PROP_FAB(n, 0x7) 173 #define FME_IPERF_PROP_FAB_MMIO_READ PERF_PROP_FAB_ROOT(0x8) 174 #define FME_IPERF_PROP_FAB_PORT_MMIO_READ(n) PERF_PROP_FAB(n, 0x8) 175 #define FME_IPERF_PROP_FAB_MMIO_WRITE PERF_PROP_FAB_ROOT(0x9) 176 #define FME_IPERF_PROP_FAB_PORT_MMIO_WRITE(n) PERF_PROP_FAB(n, 0x9) 177 #define FME_IPERF_PROP_FAB_ENABLE PERF_PROP_FAB_ROOT(0xa) /* RW */ 178 #define FME_IPERF_PROP_FAB_PORT_ENABLE(n) PERF_PROP_FAB(n, 0xa) /* RW */ 179 180 /* FME dperf properties */ 181 #define FME_DPERF_PROP_CLOCK PERF_PROP_ROOT(0x1) 182 #define FME_DPERF_PROP_REVISION PERF_PROP_ROOT(0x2) 183 184 /* dperf FAB properties */ 185 #define FME_DPERF_PROP_FAB_FREEZE PERF_PROP_FAB_ROOT(0x1) /* RW */ 186 #define FME_DPERF_PROP_FAB_PCIE0_READ PERF_PROP_FAB_ROOT(0x2) 187 #define FME_DPERF_PROP_FAB_PORT_PCIE0_READ(n) PERF_PROP_FAB(n, 0x2) 188 #define FME_DPERF_PROP_FAB_PCIE0_WRITE PERF_PROP_FAB_ROOT(0x3) 189 #define FME_DPERF_PROP_FAB_PORT_PCIE0_WRITE(n) PERF_PROP_FAB(n, 0x3) 190 #define FME_DPERF_PROP_FAB_MMIO_READ PERF_PROP_FAB_ROOT(0x4) 191 #define FME_DPERF_PROP_FAB_PORT_MMIO_READ(n) PERF_PROP_FAB(n, 0x4) 192 #define FME_DPERF_PROP_FAB_MMIO_WRITE PERF_PROP_FAB_ROOT(0x5) 193 #define FME_DPERF_PROP_FAB_PORT_MMIO_WRITE(n) PERF_PROP_FAB(n, 0x5) 194 #define FME_DPERF_PROP_FAB_ENABLE PERF_PROP_FAB_ROOT(0x6) /* RW */ 195 #define FME_DPERF_PROP_FAB_PORT_ENABLE(n) PERF_PROP_FAB(n, 0x6) /* RW */ 196 197 /*PORT hdr feature's properties*/ 198 #define PORT_HDR_PROP_REVISION 0x1 /* RDONLY */ 199 #define PORT_HDR_PROP_PORTIDX 0x2 /* RDONLY */ 200 #define PORT_HDR_PROP_LATENCY_TOLERANCE 0x3 /* RDONLY */ 201 #define PORT_HDR_PROP_AP1_EVENT 0x4 /* RW */ 202 #define PORT_HDR_PROP_AP2_EVENT 0x5 /* RW */ 203 #define PORT_HDR_PROP_POWER_STATE 0x6 /* RDONLY */ 204 #define PORT_HDR_PROP_USERCLK_FREQCMD 0x7 /* RW */ 205 #define PORT_HDR_PROP_USERCLK_FREQCNTRCMD 0x8 /* RW */ 206 #define PORT_HDR_PROP_USERCLK_FREQSTS 0x9 /* RDONLY */ 207 #define PORT_HDR_PROP_USERCLK_CNTRSTS 0xa /* RDONLY */ 208 209 /*PORT error feature's properties*/ 210 #define PORT_ERR_PROP_REVISION 0x1 /* RDONLY */ 211 #define PORT_ERR_PROP_ERRORS 0x2 /* RDONLY */ 212 #define PORT_ERR_PROP_FIRST_ERROR 0x3 /* RDONLY */ 213 #define PORT_ERR_PROP_FIRST_MALFORMED_REQ_LSB 0x4 /* RDONLY */ 214 #define PORT_ERR_PROP_FIRST_MALFORMED_REQ_MSB 0x5 /* RDONLY */ 215 #define PORT_ERR_PROP_CLEAR 0x6 /* WRONLY */ 216 217 int opae_manager_ifpga_get_prop(struct opae_manager *mgr, 218 struct feature_prop *prop); 219 int opae_manager_ifpga_set_prop(struct opae_manager *mgr, 220 struct feature_prop *prop); 221 int opae_bridge_ifpga_get_prop(struct opae_bridge *br, 222 struct feature_prop *prop); 223 int opae_bridge_ifpga_set_prop(struct opae_bridge *br, 224 struct feature_prop *prop); 225 226 /* 227 * Retrieve information about the fpga fme. 228 * Driver fills the info in provided struct fpga_fme_info. 229 */ 230 struct fpga_fme_info { 231 u32 capability; /* The capability of FME device */ 232 #define FPGA_FME_CAP_ERR_IRQ (1 << 0) /* Support fme error interrupt */ 233 }; 234 235 int opae_manager_ifpga_get_info(struct opae_manager *mgr, 236 struct fpga_fme_info *fme_info); 237 238 /* Set eventfd information for ifpga FME error interrupt */ 239 struct fpga_fme_err_irq_set { 240 s32 evtfd; /* Eventfd handler */ 241 }; 242 243 int opae_manager_ifpga_set_err_irq(struct opae_manager *mgr, 244 struct fpga_fme_err_irq_set *err_irq_set); 245 246 /* 247 * Retrieve information about the fpga port. 248 * Driver fills the info in provided struct fpga_port_info. 249 */ 250 struct fpga_port_info { 251 u32 capability; /* The capability of port device */ 252 #define FPGA_PORT_CAP_ERR_IRQ (1 << 0) /* Support port error interrupt */ 253 #define FPGA_PORT_CAP_UAFU_IRQ (1 << 1) /* Support uafu error interrupt */ 254 u32 num_umsgs; /* The number of allocated umsgs */ 255 u32 num_uafu_irqs; /* The number of uafu interrupts */ 256 }; 257 258 int opae_bridge_ifpga_get_info(struct opae_bridge *br, 259 struct fpga_port_info *port_info); 260 /* 261 * Retrieve region information about the fpga port. 262 * Driver needs to fill the index of struct fpga_port_region_info. 263 */ 264 struct fpga_port_region_info { 265 u32 index; 266 #define PORT_REGION_INDEX_STP (1 << 1) /* Signal Tap Region */ 267 u64 size; /* Region Size */ 268 u8 *addr; /* Base address of the region */ 269 }; 270 271 int opae_bridge_ifpga_get_region_info(struct opae_bridge *br, 272 struct fpga_port_region_info *info); 273 274 /* Set eventfd information for ifpga port error interrupt */ 275 struct fpga_port_err_irq_set { 276 s32 evtfd; /* Eventfd handler */ 277 }; 278 279 int opae_bridge_ifpga_set_err_irq(struct opae_bridge *br, 280 struct fpga_port_err_irq_set *err_irq_set); 281 282 #endif /* _OPAE_IFPGA_HW_API_H_ */ 283