1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2024 ZTE Corporation 3 */ 4 5 #ifndef GDTC_RAWDEV_H 6 #define GDTC_RAWDEV_H 7 8 #include <stdint.h> 9 #include <rte_log.h> 10 #include <rte_common.h> 11 #include <generic/rte_spinlock.h> 12 13 extern int zxdh_gdma_rawdev_logtype; 14 #define RTE_LOGTYPE_ZXDH_GDMA zxdh_gdma_rawdev_logtype 15 16 #define ZXDH_PMD_LOG(level, ...) \ 17 RTE_LOG_LINE_PREFIX(level, ZXDH_GDMA, \ 18 "%s() line %u: ", __func__ RTE_LOG_COMMA __LINE__, __VA_ARGS__) 19 20 #define ZXDH_GDMA_VENDORID 0x1cf2 21 #define ZXDH_GDMA_DEVICEID 0x8044 22 23 #define ZXDH_GDMA_TOTAL_CHAN_NUM 58 24 #define ZXDH_GDMA_QUEUE_SIZE 16384 25 #define ZXDH_GDMA_RING_SIZE 32768 26 27 /* States if the source addresses is physical. */ 28 #define ZXDH_GDMA_JOB_SRC_PHY (1UL) 29 30 /* States if the destination addresses is physical. */ 31 #define ZXDH_GDMA_JOB_DEST_PHY (1UL << 1) 32 33 /* ZF->HOST */ 34 #define ZXDH_GDMA_JOB_DIR_TX (1UL << 2) 35 36 /* HOST->ZF */ 37 #define ZXDH_GDMA_JOB_DIR_RX (1UL << 3) 38 39 #define ZXDH_GDMA_JOB_DIR_MASK (ZXDH_GDMA_JOB_DIR_TX | ZXDH_GDMA_JOB_DIR_RX) 40 41 enum zxdh_gdma_device_state { 42 ZXDH_GDMA_DEV_RUNNING, 43 ZXDH_GDMA_DEV_STOPPED 44 }; 45 46 struct zxdh_gdma_buff_desc { 47 uint32_t SrcAddr_L; 48 uint32_t DstAddr_L; 49 uint32_t Xpara; 50 uint32_t ZY_para; 51 uint32_t ZY_SrcStep; 52 uint32_t ZY_DstStep; 53 uint32_t ExtAddr; 54 uint32_t LLI_Addr_L; 55 uint32_t LLI_Addr_H; 56 uint32_t ChCont; 57 uint32_t LLI_User; 58 uint32_t ErrAddr; 59 uint32_t Control; 60 uint32_t SrcAddr_H; 61 uint32_t DstAddr_H; 62 uint32_t Reserved; 63 }; 64 65 struct zxdh_gdma_job { 66 uint64_t src; 67 uint64_t dest; 68 uint32_t len; 69 uint32_t flags; 70 uint64_t cnxt; 71 uint16_t status; 72 uint16_t vq_id; 73 void *usr_elem; 74 uint8_t ep_id; 75 uint8_t pf_id; 76 uint16_t vf_id; 77 }; 78 79 struct zxdh_gdma_queue { 80 uint8_t enable; 81 uint8_t is_txq; 82 uint16_t vq_id; 83 uint16_t queue_size; 84 /* 0:GDMA needs to be configured through the APB interface */ 85 uint16_t flag; 86 uint32_t user; 87 uint16_t tc_cnt; 88 rte_spinlock_t enqueue_lock; 89 struct { 90 uint16_t avail_idx; 91 uint16_t last_avail_idx; 92 rte_iova_t ring_mem; 93 const struct rte_memzone *ring_mz; 94 struct zxdh_gdma_buff_desc *desc; 95 } ring; 96 struct { 97 uint16_t free_cnt; 98 uint16_t deq_cnt; 99 uint16_t pend_cnt; 100 uint16_t enq_idx; 101 uint16_t deq_idx; 102 uint16_t used_idx; 103 struct zxdh_gdma_job **job; 104 } sw_ring; 105 }; 106 107 struct zxdh_gdma_rawdev { 108 struct rte_device *device; 109 struct rte_rawdev *rawdev; 110 uintptr_t base_addr; 111 uint8_t queue_num; /* total queue num */ 112 uint8_t used_num; /* used queue num */ 113 enum zxdh_gdma_device_state device_state; 114 struct zxdh_gdma_queue vqs[ZXDH_GDMA_TOTAL_CHAN_NUM]; 115 }; 116 117 struct zxdh_gdma_enqdeq { 118 uint16_t vq_id; 119 struct zxdh_gdma_job **job; 120 }; 121 122 struct zxdh_gdma_config { 123 uint16_t max_hw_queues_per_core; 124 uint16_t max_vqs; 125 int queue_pool_cnt; 126 }; 127 128 struct zxdh_gdma_rbp { 129 uint32_t use_ultrashort:1; 130 uint32_t enable:1; 131 uint32_t dportid:3; 132 uint32_t dpfid:3; 133 uint32_t dvfid:8; /* using route by port for destination */ 134 uint32_t drbp:1; 135 uint32_t sportid:3; 136 uint32_t spfid:3; 137 uint32_t svfid:8; 138 uint32_t srbp:1; 139 }; 140 141 struct zxdh_gdma_queue_config { 142 uint32_t lcore_id; 143 uint32_t flags; 144 struct zxdh_gdma_rbp *rbp; 145 }; 146 147 struct zxdh_gdma_attr { 148 uint16_t num_hw_queues; 149 }; 150 151 #endif /* GDTC_RAWDEV_H */ 152