1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _CNXK_BPHY_H_ 6 #define _CNXK_BPHY_H_ 7 8 #include <stdint.h> 9 10 #include <rte_common.h> 11 #include <rte_dev.h> 12 #include <rte_malloc.h> 13 #include <rte_memcpy.h> 14 #include <rte_rawdev.h> 15 16 /** 17 * @file rte_pmd_bphy.h 18 * 19 * Marvell CGX and BPHY PMD specific structures and interface 20 * 21 * This API allows applications to manage BPHY memory in user space along with 22 * installing interrupt handlers for low latency signal processing. 23 */ 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 extern int cnxk_logtype_bphy; 30 #define RTE_LOGTYPE_CNXK_BPHY cnxk_logtype_bphy 31 32 #define CNXK_BPHY_LOG(level, ...) \ 33 RTE_LOG_LINE_PREFIX(level, CNXK_BPHY, "%s(): ", __func__, __VA_ARGS__) 34 35 /** Available message types */ 36 enum cnxk_bphy_cgx_msg_type { 37 /** Type used to obtain link information */ 38 CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, 39 /** Type used to disable internal loopback */ 40 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, 41 /** Type used to enable loopback */ 42 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE, 43 /** Type used to disable PTP on RX */ 44 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE, 45 /** Type used to enable PTP on RX */ 46 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE, 47 /** Type used to set link mode */ 48 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE, 49 /** Type used to set link state */ 50 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE, 51 /** Type used to start transmission and packet reception */ 52 CNXK_BPHY_CGX_MSG_TYPE_START_RXTX, 53 /** Type used to stop transmission and packet reception */ 54 CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX, 55 /** Type used to obtain supported FEC */ 56 CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC, 57 /** Type used to set FEC */ 58 CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, 59 /** Type used to switch from eCPRI to CPRI */ 60 CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, 61 /** Type used to enable TX for CPRI SERDES */ 62 CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, 63 /** Type use to change misc CPRI SERDES settings */ 64 CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, 65 }; 66 67 /** Available link speeds */ 68 enum cnxk_bphy_cgx_eth_link_speed { 69 CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, /**< None */ 70 CNXK_BPHY_CGX_ETH_LINK_SPEED_10M, /**< 10 Mbps */ 71 CNXK_BPHY_CGX_ETH_LINK_SPEED_100M, /**< 100 Mbps */ 72 CNXK_BPHY_CGX_ETH_LINK_SPEED_1G, /**< 1 Gbps */ 73 CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, /**< 2.5 Gbps */ 74 CNXK_BPHY_CGX_ETH_LINK_SPEED_5G, /**< 5 Gbps */ 75 CNXK_BPHY_CGX_ETH_LINK_SPEED_10G, /**< 10 Gbps */ 76 CNXK_BPHY_CGX_ETH_LINK_SPEED_20G, /**< 20 Gbps */ 77 CNXK_BPHY_CGX_ETH_LINK_SPEED_25G, /**< 25 Gbps */ 78 CNXK_BPHY_CGX_ETH_LINK_SPEED_40G, /**< 40 Gbps */ 79 CNXK_BPHY_CGX_ETH_LINK_SPEED_50G, /**< 50 Gbps */ 80 CNXK_BPHY_CGX_ETH_LINK_SPEED_80G, /**< 80 Gbps */ 81 CNXK_BPHY_CGX_ETH_LINK_SPEED_100G, /**< 100 Gbps */ 82 __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX 83 }; 84 85 /** Available FEC modes */ 86 enum cnxk_bphy_cgx_eth_link_fec { 87 /** Disable FEC */ 88 CNXK_BPHY_CGX_ETH_LINK_FEC_NONE, 89 /** Base FEC (IEEE 802.3 CLause 74) */ 90 CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R, 91 /** Reed-Solomon FEC */ 92 CNXK_BPHY_CGX_ETH_LINK_FEC_RS, 93 __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX 94 }; 95 96 /** Available link modes */ 97 enum cnxk_bphy_cgx_eth_link_mode { 98 /** SGMII */ 99 CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, 100 /** 1000BASE-X */ 101 CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, 102 /** QSGMII */ 103 CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, 104 /** 10GBASE-C2C */ 105 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, 106 /** 10GBASE-C2M */ 107 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, 108 /** 10GBASE-KR */ 109 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, 110 /** 20GBASE-C2C */ 111 CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, 112 /** 25GBASE-C2C */ 113 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, 114 /** 25GBASE-C2M */ 115 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, 116 /** 25GBASE-2-C2M */ 117 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, 118 /** 25GBASE-CR */ 119 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, 120 /** 25GBASE-KR */ 121 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, 122 /** 40GBASE-C2C */ 123 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, 124 /** 40GBASE-C2M */ 125 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, 126 /** 40GBASE-CR4 */ 127 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, 128 /** 40GBASE-KR4 */ 129 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, 130 /** 40GAUI-C2C */ 131 CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, 132 /** 50GBASE-C2C */ 133 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, 134 /** 50GBASE-C2M */ 135 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, 136 /** 50GBASE-4-C2C */ 137 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, 138 /** 50GBASE-CR */ 139 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, 140 /** 50GBASE-KR */ 141 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, 142 /** 80GAUI-C2C */ 143 CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, 144 /** 100GBASE-C2C */ 145 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, 146 /** 100GBASE-C2M */ 147 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, 148 /** 100GBASE-CR4 */ 149 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, 150 /** 100GBASE-KR4 */ 151 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, 152 /** 50GAUI-2-C2C */ 153 CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT, 154 /** 50GAUI-2-C2M */ 155 CNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT, 156 /** 50GBASE-CR2-C */ 157 CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT, 158 /** 50GBASE-KR2-C */ 159 CNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT, 160 /** 100GAUI-2-C2C */ 161 CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT, 162 /** 100GAUI-2-C2M */ 163 CNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT, 164 /** 100GBASE-CR2 */ 165 CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT, 166 /** 100GBASE-KR2 */ 167 CNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT, 168 /** SFI-1G */ 169 CNXK_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT, 170 /** 25GBASE-CR-C */ 171 CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT, 172 /** 25GBASE-KR-C */ 173 CNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT, 174 __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX 175 }; 176 177 enum cnxk_bphy_cgx_eth_mode_cpri { 178 /** 2.4G Lane Rate */ 179 CNXK_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT, 180 /** 3.1G Lane Rate */ 181 CNXK_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT, 182 /** 4.9G Lane Rate */ 183 CNXK_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT, 184 /** 6.1G Lane Rate */ 185 CNXK_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT, 186 /** 9.8G Lane Rate */ 187 CNXK_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT, 188 /** 10.1G Lane Rate */ 189 CNXK_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT, 190 /** 24.3G Lane Rate */ 191 CNXK_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT, 192 }; 193 194 enum cnxk_bphy_cgx_mode_group { 195 /** ETH group */ 196 CNXK_BPHY_CGX_MODE_GROUP_ETH, 197 /** CPRI group */ 198 CNXK_BPHY_CGX_MODE_GROUP_CPRI = 2, 199 }; 200 201 struct cnxk_bphy_cgx_msg_link_mode { 202 /** Setting for full-duplex */ 203 bool full_duplex; 204 /** Setting for automatic link negotiation */ 205 bool autoneg; 206 /** Set to true to use port index */ 207 bool use_portm_idx; 208 /** Port index */ 209 unsigned int portm_idx; 210 /** Mode group */ 211 enum cnxk_bphy_cgx_mode_group mode_group_idx; 212 /** Link speed */ 213 enum cnxk_bphy_cgx_eth_link_speed speed; 214 union { 215 /** Link mode */ 216 enum cnxk_bphy_cgx_eth_link_mode mode; 217 /** CPRI mode */ 218 enum cnxk_bphy_cgx_eth_mode_cpri mode_cpri; 219 }; 220 }; 221 222 struct cnxk_bphy_cgx_msg_link_info { 223 /** Link state information */ 224 bool link_up; 225 /** Link full duplex state */ 226 bool full_duplex; 227 /** Link speed */ 228 enum cnxk_bphy_cgx_eth_link_speed speed; 229 /** Link auto-negotiation setting */ 230 bool autoneg; 231 /** FEC mode */ 232 enum cnxk_bphy_cgx_eth_link_fec fec; 233 /** Link configuration */ 234 enum cnxk_bphy_cgx_eth_link_mode mode; 235 }; 236 237 struct cnxk_bphy_cgx_msg_set_link_state { 238 /** Defines link state result */ 239 bool state; /* up or down */ 240 /** Timeout in ms */ 241 int timeout; 242 /** Set if Rx/Tx should not be enabled during link up config */ 243 bool rx_tx_dis; 244 }; 245 246 struct cnxk_bphy_cgx_msg_cpri_mode_change { 247 /** SERDES index (0 - 4) */ 248 int gserc_idx; 249 /** Lane index (0 - 1) */ 250 int lane_idx; 251 /** Baud rate (9830/4915/2458/6144/3072) */ 252 int rate; 253 /** Disable LEQ */ 254 bool disable_leq; 255 /** Disable DFE */ 256 bool disable_dfe; 257 }; 258 259 struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl { 260 /** SERDES index (0 - 4) */ 261 int gserc_idx; 262 /** Lane index (0 - 1) */ 263 int lane_idx; 264 /** Disable or enable SERDES */ 265 bool enable; 266 }; 267 268 struct cnxk_bphy_cgx_msg_cpri_mode_misc { 269 /** SERDES index (0 - 4) */ 270 int gserc_idx; 271 /** Lane index (0 - 1) */ 272 int lane_idx; 273 /** Misc flags (0 - RX Eq, 1 - RX state machine reset) */ 274 int flags; 275 }; 276 277 struct cnxk_bphy_cgx_msg { 278 /** Message type */ 279 enum cnxk_bphy_cgx_msg_type type; 280 /** 281 * Data depends on message type and whether 282 * it's a request or a response 283 */ 284 void *data; 285 }; 286 287 #define CNXK_BPHY_DEF_QUEUE 0 288 289 /** 290 * BPHY interrupt handler 291 * 292 * @param irq_num 293 * Zero-based interrupt number 294 * @param isr_data 295 * Cookie passed to interrupt handler 296 */ 297 typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data); 298 299 struct cnxk_bphy_mem { 300 /** Memory for BAR0 */ 301 struct rte_mem_resource res0; 302 /** Memory for BAR2 */ 303 struct rte_mem_resource res2; 304 }; 305 306 /** Available IRQ configuration commands */ 307 enum cnxk_bphy_irq_msg_type { 308 /** Type used to initialize interrupts */ 309 CNXK_BPHY_IRQ_MSG_TYPE_INIT, 310 /** Type used to deinitialize interrupts */ 311 CNXK_BPHY_IRQ_MSG_TYPE_FINI, 312 /** Type used to register interrupt */ 313 CNXK_BPHY_IRQ_MSG_TYPE_REGISTER, 314 /** Type used to unregister interrupt */ 315 CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER, 316 /** Type used to retrieve BPHY memory */ 317 CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET, 318 /** Type used to retrieve NPA PF function */ 319 CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC, 320 /** Type used to retrieve NPA SSO function */ 321 CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC, 322 }; 323 324 struct cnxk_bphy_irq_msg { 325 /** Message command type */ 326 enum cnxk_bphy_irq_msg_type type; 327 /** 328 * Data depends on message type and whether 329 * it is a request or a response 330 */ 331 void *data; 332 }; 333 334 struct cnxk_bphy_irq_info { 335 /** Interrupt number */ 336 int irq_num; 337 /** Interrupt handler */ 338 cnxk_bphy_intr_handler_t handler; 339 /** Interrupt handler cookie */ 340 void *data; 341 /** CPU zero-based number for interrupt execution */ 342 int cpu; 343 }; 344 345 /** @internal helper routine for enqueuing/dequeuing messages */ 346 static __rte_always_inline int 347 __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req, 348 void *rsp, size_t rsp_size) 349 { 350 struct rte_rawdev_buf *bufs[1]; 351 struct rte_rawdev_buf buf; 352 void *q; 353 int ret; 354 355 q = (void *)(size_t)queue; 356 buf.buf_addr = req; 357 bufs[0] = &buf; 358 359 ret = rte_rawdev_enqueue_buffers(dev_id, bufs, RTE_DIM(bufs), q); 360 if (ret < 0) 361 return ret; 362 if (ret != RTE_DIM(bufs)) 363 return -EIO; 364 365 if (!rsp) 366 return 0; 367 368 ret = rte_rawdev_dequeue_buffers(dev_id, bufs, RTE_DIM(bufs), q); 369 if (ret < 0) 370 return ret; 371 if (ret != RTE_DIM(bufs)) 372 return -EIO; 373 374 rte_memcpy(rsp, buf.buf_addr, rsp_size); 375 rte_free(buf.buf_addr); 376 377 return 0; 378 } 379 380 /** 381 * Initialize BPHY subsystem 382 * 383 * @param dev_id 384 * The identifier of the device 385 * 386 * @return 387 * Returns 0 on success, negative error code otherwise 388 */ 389 static __rte_always_inline int 390 rte_pmd_bphy_intr_init(uint16_t dev_id) 391 { 392 struct cnxk_bphy_irq_msg msg = { 393 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT, 394 }; 395 396 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 397 NULL, 0); 398 } 399 400 /** 401 * Deinitialize BPHY subsystem 402 * 403 * @param dev_id 404 * The identifier of the device 405 * 406 * @return 407 * Returns 0 on success, negative error code otherwise 408 */ 409 static __rte_always_inline int 410 rte_pmd_bphy_intr_fini(uint16_t dev_id) 411 { 412 struct cnxk_bphy_irq_msg msg = { 413 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI, 414 }; 415 416 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 417 NULL, 0); 418 } 419 420 /** 421 * Register BPHY interrupt handler 422 * 423 * @param dev_id 424 * The identifier of the device 425 * @param irq_num 426 * Zero-based interrupt number 427 * @param handler 428 * Interrupt handler to be executed 429 * @param data 430 * Data to be passed to interrupt handler 431 * @param cpu 432 * CPU number which will be handling interrupt 433 * 434 * @return 435 * Returns 0 on success, negative error code otherwise 436 */ 437 static __rte_always_inline int 438 rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num, 439 cnxk_bphy_intr_handler_t handler, void *data, 440 int cpu) 441 { 442 struct cnxk_bphy_irq_info info = { 443 .irq_num = irq_num, 444 .handler = handler, 445 .data = data, 446 .cpu = cpu, 447 }; 448 struct cnxk_bphy_irq_msg msg = { 449 .type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER, 450 .data = &info 451 }; 452 453 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 454 NULL, 0); 455 } 456 457 /** 458 * Unregister BPHY interrupt handler 459 * 460 * @param dev_id 461 * The identifier of the device 462 * @param irq_num 463 * Zero-based interrupt number used during registration 464 * 465 * @return 466 * Returns 0 on success, negative error code otherwise 467 */ 468 static __rte_always_inline int 469 rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num) 470 { 471 struct cnxk_bphy_irq_info info = { 472 .irq_num = irq_num, 473 }; 474 struct cnxk_bphy_irq_msg msg = { 475 .type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER, 476 .data = &info 477 }; 478 479 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 480 NULL, 0); 481 } 482 483 /** 484 * Obtain BPHY memory 485 * 486 * @param dev_id 487 * The identifier of the device 488 * @param mem 489 * Memory structure which will be filled for memory access 490 * 491 * @return 492 * Returns 0 on success, negative error code otherwise 493 */ 494 static __rte_always_inline int 495 rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem) 496 { 497 struct cnxk_bphy_irq_msg msg = { 498 .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET, 499 }; 500 501 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 502 mem, sizeof(*mem)); 503 } 504 505 /** 506 * Obtain NPA PF func 507 * 508 * @param dev_id 509 * The identifier of the device 510 * @param pf_func 511 * NPA PF function to obtain 512 * 513 * @return 514 * Returns 0 on success, negative error code otherwise 515 */ 516 static __rte_always_inline int 517 rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func) 518 { 519 struct cnxk_bphy_irq_msg msg = { 520 .type = CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC, 521 }; 522 523 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 524 pf_func, sizeof(*pf_func)); 525 } 526 527 /** 528 * Obtain SSO PF func 529 * 530 * @param dev_id 531 * The identifier of the device 532 * @param pf_func 533 * SSO PF function to obtain 534 * 535 * @return 536 * Returns 0 on success, negative error code otherwise 537 */ 538 static __rte_always_inline int 539 rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func) 540 { 541 struct cnxk_bphy_irq_msg msg = { 542 .type = CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC, 543 }; 544 545 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg, 546 pf_func, sizeof(*pf_func)); 547 } 548 549 /** 550 * Obtain link information 551 * 552 * @param dev_id 553 * The identifier of the device 554 * @param lmac 555 * LMAC number for operation 556 * @param info 557 * Link information structure 558 * 559 * @return 560 * Returns 0 on success, negative error code otherwise 561 */ 562 static __rte_always_inline int 563 rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac, 564 struct cnxk_bphy_cgx_msg_link_info *info) 565 { 566 struct cnxk_bphy_cgx_msg msg = { 567 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, 568 }; 569 570 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, info, sizeof(*info)); 571 } 572 573 /** 574 * Disable loopback mode for an interface 575 * 576 * @param dev_id 577 * The identifier of the device 578 * @param lmac 579 * LMAC number for operation 580 * 581 * @return 582 * Returns 0 on success, negative error code otherwise 583 */ 584 static __rte_always_inline int 585 rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac) 586 { 587 struct cnxk_bphy_cgx_msg msg = { 588 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, 589 }; 590 591 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 592 } 593 594 /** 595 * Enable loopback mode for an interface 596 * 597 * @param dev_id 598 * The identifier of the device 599 * @param lmac 600 * LMAC number for operation 601 * 602 * @return 603 * Returns 0 on success, negative error code otherwise 604 */ 605 static __rte_always_inline int 606 rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac) 607 { 608 struct cnxk_bphy_cgx_msg msg = { 609 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE, 610 }; 611 612 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 613 } 614 615 /** 616 * Disable PTP on RX path 617 * 618 * @param dev_id 619 * The identifier of the device 620 * @param lmac 621 * LMAC number for operation 622 * 623 * @return 624 * Returns 0 on success, negative error code otherwise 625 */ 626 static __rte_always_inline int 627 rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac) 628 { 629 struct cnxk_bphy_cgx_msg msg = { 630 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE, 631 }; 632 633 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 634 } 635 636 /** 637 * Enable PTP on RX path 638 * 639 * @param dev_id 640 * The identifier of the device 641 * @param lmac 642 * LMAC number for operation 643 * 644 * @return 645 * Returns 0 on success, negative error code otherwise 646 */ 647 static __rte_always_inline int 648 rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac) 649 { 650 struct cnxk_bphy_cgx_msg msg = { 651 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE, 652 }; 653 654 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 655 } 656 657 /** 658 * Set link mode for a CGX 659 * 660 * @param dev_id 661 * The identifier of the device 662 * @param lmac 663 * LMAC number for operation 664 * @param mode 665 * Link mode to set 666 * 667 * @return 668 * Returns 0 on success, negative error code otherwise 669 */ 670 static __rte_always_inline int 671 rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac, 672 struct cnxk_bphy_cgx_msg_link_mode *mode) 673 { 674 struct cnxk_bphy_cgx_msg msg = { 675 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE, 676 .data = mode, 677 }; 678 679 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 680 } 681 682 /** 683 * Set link state for a CGX 684 * 685 * @param dev_id 686 * The identifier of the device 687 * @param lmac 688 * LMAC number for operation 689 * @param state 690 * Link state to set 691 * 692 * @return 693 * Returns 0 on success, negative error code otherwise 694 */ 695 static __rte_always_inline int 696 rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, 697 struct cnxk_bphy_cgx_msg_set_link_state *state) 698 { 699 struct cnxk_bphy_cgx_msg msg = { 700 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE, 701 .data = state, 702 }; 703 704 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 705 } 706 707 /** 708 * Start CGX 709 * 710 * @param dev_id 711 * The identifier of the device 712 * @param lmac 713 * LMAC number for operation 714 * 715 * @return 716 * Returns 0 on success, negative error code otherwise 717 */ 718 static __rte_always_inline int 719 rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac) 720 { 721 struct cnxk_bphy_cgx_msg msg = { 722 .type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX, 723 }; 724 725 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 726 } 727 728 /** 729 * Stop CGX 730 * 731 * @param dev_id 732 * The identifier of the device 733 * @param lmac 734 * LMAC number for operation 735 * 736 * @return 737 * Returns 0 on success, negative error code otherwise 738 */ 739 static __rte_always_inline int 740 rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac) 741 { 742 struct cnxk_bphy_cgx_msg msg = { 743 .type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX, 744 }; 745 746 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 747 } 748 749 /** 750 * Get supported list FEC mode 751 * 752 * @param dev_id 753 * The identifier of the device 754 * @param lmac 755 * LMAC number for operation 756 * @param fec 757 * FEC structure which holds information 758 * 759 * @return 760 * Returns 0 on success, negative error code otherwise 761 */ 762 static __rte_always_inline int 763 rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac, 764 enum cnxk_bphy_cgx_eth_link_fec *fec) 765 { 766 struct cnxk_bphy_cgx_msg msg = { 767 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC, 768 }; 769 770 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, fec, sizeof(*fec)); 771 } 772 773 /** 774 * Set FEC mode for a device 775 * 776 * @param dev_id 777 * The identifier of the device 778 * @param lmac 779 * LMAC number for operation 780 * @param fec 781 * FEC structure which holds information to set 782 * 783 * @return 784 * Returns 0 on success, negative error code otherwise 785 */ 786 static __rte_always_inline int 787 rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac, 788 enum cnxk_bphy_cgx_eth_link_fec fec) 789 { 790 struct cnxk_bphy_cgx_msg msg = { 791 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_FEC, 792 .data = &fec, 793 }; 794 795 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 796 } 797 798 /** 799 * Switch from eCPRI to CPRI and change 800 * 801 * @param dev_id 802 * The identifier of the device 803 * @param lmac 804 * LMAC number for operation 805 * @param mode 806 * CPRI structure which holds configuration data 807 * 808 * @return 809 * Returns 0 on success, negative error code otherwise 810 */ 811 static __rte_always_inline int 812 rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac, 813 struct cnxk_bphy_cgx_msg_cpri_mode_change *mode) 814 { 815 struct cnxk_bphy_cgx_msg msg = { 816 .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE, 817 .data = mode, 818 }; 819 820 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 821 } 822 823 /** 824 * Enable TX for SERDES configured in CPRI mode 825 * 826 * @param dev_id 827 * The identifier of the device 828 * @param lmac 829 * LMAC number for operation 830 * @param mode 831 * CPRI TX control structure holding control data 832 * 833 * @return 834 * Returns 0 on success, negative error code otherwise 835 */ 836 static __rte_always_inline int 837 rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac, 838 struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *mode) 839 { 840 struct cnxk_bphy_cgx_msg msg = { 841 .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL, 842 .data = mode, 843 }; 844 845 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 846 } 847 848 /** 849 * CPRI misc settings 850 * 851 * @param dev_id 852 * The identifier of the device 853 * @param lmac 854 * LMAC number for operation 855 * @param mode 856 * CPRI settings holding misc control data 857 * 858 * @return 859 * Returns 0 on success, negative error code otherwise 860 */ 861 static __rte_always_inline int 862 rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac, 863 struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode) 864 { 865 struct cnxk_bphy_cgx_msg msg = { 866 .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC, 867 .data = mode, 868 }; 869 870 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0); 871 } 872 873 /** 874 * Obtain NPA PF func 875 * 876 * @param pf_func 877 * Address of an NPA PF and function for NPA free pointer 878 * requests to obtain 879 * 880 * @return 881 * Returns 0 on success, negative error code otherwise 882 */ 883 int rte_pmd_bphy_npa_pf_func_get_rmt(uint16_t *pf_func); 884 885 /** 886 * Obtain SSO PF func 887 * 888 * @param pf_func 889 * Address SSO PF and function for SSO add-work requests to obtain 890 * 891 * @return 892 * Returns 0 on success, negative error code otherwise 893 */ 894 int rte_pmd_bphy_sso_pf_func_get_rmt(uint16_t *pf_func); 895 896 #ifdef __cplusplus 897 } 898 #endif 899 900 #endif /* _CNXK_BPHY_H_ */ 901