xref: /dpdk/drivers/net/zxdh/zxdh_msg.h (revision e77506397fc8005c5129e22e9e2d15d5876790fd)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2024 ZTE Corporation
3  */
4 
5 #ifndef ZXDH_MSG_H
6 #define ZXDH_MSG_H
7 
8 #include <stdint.h>
9 
10 #include <ethdev_driver.h>
11 
12 #define ZXDH_BAR0_INDEX                 0
13 #define ZXDH_CTRLCH_OFFSET              (0x2000)
14 #define ZXDH_MSG_CHAN_PFVFSHARE_OFFSET  (ZXDH_CTRLCH_OFFSET + 0x1000)
15 
16 #define ZXDH_MSIX_INTR_MSG_VEC_BASE   1
17 #define ZXDH_MSIX_INTR_MSG_VEC_NUM    3
18 #define ZXDH_MSIX_INTR_DTB_VEC        (ZXDH_MSIX_INTR_MSG_VEC_BASE + ZXDH_MSIX_INTR_MSG_VEC_NUM)
19 #define ZXDH_MSIX_INTR_DTB_VEC_NUM    1
20 #define ZXDH_INTR_NONQUE_NUM          (ZXDH_MSIX_INTR_MSG_VEC_NUM + ZXDH_MSIX_INTR_DTB_VEC_NUM + 1)
21 #define ZXDH_QUEUE_INTR_VEC_BASE      (ZXDH_MSIX_INTR_DTB_VEC + ZXDH_MSIX_INTR_DTB_VEC_NUM)
22 #define ZXDH_QUEUE_INTR_VEC_NUM       256
23 
24 #define ZXDH_BAR_MSG_POLLING_SPAN     100
25 #define ZXDH_BAR_MSG_POLL_CNT_PER_MS  (1 * 1000 / ZXDH_BAR_MSG_POLLING_SPAN)
26 #define ZXDH_BAR_MSG_POLL_CNT_PER_S   (1 * 1000 * 1000 / ZXDH_BAR_MSG_POLLING_SPAN)
27 #define ZXDH_BAR_MSG_TIMEOUT_TH       (10 * 1000 * 1000 / ZXDH_BAR_MSG_POLLING_SPAN)
28 
29 #define ZXDH_BAR_CHAN_MSG_SYNC         0
30 
31 #define ZXDH_BAR_MSG_ADDR_CHAN_INTERVAL  (2 * 1024) /* channel size */
32 #define ZXDH_BAR_MSG_PLAYLOAD_OFFSET     (sizeof(struct zxdh_bar_msg_header))
33 #define ZXDH_BAR_MSG_PAYLOAD_MAX_LEN     \
34 	(ZXDH_BAR_MSG_ADDR_CHAN_INTERVAL - sizeof(struct zxdh_bar_msg_header))
35 
36 enum ZXDH_DRIVER_TYPE {
37 	ZXDH_MSG_CHAN_END_MPF = 0,
38 	ZXDH_MSG_CHAN_END_PF,
39 	ZXDH_MSG_CHAN_END_VF,
40 	ZXDH_MSG_CHAN_END_RISC,
41 };
42 
43 enum ZXDH_MSG_VEC {
44 	ZXDH_MSIX_FROM_PFVF = ZXDH_MSIX_INTR_MSG_VEC_BASE,
45 	ZXDH_MSIX_FROM_MPF,
46 	ZXDH_MSIX_FROM_RISCV,
47 	ZXDH_MSG_VEC_NUM,
48 };
49 
50 enum ZXDH_BAR_MSG_RTN {
51 	ZXDH_BAR_MSG_OK = 0,
52 	ZXDH_BAR_MSG_ERR_MSGID,
53 	ZXDH_BAR_MSG_ERR_NULL,
54 	ZXDH_BAR_MSG_ERR_TYPE, /* Message type exception */
55 	ZXDH_BAR_MSG_ERR_MODULE, /* Module ID exception */
56 	ZXDH_BAR_MSG_ERR_BODY_NULL, /* Message body exception */
57 	ZXDH_BAR_MSG_ERR_LEN, /* Message length exception */
58 	ZXDH_BAR_MSG_ERR_TIME_OUT, /* Message sending length too long */
59 	ZXDH_BAR_MSG_ERR_NOT_READY, /* Abnormal message sending conditions*/
60 	ZXDH_BAR_MEG_ERR_NULL_FUNC, /* Empty receive processing function pointer*/
61 	ZXDH_BAR_MSG_ERR_REPEAT_REGISTER, /* Module duplicate registration*/
62 	ZXDH_BAR_MSG_ERR_UNGISTER, /* Repeated deregistration*/
63 	/*
64 	 * The sending interface parameter boundary structure pointer is empty
65 	 */
66 	ZXDH_BAR_MSG_ERR_NULL_PARA,
67 	ZXDH_BAR_MSG_ERR_REPSBUFF_LEN, /* The length of reps_buff is too short*/
68 	/*
69 	 * Unable to find the corresponding message processing function for this module
70 	 */
71 	ZXDH_BAR_MSG_ERR_MODULE_NOEXIST,
72 	/*
73 	 * The virtual address in the parameters passed in by the sending interface is empty
74 	 */
75 	ZXDH_BAR_MSG_ERR_VIRTADDR_NULL,
76 	ZXDH_BAR_MSG_ERR_REPLY, /* sync msg resp_error */
77 	ZXDH_BAR_MSG_ERR_MPF_NOT_SCANNED,
78 	ZXDH_BAR_MSG_ERR_KERNEL_READY,
79 	ZXDH_BAR_MSG_ERR_USR_RET_ERR,
80 	ZXDH_BAR_MSG_ERR_ERR_PCIEID,
81 	ZXDH_BAR_MSG_ERR_SOCKET, /* netlink sockte err */
82 };
83 
84 enum ZXDH_BAR_MODULE_ID {
85 	ZXDH_BAR_MODULE_DBG = 0, /* 0:  debug */
86 	ZXDH_BAR_MODULE_TBL,     /* 1:  resource table */
87 	ZXDH_BAR_MODULE_MISX,    /* 2:  config msix */
88 	ZXDH_BAR_MODULE_SDA,     /* 3: */
89 	ZXDH_BAR_MODULE_RDMA,    /* 4: */
90 	ZXDH_BAR_MODULE_DEMO,    /* 5:  channel test */
91 	ZXDH_BAR_MODULE_SMMU,    /* 6: */
92 	ZXDH_BAR_MODULE_MAC,     /* 7:  mac rx/tx stats */
93 	ZXDH_BAR_MODULE_VDPA,    /* 8:  vdpa live migration */
94 	ZXDH_BAR_MODULE_VQM,     /* 9:  vqm live migration */
95 	ZXDH_BAR_MODULE_NP,      /* 10: vf msg callback np */
96 	ZXDH_BAR_MODULE_VPORT,   /* 11: get vport */
97 	ZXDH_BAR_MODULE_BDF,     /* 12: get bdf */
98 	ZXDH_BAR_MODULE_RISC_READY, /* 13: */
99 	ZXDH_BAR_MODULE_REVERSE,    /* 14: byte stream reverse */
100 	ZXDH_BAR_MDOULE_NVME,       /* 15: */
101 	ZXDH_BAR_MDOULE_NPSDK,      /* 16: */
102 	ZXDH_BAR_MODULE_NP_TODO,    /* 17: */
103 	ZXDH_MODULE_BAR_MSG_TO_PF,  /* 18: */
104 	ZXDH_MODULE_BAR_MSG_TO_VF,  /* 19: */
105 
106 	ZXDH_MODULE_FLASH = 32,
107 	ZXDH_BAR_MODULE_OFFSET_GET = 33,
108 	ZXDH_BAR_EVENT_OVS_WITH_VCB = 36,
109 
110 	ZXDH_BAR_MSG_MODULE_NUM = 100,
111 };
112 
113 enum ZXDH_RES_TBL_FILED {
114 	ZXDH_TBL_FIELD_PCIEID     = 0,
115 	ZXDH_TBL_FIELD_BDF        = 1,
116 	ZXDH_TBL_FIELD_MSGCH      = 2,
117 	ZXDH_TBL_FIELD_DATACH     = 3,
118 	ZXDH_TBL_FIELD_VPORT      = 4,
119 	ZXDH_TBL_FIELD_PNLID      = 5,
120 	ZXDH_TBL_FIELD_PHYPORT    = 6,
121 	ZXDH_TBL_FIELD_SERDES_NUM = 7,
122 	ZXDH_TBL_FIELD_NP_PORT    = 8,
123 	ZXDH_TBL_FIELD_SPEED      = 9,
124 	ZXDH_TBL_FIELD_HASHID     = 10,
125 	ZXDH_TBL_FIELD_NON,
126 };
127 
128 enum ZXDH_TBL_MSG_TYPE {
129 	ZXDH_TBL_TYPE_READ,
130 	ZXDH_TBL_TYPE_WRITE,
131 	ZXDH_TBL_TYPE_NON,
132 };
133 
134 struct zxdh_msix_para {
135 	uint16_t pcie_id;
136 	uint16_t vector_risc;
137 	uint16_t vector_pfvf;
138 	uint16_t vector_mpf;
139 	uint64_t virt_addr;
140 	uint16_t driver_type; /* refer to DRIVER_TYPE */
141 };
142 
143 struct zxdh_msix_msg {
144 	uint16_t pcie_id;
145 	uint16_t vector_risc;
146 	uint16_t vector_pfvf;
147 	uint16_t vector_mpf;
148 };
149 
150 struct zxdh_pci_bar_msg {
151 	uint64_t virt_addr; /* bar addr */
152 	void    *payload_addr;
153 	uint16_t payload_len;
154 	uint16_t emec;
155 	uint16_t src; /* refer to BAR_DRIVER_TYPE */
156 	uint16_t dst; /* refer to BAR_DRIVER_TYPE */
157 	uint16_t module_id;
158 	uint16_t src_pcieid;
159 	uint16_t dst_pcieid;
160 	uint16_t usr;
161 };
162 
163 struct __rte_packed_begin zxdh_bar_msix_reps {
164 	uint16_t pcie_id;
165 	uint16_t check;
166 	uint16_t vport;
167 	uint16_t rsv;
168 } __rte_packed_end;
169 
170 struct __rte_packed_begin zxdh_bar_offset_reps {
171 	uint16_t check;
172 	uint16_t rsv;
173 	uint32_t offset;
174 	uint32_t length;
175 } __rte_packed_end;
176 
177 struct __rte_packed_begin zxdh_bar_recv_msg {
178 	uint8_t reps_ok;
179 	uint16_t reps_len;
180 	uint8_t rsv;
181 	union __rte_packed_begin {
182 		struct zxdh_bar_msix_reps msix_reps;
183 		struct zxdh_bar_offset_reps offset_reps;
184 	} __rte_packed_end;
185 } __rte_packed_end;
186 
187 struct zxdh_msg_recviver_mem {
188 	void *recv_buffer; /* first 4B is head, followed by payload */
189 	uint64_t buffer_len;
190 };
191 
192 struct zxdh_bar_msg_header {
193 	uint8_t valid : 1; /* used by __bar_chan_msg_valid_set/get */
194 	uint8_t sync  : 1;
195 	uint8_t emec  : 1; /* emergency */
196 	uint8_t ack   : 1; /* ack msg */
197 	uint8_t poll  : 1;
198 	uint8_t usr   : 1;
199 	uint8_t rsv;
200 	uint16_t module_id;
201 	uint16_t len;
202 	uint16_t msg_id;
203 	uint16_t src_pcieid;
204 	uint16_t dst_pcieid; /* used in PF-->VF */
205 };
206 
207 typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len,
208 		void *reps_buffer, uint16_t *reps_len, void *dev);
209 
210 int zxdh_msg_chan_init(void);
211 int zxdh_bar_msg_chan_exit(void);
212 int zxdh_msg_chan_hwlock_init(struct rte_eth_dev *dev);
213 
214 int zxdh_msg_chan_enable(struct rte_eth_dev *dev);
215 int zxdh_bar_chan_sync_msg_send(struct zxdh_pci_bar_msg *in,
216 		struct zxdh_msg_recviver_mem *result);
217 
218 int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev);
219 
220 #endif /* ZXDH_MSG_H */
221