xref: /dpdk/drivers/net/virtio/virtio_pci.h (revision bd03d3f1e4f1734c70bf6be32cdeb5e3ae6fa611)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2014 Intel Corporation
3  */
4 
5 #ifndef _VIRTIO_PCI_H_
6 #define _VIRTIO_PCI_H_
7 
8 #include <stdint.h>
9 #include <stdbool.h>
10 
11 #include <rte_pci.h>
12 #include <rte_bus_pci.h>
13 #include <rte_ethdev_driver.h>
14 
15 struct virtqueue;
16 struct virtnet_ctl;
17 
18 /* VirtIO PCI vendor/device ID. */
19 #define VIRTIO_PCI_VENDORID     0x1AF4
20 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000
21 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041
22 
23 /* VirtIO ABI version, this must match exactly. */
24 #define VIRTIO_PCI_ABI_VERSION 0
25 
26 /*
27  * VirtIO Header, located in BAR 0.
28  */
29 #define VIRTIO_PCI_HOST_FEATURES  0  /* host's supported features (32bit, RO)*/
30 #define VIRTIO_PCI_GUEST_FEATURES 4  /* guest's supported features (32, RW) */
31 #define VIRTIO_PCI_QUEUE_PFN      8  /* physical address of VQ (32, RW) */
32 #define VIRTIO_PCI_QUEUE_NUM      12 /* number of ring entries (16, RO) */
33 #define VIRTIO_PCI_QUEUE_SEL      14 /* current VQ selection (16, RW) */
34 #define VIRTIO_PCI_QUEUE_NOTIFY   16 /* notify host regarding VQ (16, RW) */
35 #define VIRTIO_PCI_STATUS         18 /* device status register (8, RW) */
36 #define VIRTIO_PCI_ISR		  19 /* interrupt status register, reading
37 				      * also clears the register (8, RO) */
38 /* Only if MSIX is enabled: */
39 #define VIRTIO_MSI_CONFIG_VECTOR  20 /* configuration change vector (16, RW) */
40 #define VIRTIO_MSI_QUEUE_VECTOR	  22 /* vector for selected VQ notifications
41 				      (16, RW) */
42 
43 /* The bit of the ISR which indicates a device has an interrupt. */
44 #define VIRTIO_PCI_ISR_INTR   0x1
45 /* The bit of the ISR which indicates a device configuration change. */
46 #define VIRTIO_PCI_ISR_CONFIG 0x2
47 /* Vector value used to disable MSI for queue. */
48 #define VIRTIO_MSI_NO_VECTOR 0xFFFF
49 
50 /* VirtIO device IDs. */
51 #define VIRTIO_ID_NETWORK  0x01
52 #define VIRTIO_ID_BLOCK    0x02
53 #define VIRTIO_ID_CONSOLE  0x03
54 #define VIRTIO_ID_ENTROPY  0x04
55 #define VIRTIO_ID_BALLOON  0x05
56 #define VIRTIO_ID_IOMEMORY 0x06
57 #define VIRTIO_ID_9P       0x09
58 
59 /* Status byte for guest to report progress. */
60 #define VIRTIO_CONFIG_STATUS_RESET     0x00
61 #define VIRTIO_CONFIG_STATUS_ACK       0x01
62 #define VIRTIO_CONFIG_STATUS_DRIVER    0x02
63 #define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04
64 #define VIRTIO_CONFIG_STATUS_FEATURES_OK 0x08
65 #define VIRTIO_CONFIG_STATUS_FAILED    0x80
66 
67 /*
68  * Each virtqueue indirect descriptor list must be physically contiguous.
69  * To allow us to malloc(9) each list individually, limit the number
70  * supported to what will fit in one page. With 4KB pages, this is a limit
71  * of 256 descriptors. If there is ever a need for more, we can switch to
72  * contigmalloc(9) for the larger allocations, similar to what
73  * bus_dmamem_alloc(9) does.
74  *
75  * Note the sizeof(struct vring_desc) is 16 bytes.
76  */
77 #define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16))
78 
79 /* The feature bitmap for virtio net */
80 #define VIRTIO_NET_F_CSUM	0	/* Host handles pkts w/ partial csum */
81 #define VIRTIO_NET_F_GUEST_CSUM	1	/* Guest handles pkts w/ partial csum */
82 #define VIRTIO_NET_F_MTU	3	/* Initial MTU advice. */
83 #define VIRTIO_NET_F_MAC	5	/* Host has given MAC address. */
84 #define VIRTIO_NET_F_GUEST_TSO4	7	/* Guest can handle TSOv4 in. */
85 #define VIRTIO_NET_F_GUEST_TSO6	8	/* Guest can handle TSOv6 in. */
86 #define VIRTIO_NET_F_GUEST_ECN	9	/* Guest can handle TSO[6] w/ ECN in. */
87 #define VIRTIO_NET_F_GUEST_UFO	10	/* Guest can handle UFO in. */
88 #define VIRTIO_NET_F_HOST_TSO4	11	/* Host can handle TSOv4 in. */
89 #define VIRTIO_NET_F_HOST_TSO6	12	/* Host can handle TSOv6 in. */
90 #define VIRTIO_NET_F_HOST_ECN	13	/* Host can handle TSO[6] w/ ECN in. */
91 #define VIRTIO_NET_F_HOST_UFO	14	/* Host can handle UFO in. */
92 #define VIRTIO_NET_F_MRG_RXBUF	15	/* Host can merge receive buffers. */
93 #define VIRTIO_NET_F_STATUS	16	/* virtio_net_config.status available */
94 #define VIRTIO_NET_F_CTRL_VQ	17	/* Control channel available */
95 #define VIRTIO_NET_F_CTRL_RX	18	/* Control channel RX mode support */
96 #define VIRTIO_NET_F_CTRL_VLAN	19	/* Control channel VLAN filtering */
97 #define VIRTIO_NET_F_CTRL_RX_EXTRA 20	/* Extra RX mode control support */
98 #define VIRTIO_NET_F_GUEST_ANNOUNCE 21	/* Guest can announce device on the
99 					 * network */
100 #define VIRTIO_NET_F_MQ		22	/* Device supports Receive Flow
101 					 * Steering */
102 #define VIRTIO_NET_F_CTRL_MAC_ADDR 23	/* Set MAC address */
103 
104 /* Do we get callbacks when the ring is completely used, even if we've
105  * suppressed them? */
106 #define VIRTIO_F_NOTIFY_ON_EMPTY	24
107 
108 /* Can the device handle any descriptor layout? */
109 #define VIRTIO_F_ANY_LAYOUT		27
110 
111 /* We support indirect buffer descriptors */
112 #define VIRTIO_RING_F_INDIRECT_DESC	28
113 
114 #define VIRTIO_F_VERSION_1		32
115 #define VIRTIO_F_IOMMU_PLATFORM	33
116 #define VIRTIO_F_RING_PACKED		34
117 
118 /*
119  * Some VirtIO feature bits (currently bits 28 through 31) are
120  * reserved for the transport being used (eg. virtio_ring), the
121  * rest are per-device feature bits.
122  */
123 #define VIRTIO_TRANSPORT_F_START 28
124 #define VIRTIO_TRANSPORT_F_END   34
125 
126 /*
127  * Inorder feature indicates that all buffers are used by the device
128  * in the same order in which they have been made available.
129  */
130 #define VIRTIO_F_IN_ORDER 35
131 
132 /* The Guest publishes the used index for which it expects an interrupt
133  * at the end of the avail ring. Host should ignore the avail->flags field. */
134 /* The Host publishes the avail index for which it expects a kick
135  * at the end of the used ring. Guest should ignore the used->flags field. */
136 #define VIRTIO_RING_F_EVENT_IDX		29
137 
138 #define VIRTIO_NET_S_LINK_UP	1	/* Link is up */
139 #define VIRTIO_NET_S_ANNOUNCE	2	/* Announcement is needed */
140 
141 /*
142  * Maximum number of virtqueues per device.
143  */
144 #define VIRTIO_MAX_VIRTQUEUE_PAIRS 8
145 #define VIRTIO_MAX_VIRTQUEUES (VIRTIO_MAX_VIRTQUEUE_PAIRS * 2 + 1)
146 
147 /* Common configuration */
148 #define VIRTIO_PCI_CAP_COMMON_CFG	1
149 /* Notifications */
150 #define VIRTIO_PCI_CAP_NOTIFY_CFG	2
151 /* ISR Status */
152 #define VIRTIO_PCI_CAP_ISR_CFG		3
153 /* Device specific configuration */
154 #define VIRTIO_PCI_CAP_DEVICE_CFG	4
155 /* PCI configuration access */
156 #define VIRTIO_PCI_CAP_PCI_CFG		5
157 
158 /* This is the PCI capability header: */
159 struct virtio_pci_cap {
160 	uint8_t cap_vndr;		/* Generic PCI field: PCI_CAP_ID_VNDR */
161 	uint8_t cap_next;		/* Generic PCI field: next ptr. */
162 	uint8_t cap_len;		/* Generic PCI field: capability length */
163 	uint8_t cfg_type;		/* Identifies the structure. */
164 	uint8_t bar;			/* Where to find it. */
165 	uint8_t padding[3];		/* Pad to full dword. */
166 	uint32_t offset;		/* Offset within bar. */
167 	uint32_t length;		/* Length of the structure, in bytes. */
168 };
169 
170 struct virtio_pci_notify_cap {
171 	struct virtio_pci_cap cap;
172 	uint32_t notify_off_multiplier;	/* Multiplier for queue_notify_off. */
173 };
174 
175 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
176 struct virtio_pci_common_cfg {
177 	/* About the whole device. */
178 	uint32_t device_feature_select;	/* read-write */
179 	uint32_t device_feature;	/* read-only */
180 	uint32_t guest_feature_select;	/* read-write */
181 	uint32_t guest_feature;		/* read-write */
182 	uint16_t msix_config;		/* read-write */
183 	uint16_t num_queues;		/* read-only */
184 	uint8_t device_status;		/* read-write */
185 	uint8_t config_generation;	/* read-only */
186 
187 	/* About a specific virtqueue. */
188 	uint16_t queue_select;		/* read-write */
189 	uint16_t queue_size;		/* read-write, power of 2. */
190 	uint16_t queue_msix_vector;	/* read-write */
191 	uint16_t queue_enable;		/* read-write */
192 	uint16_t queue_notify_off;	/* read-only */
193 	uint32_t queue_desc_lo;		/* read-write */
194 	uint32_t queue_desc_hi;		/* read-write */
195 	uint32_t queue_avail_lo;	/* read-write */
196 	uint32_t queue_avail_hi;	/* read-write */
197 	uint32_t queue_used_lo;		/* read-write */
198 	uint32_t queue_used_hi;		/* read-write */
199 };
200 
201 struct virtio_hw;
202 
203 struct virtio_pci_ops {
204 	void (*read_dev_cfg)(struct virtio_hw *hw, size_t offset,
205 			     void *dst, int len);
206 	void (*write_dev_cfg)(struct virtio_hw *hw, size_t offset,
207 			      const void *src, int len);
208 
209 	uint8_t (*get_status)(struct virtio_hw *hw);
210 	void    (*set_status)(struct virtio_hw *hw, uint8_t status);
211 
212 	uint64_t (*get_features)(struct virtio_hw *hw);
213 	void     (*set_features)(struct virtio_hw *hw, uint64_t features);
214 
215 	uint8_t (*get_isr)(struct virtio_hw *hw);
216 
217 	uint16_t (*set_config_irq)(struct virtio_hw *hw, uint16_t vec);
218 
219 	uint16_t (*set_queue_irq)(struct virtio_hw *hw, struct virtqueue *vq,
220 			uint16_t vec);
221 
222 	uint16_t (*get_queue_num)(struct virtio_hw *hw, uint16_t queue_id);
223 	int (*setup_queue)(struct virtio_hw *hw, struct virtqueue *vq);
224 	void (*del_queue)(struct virtio_hw *hw, struct virtqueue *vq);
225 	void (*notify_queue)(struct virtio_hw *hw, struct virtqueue *vq);
226 };
227 
228 struct virtio_net_config;
229 
230 struct virtio_hw {
231 	struct virtnet_ctl *cvq;
232 	uint64_t    req_guest_features;
233 	uint64_t    guest_features;
234 	uint32_t    max_queue_pairs;
235 	bool        started;
236 	uint16_t	max_mtu;
237 	uint16_t    vtnet_hdr_size;
238 	uint8_t	    vlan_strip;
239 	uint8_t	    use_msix;
240 	uint8_t     modern;
241 	uint8_t     use_simple_rx;
242 	uint8_t     use_inorder_rx;
243 	uint8_t     use_inorder_tx;
244 	bool        has_tx_offload;
245 	bool        has_rx_offload;
246 	uint16_t    port_id;
247 	uint8_t     mac_addr[ETHER_ADDR_LEN];
248 	uint32_t    notify_off_multiplier;
249 	uint8_t     *isr;
250 	uint16_t    *notify_base;
251 	struct virtio_pci_common_cfg *common_cfg;
252 	struct virtio_net_config *dev_cfg;
253 	void	    *virtio_user_dev;
254 	/*
255 	 * App management thread and virtio interrupt handler thread
256 	 * both can change device state, this lock is meant to avoid
257 	 * such a contention.
258 	 */
259 	rte_spinlock_t state_lock;
260 	struct rte_mbuf **inject_pkts;
261 	bool        opened;
262 
263 	struct virtqueue **vqs;
264 };
265 
266 
267 /*
268  * While virtio_hw is stored in shared memory, this structure stores
269  * some infos that may vary in the multiple process model locally.
270  * For example, the vtpci_ops pointer.
271  */
272 struct virtio_hw_internal {
273 	const struct virtio_pci_ops *vtpci_ops;
274 	struct rte_pci_ioport io;
275 };
276 
277 #define VTPCI_OPS(hw)	(virtio_hw_internal[(hw)->port_id].vtpci_ops)
278 #define VTPCI_IO(hw)	(&virtio_hw_internal[(hw)->port_id].io)
279 
280 extern struct virtio_hw_internal virtio_hw_internal[RTE_MAX_ETHPORTS];
281 
282 
283 /*
284  * This structure is just a reference to read
285  * net device specific config space; it just a chodu structure
286  *
287  */
288 struct virtio_net_config {
289 	/* The config defining mac address (if VIRTIO_NET_F_MAC) */
290 	uint8_t    mac[ETHER_ADDR_LEN];
291 	/* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */
292 	uint16_t   status;
293 	uint16_t   max_virtqueue_pairs;
294 	uint16_t   mtu;
295 } __attribute__((packed));
296 
297 /*
298  * How many bits to shift physical queue address written to QUEUE_PFN.
299  * 12 is historical, and due to x86 page size.
300  */
301 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
302 
303 /* The alignment to use between consumer and producer parts of vring. */
304 #define VIRTIO_PCI_VRING_ALIGN 4096
305 
306 enum virtio_msix_status {
307 	VIRTIO_MSIX_NONE = 0,
308 	VIRTIO_MSIX_DISABLED = 1,
309 	VIRTIO_MSIX_ENABLED = 2
310 };
311 
312 static inline int
313 vtpci_with_feature(struct virtio_hw *hw, uint64_t bit)
314 {
315 	return (hw->guest_features & (1ULL << bit)) != 0;
316 }
317 
318 static inline int
319 vtpci_packed_queue(struct virtio_hw *hw)
320 {
321 	return vtpci_with_feature(hw, VIRTIO_F_RING_PACKED);
322 }
323 
324 /*
325  * Function declaration from virtio_pci.c
326  */
327 int vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw);
328 void vtpci_reset(struct virtio_hw *);
329 
330 void vtpci_reinit_complete(struct virtio_hw *);
331 
332 uint8_t vtpci_get_status(struct virtio_hw *);
333 void vtpci_set_status(struct virtio_hw *, uint8_t);
334 
335 uint64_t vtpci_negotiate_features(struct virtio_hw *, uint64_t);
336 
337 void vtpci_write_dev_config(struct virtio_hw *, size_t, const void *, int);
338 
339 void vtpci_read_dev_config(struct virtio_hw *, size_t, void *, int);
340 
341 uint8_t vtpci_isr(struct virtio_hw *);
342 
343 enum virtio_msix_status vtpci_msix_detect(struct rte_pci_device *dev);
344 
345 extern const struct virtio_pci_ops legacy_ops;
346 extern const struct virtio_pci_ops modern_ops;
347 extern const struct virtio_pci_ops virtio_user_ops;
348 
349 #endif /* _VIRTIO_PCI_H_ */
350