1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2014 Intel Corporation 3 */ 4 5 #ifndef _VIRTIO_PCI_H_ 6 #define _VIRTIO_PCI_H_ 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include <rte_pci.h> 12 #include <bus_pci_driver.h> 13 #include <ethdev_driver.h> 14 15 #include "virtio.h" 16 17 struct virtqueue; 18 struct virtnet_ctl; 19 20 /* VirtIO PCI vendor/device ID. */ 21 #define VIRTIO_PCI_VENDORID 0x1AF4 22 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000 23 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041 24 25 /* VirtIO ABI version, this must match exactly. */ 26 #define VIRTIO_PCI_ABI_VERSION 0 27 28 /* 29 * VirtIO Header, located in BAR 0. 30 */ 31 #define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/ 32 #define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */ 33 #define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */ 34 #define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */ 35 #define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */ 36 #define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */ 37 #define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */ 38 #define VIRTIO_PCI_ISR 19 /* interrupt status register, reading 39 * also clears the register (8, RO) */ 40 /* Only if MSIX is enabled: */ 41 #define VIRTIO_MSI_CONFIG_VECTOR 20 /* configuration change vector (16, RW) */ 42 #define VIRTIO_MSI_QUEUE_VECTOR 22 /* vector for selected VQ notifications 43 (16, RW) */ 44 45 /* Common configuration */ 46 #define VIRTIO_PCI_CAP_COMMON_CFG 1 47 /* Notifications */ 48 #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 49 /* ISR Status */ 50 #define VIRTIO_PCI_CAP_ISR_CFG 3 51 /* Device specific configuration */ 52 #define VIRTIO_PCI_CAP_DEVICE_CFG 4 53 /* PCI configuration access */ 54 #define VIRTIO_PCI_CAP_PCI_CFG 5 55 56 /* This is the PCI capability header: */ 57 struct virtio_pci_cap { 58 uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 59 uint8_t cap_next; /* Generic PCI field: next ptr. */ 60 uint8_t cap_len; /* Generic PCI field: capability length */ 61 uint8_t cfg_type; /* Identifies the structure. */ 62 uint8_t bar; /* Where to find it. */ 63 uint8_t padding[3]; /* Pad to full dword. */ 64 uint32_t offset; /* Offset within bar. */ 65 uint32_t length; /* Length of the structure, in bytes. */ 66 }; 67 68 struct virtio_pci_notify_cap { 69 struct virtio_pci_cap cap; 70 uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */ 71 }; 72 73 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ 74 struct virtio_pci_common_cfg { 75 /* About the whole device. */ 76 uint32_t device_feature_select; /* read-write */ 77 uint32_t device_feature; /* read-only */ 78 uint32_t guest_feature_select; /* read-write */ 79 uint32_t guest_feature; /* read-write */ 80 uint16_t msix_config; /* read-write */ 81 uint16_t num_queues; /* read-only */ 82 uint8_t device_status; /* read-write */ 83 uint8_t config_generation; /* read-only */ 84 85 /* About a specific virtqueue. */ 86 uint16_t queue_select; /* read-write */ 87 uint16_t queue_size; /* read-write, power of 2. */ 88 uint16_t queue_msix_vector; /* read-write */ 89 uint16_t queue_enable; /* read-write */ 90 uint16_t queue_notify_off; /* read-only */ 91 uint32_t queue_desc_lo; /* read-write */ 92 uint32_t queue_desc_hi; /* read-write */ 93 uint32_t queue_avail_lo; /* read-write */ 94 uint32_t queue_avail_hi; /* read-write */ 95 uint32_t queue_used_lo; /* read-write */ 96 uint32_t queue_used_hi; /* read-write */ 97 }; 98 99 enum virtio_msix_status { 100 VIRTIO_MSIX_NONE = 0, 101 VIRTIO_MSIX_DISABLED = 1, 102 VIRTIO_MSIX_ENABLED = 2 103 }; 104 105 struct virtio_pci_dev { 106 struct virtio_hw hw; 107 struct virtio_pci_common_cfg *common_cfg; 108 struct virtio_net_config *dev_cfg; 109 enum virtio_msix_status msix_status; 110 uint8_t *isr; 111 uint16_t *notify_base; 112 uint32_t notify_off_multiplier; 113 bool modern; 114 }; 115 116 #define virtio_pci_get_dev(hwp) container_of(hwp, struct virtio_pci_dev, hw) 117 118 struct virtio_pci_internal { 119 struct rte_pci_ioport io; 120 struct rte_pci_device *dev; 121 }; 122 123 extern struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS]; 124 125 #define VTPCI_IO(hw) (&virtio_pci_internal[(hw)->port_id].io) 126 #define VTPCI_DEV(hw) (virtio_pci_internal[(hw)->port_id].dev) 127 128 129 /* 130 * How many bits to shift physical queue address written to QUEUE_PFN. 131 * 12 is historical, and due to x86 page size. 132 */ 133 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 134 135 /* 136 * Function declaration from virtio_pci.c 137 */ 138 int vtpci_init(struct rte_pci_device *pci_dev, struct virtio_pci_dev *dev); 139 void vtpci_legacy_ioport_unmap(struct virtio_hw *hw); 140 int vtpci_legacy_ioport_map(struct virtio_hw *hw); 141 142 extern const struct virtio_ops legacy_ops; 143 extern const struct virtio_ops modern_ops; 144 145 #endif /* _VIRTIO_PCI_H_ */ 146