1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _VIRTIO_PCI_H_ 35 #define _VIRTIO_PCI_H_ 36 37 #include <stdint.h> 38 39 #include <rte_pci.h> 40 #include <rte_bus_pci.h> 41 #include <rte_ethdev.h> 42 43 struct virtqueue; 44 struct virtnet_ctl; 45 46 /* VirtIO PCI vendor/device ID. */ 47 #define VIRTIO_PCI_VENDORID 0x1AF4 48 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000 49 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041 50 51 /* VirtIO ABI version, this must match exactly. */ 52 #define VIRTIO_PCI_ABI_VERSION 0 53 54 /* 55 * VirtIO Header, located in BAR 0. 56 */ 57 #define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/ 58 #define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */ 59 #define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */ 60 #define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */ 61 #define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */ 62 #define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */ 63 #define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */ 64 #define VIRTIO_PCI_ISR 19 /* interrupt status register, reading 65 * also clears the register (8, RO) */ 66 /* Only if MSIX is enabled: */ 67 #define VIRTIO_MSI_CONFIG_VECTOR 20 /* configuration change vector (16, RW) */ 68 #define VIRTIO_MSI_QUEUE_VECTOR 22 /* vector for selected VQ notifications 69 (16, RW) */ 70 71 /* The bit of the ISR which indicates a device has an interrupt. */ 72 #define VIRTIO_PCI_ISR_INTR 0x1 73 /* The bit of the ISR which indicates a device configuration change. */ 74 #define VIRTIO_PCI_ISR_CONFIG 0x2 75 /* Vector value used to disable MSI for queue. */ 76 #define VIRTIO_MSI_NO_VECTOR 0xFFFF 77 78 /* VirtIO device IDs. */ 79 #define VIRTIO_ID_NETWORK 0x01 80 #define VIRTIO_ID_BLOCK 0x02 81 #define VIRTIO_ID_CONSOLE 0x03 82 #define VIRTIO_ID_ENTROPY 0x04 83 #define VIRTIO_ID_BALLOON 0x05 84 #define VIRTIO_ID_IOMEMORY 0x06 85 #define VIRTIO_ID_9P 0x09 86 87 /* Status byte for guest to report progress. */ 88 #define VIRTIO_CONFIG_STATUS_RESET 0x00 89 #define VIRTIO_CONFIG_STATUS_ACK 0x01 90 #define VIRTIO_CONFIG_STATUS_DRIVER 0x02 91 #define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04 92 #define VIRTIO_CONFIG_STATUS_FEATURES_OK 0x08 93 #define VIRTIO_CONFIG_STATUS_FAILED 0x80 94 95 /* 96 * Each virtqueue indirect descriptor list must be physically contiguous. 97 * To allow us to malloc(9) each list individually, limit the number 98 * supported to what will fit in one page. With 4KB pages, this is a limit 99 * of 256 descriptors. If there is ever a need for more, we can switch to 100 * contigmalloc(9) for the larger allocations, similar to what 101 * bus_dmamem_alloc(9) does. 102 * 103 * Note the sizeof(struct vring_desc) is 16 bytes. 104 */ 105 #define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16)) 106 107 /* The feature bitmap for virtio net */ 108 #define VIRTIO_NET_F_CSUM 0 /* Host handles pkts w/ partial csum */ 109 #define VIRTIO_NET_F_GUEST_CSUM 1 /* Guest handles pkts w/ partial csum */ 110 #define VIRTIO_NET_F_MTU 3 /* Initial MTU advice. */ 111 #define VIRTIO_NET_F_MAC 5 /* Host has given MAC address. */ 112 #define VIRTIO_NET_F_GUEST_TSO4 7 /* Guest can handle TSOv4 in. */ 113 #define VIRTIO_NET_F_GUEST_TSO6 8 /* Guest can handle TSOv6 in. */ 114 #define VIRTIO_NET_F_GUEST_ECN 9 /* Guest can handle TSO[6] w/ ECN in. */ 115 #define VIRTIO_NET_F_GUEST_UFO 10 /* Guest can handle UFO in. */ 116 #define VIRTIO_NET_F_HOST_TSO4 11 /* Host can handle TSOv4 in. */ 117 #define VIRTIO_NET_F_HOST_TSO6 12 /* Host can handle TSOv6 in. */ 118 #define VIRTIO_NET_F_HOST_ECN 13 /* Host can handle TSO[6] w/ ECN in. */ 119 #define VIRTIO_NET_F_HOST_UFO 14 /* Host can handle UFO in. */ 120 #define VIRTIO_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */ 121 #define VIRTIO_NET_F_STATUS 16 /* virtio_net_config.status available */ 122 #define VIRTIO_NET_F_CTRL_VQ 17 /* Control channel available */ 123 #define VIRTIO_NET_F_CTRL_RX 18 /* Control channel RX mode support */ 124 #define VIRTIO_NET_F_CTRL_VLAN 19 /* Control channel VLAN filtering */ 125 #define VIRTIO_NET_F_CTRL_RX_EXTRA 20 /* Extra RX mode control support */ 126 #define VIRTIO_NET_F_GUEST_ANNOUNCE 21 /* Guest can announce device on the 127 * network */ 128 #define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow 129 * Steering */ 130 #define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */ 131 132 /* Do we get callbacks when the ring is completely used, even if we've 133 * suppressed them? */ 134 #define VIRTIO_F_NOTIFY_ON_EMPTY 24 135 136 /* Can the device handle any descriptor layout? */ 137 #define VIRTIO_F_ANY_LAYOUT 27 138 139 /* We support indirect buffer descriptors */ 140 #define VIRTIO_RING_F_INDIRECT_DESC 28 141 142 #define VIRTIO_F_VERSION_1 32 143 #define VIRTIO_F_IOMMU_PLATFORM 33 144 145 /* 146 * Some VirtIO feature bits (currently bits 28 through 31) are 147 * reserved for the transport being used (eg. virtio_ring), the 148 * rest are per-device feature bits. 149 */ 150 #define VIRTIO_TRANSPORT_F_START 28 151 #define VIRTIO_TRANSPORT_F_END 34 152 153 /* The Guest publishes the used index for which it expects an interrupt 154 * at the end of the avail ring. Host should ignore the avail->flags field. */ 155 /* The Host publishes the avail index for which it expects a kick 156 * at the end of the used ring. Guest should ignore the used->flags field. */ 157 #define VIRTIO_RING_F_EVENT_IDX 29 158 159 #define VIRTIO_NET_S_LINK_UP 1 /* Link is up */ 160 #define VIRTIO_NET_S_ANNOUNCE 2 /* Announcement is needed */ 161 162 /* 163 * Maximum number of virtqueues per device. 164 */ 165 #define VIRTIO_MAX_VIRTQUEUE_PAIRS 8 166 #define VIRTIO_MAX_VIRTQUEUES (VIRTIO_MAX_VIRTQUEUE_PAIRS * 2 + 1) 167 168 /* Common configuration */ 169 #define VIRTIO_PCI_CAP_COMMON_CFG 1 170 /* Notifications */ 171 #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 172 /* ISR Status */ 173 #define VIRTIO_PCI_CAP_ISR_CFG 3 174 /* Device specific configuration */ 175 #define VIRTIO_PCI_CAP_DEVICE_CFG 4 176 /* PCI configuration access */ 177 #define VIRTIO_PCI_CAP_PCI_CFG 5 178 179 /* This is the PCI capability header: */ 180 struct virtio_pci_cap { 181 uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 182 uint8_t cap_next; /* Generic PCI field: next ptr. */ 183 uint8_t cap_len; /* Generic PCI field: capability length */ 184 uint8_t cfg_type; /* Identifies the structure. */ 185 uint8_t bar; /* Where to find it. */ 186 uint8_t padding[3]; /* Pad to full dword. */ 187 uint32_t offset; /* Offset within bar. */ 188 uint32_t length; /* Length of the structure, in bytes. */ 189 }; 190 191 struct virtio_pci_notify_cap { 192 struct virtio_pci_cap cap; 193 uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */ 194 }; 195 196 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ 197 struct virtio_pci_common_cfg { 198 /* About the whole device. */ 199 uint32_t device_feature_select; /* read-write */ 200 uint32_t device_feature; /* read-only */ 201 uint32_t guest_feature_select; /* read-write */ 202 uint32_t guest_feature; /* read-write */ 203 uint16_t msix_config; /* read-write */ 204 uint16_t num_queues; /* read-only */ 205 uint8_t device_status; /* read-write */ 206 uint8_t config_generation; /* read-only */ 207 208 /* About a specific virtqueue. */ 209 uint16_t queue_select; /* read-write */ 210 uint16_t queue_size; /* read-write, power of 2. */ 211 uint16_t queue_msix_vector; /* read-write */ 212 uint16_t queue_enable; /* read-write */ 213 uint16_t queue_notify_off; /* read-only */ 214 uint32_t queue_desc_lo; /* read-write */ 215 uint32_t queue_desc_hi; /* read-write */ 216 uint32_t queue_avail_lo; /* read-write */ 217 uint32_t queue_avail_hi; /* read-write */ 218 uint32_t queue_used_lo; /* read-write */ 219 uint32_t queue_used_hi; /* read-write */ 220 }; 221 222 struct virtio_hw; 223 224 struct virtio_pci_ops { 225 void (*read_dev_cfg)(struct virtio_hw *hw, size_t offset, 226 void *dst, int len); 227 void (*write_dev_cfg)(struct virtio_hw *hw, size_t offset, 228 const void *src, int len); 229 void (*reset)(struct virtio_hw *hw); 230 231 uint8_t (*get_status)(struct virtio_hw *hw); 232 void (*set_status)(struct virtio_hw *hw, uint8_t status); 233 234 uint64_t (*get_features)(struct virtio_hw *hw); 235 void (*set_features)(struct virtio_hw *hw, uint64_t features); 236 237 uint8_t (*get_isr)(struct virtio_hw *hw); 238 239 uint16_t (*set_config_irq)(struct virtio_hw *hw, uint16_t vec); 240 241 uint16_t (*set_queue_irq)(struct virtio_hw *hw, struct virtqueue *vq, 242 uint16_t vec); 243 244 uint16_t (*get_queue_num)(struct virtio_hw *hw, uint16_t queue_id); 245 int (*setup_queue)(struct virtio_hw *hw, struct virtqueue *vq); 246 void (*del_queue)(struct virtio_hw *hw, struct virtqueue *vq); 247 void (*notify_queue)(struct virtio_hw *hw, struct virtqueue *vq); 248 }; 249 250 struct virtio_net_config; 251 252 struct virtio_hw { 253 struct virtnet_ctl *cvq; 254 uint64_t req_guest_features; 255 uint64_t guest_features; 256 uint32_t max_queue_pairs; 257 uint16_t started; 258 uint16_t max_mtu; 259 uint16_t vtnet_hdr_size; 260 uint8_t vlan_strip; 261 uint8_t use_msix; 262 uint8_t modern; 263 uint8_t use_simple_rx; 264 uint8_t use_simple_tx; 265 uint16_t port_id; 266 uint8_t mac_addr[ETHER_ADDR_LEN]; 267 uint32_t notify_off_multiplier; 268 uint8_t *isr; 269 uint16_t *notify_base; 270 struct virtio_pci_common_cfg *common_cfg; 271 struct virtio_net_config *dev_cfg; 272 void *virtio_user_dev; 273 274 struct virtqueue **vqs; 275 }; 276 277 278 /* 279 * While virtio_hw is stored in shared memory, this structure stores 280 * some infos that may vary in the multiple process model locally. 281 * For example, the vtpci_ops pointer. 282 */ 283 struct virtio_hw_internal { 284 const struct virtio_pci_ops *vtpci_ops; 285 struct rte_pci_ioport io; 286 }; 287 288 #define VTPCI_OPS(hw) (virtio_hw_internal[(hw)->port_id].vtpci_ops) 289 #define VTPCI_IO(hw) (&virtio_hw_internal[(hw)->port_id].io) 290 291 extern struct virtio_hw_internal virtio_hw_internal[RTE_MAX_ETHPORTS]; 292 293 294 /* 295 * This structure is just a reference to read 296 * net device specific config space; it just a chodu structure 297 * 298 */ 299 struct virtio_net_config { 300 /* The config defining mac address (if VIRTIO_NET_F_MAC) */ 301 uint8_t mac[ETHER_ADDR_LEN]; 302 /* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */ 303 uint16_t status; 304 uint16_t max_virtqueue_pairs; 305 uint16_t mtu; 306 } __attribute__((packed)); 307 308 /* 309 * How many bits to shift physical queue address written to QUEUE_PFN. 310 * 12 is historical, and due to x86 page size. 311 */ 312 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 313 314 /* The alignment to use between consumer and producer parts of vring. */ 315 #define VIRTIO_PCI_VRING_ALIGN 4096 316 317 static inline int 318 vtpci_with_feature(struct virtio_hw *hw, uint64_t bit) 319 { 320 return (hw->guest_features & (1ULL << bit)) != 0; 321 } 322 323 /* 324 * Function declaration from virtio_pci.c 325 */ 326 int vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw); 327 void vtpci_reset(struct virtio_hw *); 328 329 void vtpci_reinit_complete(struct virtio_hw *); 330 331 uint8_t vtpci_get_status(struct virtio_hw *); 332 void vtpci_set_status(struct virtio_hw *, uint8_t); 333 334 uint64_t vtpci_negotiate_features(struct virtio_hw *, uint64_t); 335 336 void vtpci_write_dev_config(struct virtio_hw *, size_t, const void *, int); 337 338 void vtpci_read_dev_config(struct virtio_hw *, size_t, void *, int); 339 340 uint8_t vtpci_isr(struct virtio_hw *); 341 342 extern const struct virtio_pci_ops legacy_ops; 343 extern const struct virtio_pci_ops modern_ops; 344 extern const struct virtio_pci_ops virtio_user_ops; 345 346 #endif /* _VIRTIO_PCI_H_ */ 347