1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _TXGBE_TYPE_H_ 7 #define _TXGBE_TYPE_H_ 8 9 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP 10 #define TXGBE_DCB_UP_MAX TXGBE_MAX_UP 11 #define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP 12 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 13 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 14 15 #define TXGBE_RX_HDR_SIZE 256 16 #define TXGBE_RX_BUF_SIZE 2048 17 18 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */ 19 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */ 20 #define TXGBE_NUM_POOL (64) 21 #define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 22 #define TXGBE_MAX_FTQF_FILTERS 128 23 #define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 24 #define TXGBE_MAX_UP 8 25 #define TXGBE_MAX_QP (128) 26 #define TXGBE_MAX_UTA 128 27 28 #define TXGBE_FDIR_INIT_DONE_POLL 10 29 #define TXGBE_FDIRCMD_CMD_POLL 10 30 #define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 31 #define TXGBE_SPI_TIMEOUT 10000 32 #define TXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 33 34 #define TXGBE_ALIGN 128 /* as intel did */ 35 36 #include "txgbe_status.h" 37 #include "txgbe_osdep.h" 38 #include "txgbe_devids.h" 39 40 struct txgbe_thermal_diode_data { 41 s16 temp; 42 s16 alarm_thresh; 43 s16 dalarm_thresh; 44 }; 45 46 struct txgbe_thermal_sensor_data { 47 struct txgbe_thermal_diode_data sensor[1]; 48 }; 49 50 /* Packet buffer allocation strategies */ 51 enum { 52 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 53 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 54 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 55 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 56 }; 57 58 /* Physical layer type */ 59 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0 60 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001 61 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002 62 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004 63 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008 64 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010 65 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020 66 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040 67 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080 68 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100 69 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200 70 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400 71 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800 72 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000 73 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000 74 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 75 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 76 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 77 78 /* Software ATR hash keys */ 79 #define TXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 80 #define TXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 81 82 /* Software ATR input stream values and masks */ 83 #define TXGBE_ATR_HASH_MASK 0x7fff 84 #define TXGBE_ATR_L3TYPE_MASK 0x4 85 #define TXGBE_ATR_L3TYPE_IPV4 0x0 86 #define TXGBE_ATR_L3TYPE_IPV6 0x4 87 #define TXGBE_ATR_L4TYPE_MASK 0x3 88 #define TXGBE_ATR_L4TYPE_UDP 0x1 89 #define TXGBE_ATR_L4TYPE_TCP 0x2 90 #define TXGBE_ATR_L4TYPE_SCTP 0x3 91 #define TXGBE_ATR_TUNNEL_MASK 0x10 92 #define TXGBE_ATR_TUNNEL_ANY 0x10 93 enum txgbe_atr_flow_type { 94 TXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 95 TXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 96 TXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 97 TXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 98 TXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 99 TXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 100 TXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 101 TXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 102 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 103 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 104 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 105 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 106 TXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 107 TXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 108 TXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 109 TXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 110 }; 111 112 /* Flow Director ATR input struct. */ 113 struct txgbe_atr_input { 114 /* 115 * Byte layout in order, all values with MSB first: 116 * 117 * vm_pool - 1 byte 118 * flow_type - 1 byte 119 * vlan_id - 2 bytes 120 * src_ip - 16 bytes 121 * inner_mac - 6 bytes 122 * cloud_mode - 2 bytes 123 * tni_vni - 4 bytes 124 * dst_ip - 16 bytes 125 * src_port - 2 bytes 126 * dst_port - 2 bytes 127 * flex_bytes - 2 bytes 128 * bkt_hash - 2 bytes 129 */ 130 u8 vm_pool; 131 u8 flow_type; 132 __be16 pkt_type; 133 __be32 dst_ip[4]; 134 __be32 src_ip[4]; 135 __be16 src_port; 136 __be16 dst_port; 137 __be16 flex_bytes; 138 __be16 bkt_hash; 139 }; 140 141 enum txgbe_eeprom_type { 142 txgbe_eeprom_unknown = 0, 143 txgbe_eeprom_spi, 144 txgbe_eeprom_flash, 145 txgbe_eeprom_none /* No NVM support */ 146 }; 147 148 enum txgbe_mac_type { 149 txgbe_mac_unknown = 0, 150 txgbe_mac_raptor, 151 txgbe_mac_raptor_vf, 152 txgbe_num_macs 153 }; 154 155 enum txgbe_phy_type { 156 txgbe_phy_unknown = 0, 157 txgbe_phy_none, 158 txgbe_phy_tn, 159 txgbe_phy_aq, 160 txgbe_phy_ext_1g_t, 161 txgbe_phy_cu_mtd, 162 txgbe_phy_cu_unknown, 163 txgbe_phy_qt, 164 txgbe_phy_xaui, 165 txgbe_phy_nl, 166 txgbe_phy_sfp_tyco_passive, 167 txgbe_phy_sfp_unknown_passive, 168 txgbe_phy_sfp_unknown_active, 169 txgbe_phy_sfp_avago, 170 txgbe_phy_sfp_ftl, 171 txgbe_phy_sfp_ftl_active, 172 txgbe_phy_sfp_unknown, 173 txgbe_phy_sfp_intel, 174 txgbe_phy_qsfp_unknown_passive, 175 txgbe_phy_qsfp_unknown_active, 176 txgbe_phy_qsfp_intel, 177 txgbe_phy_qsfp_unknown, 178 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */ 179 txgbe_phy_sgmii, 180 txgbe_phy_fw, 181 txgbe_phy_generic 182 }; 183 184 /* 185 * SFP+ module type IDs: 186 * 187 * ID Module Type 188 * ============= 189 * 0 SFP_DA_CU 190 * 1 SFP_SR 191 * 2 SFP_LR 192 * 3 SFP_DA_CU_CORE0 - chip-specific 193 * 4 SFP_DA_CU_CORE1 - chip-specific 194 * 5 SFP_SR/LR_CORE0 - chip-specific 195 * 6 SFP_SR/LR_CORE1 - chip-specific 196 */ 197 enum txgbe_sfp_type { 198 txgbe_sfp_type_unknown = 0, 199 txgbe_sfp_type_da_cu, 200 txgbe_sfp_type_sr, 201 txgbe_sfp_type_lr, 202 txgbe_sfp_type_da_cu_core0, 203 txgbe_sfp_type_da_cu_core1, 204 txgbe_sfp_type_srlr_core0, 205 txgbe_sfp_type_srlr_core1, 206 txgbe_sfp_type_da_act_lmt_core0, 207 txgbe_sfp_type_da_act_lmt_core1, 208 txgbe_sfp_type_1g_cu_core0, 209 txgbe_sfp_type_1g_cu_core1, 210 txgbe_sfp_type_1g_sx_core0, 211 txgbe_sfp_type_1g_sx_core1, 212 txgbe_sfp_type_1g_lx_core0, 213 txgbe_sfp_type_1g_lx_core1, 214 txgbe_sfp_type_not_present = 0xFFFE, 215 txgbe_sfp_type_not_known = 0xFFFF 216 }; 217 218 enum txgbe_media_type { 219 txgbe_media_type_unknown = 0, 220 txgbe_media_type_fiber, 221 txgbe_media_type_fiber_qsfp, 222 txgbe_media_type_copper, 223 txgbe_media_type_backplane, 224 txgbe_media_type_cx4, 225 txgbe_media_type_virtual 226 }; 227 228 /* Flow Control Settings */ 229 enum txgbe_fc_mode { 230 txgbe_fc_none = 0, 231 txgbe_fc_rx_pause, 232 txgbe_fc_tx_pause, 233 txgbe_fc_full, 234 txgbe_fc_default 235 }; 236 237 /* Smart Speed Settings */ 238 #define TXGBE_SMARTSPEED_MAX_RETRIES 3 239 enum txgbe_smart_speed { 240 txgbe_smart_speed_auto = 0, 241 txgbe_smart_speed_on, 242 txgbe_smart_speed_off 243 }; 244 245 /* PCI bus types */ 246 enum txgbe_bus_type { 247 txgbe_bus_type_unknown = 0, 248 txgbe_bus_type_pci, 249 txgbe_bus_type_pcix, 250 txgbe_bus_type_pci_express, 251 txgbe_bus_type_internal, 252 txgbe_bus_type_reserved 253 }; 254 255 /* PCI bus speeds */ 256 enum txgbe_bus_speed { 257 txgbe_bus_speed_unknown = 0, 258 txgbe_bus_speed_33 = 33, 259 txgbe_bus_speed_66 = 66, 260 txgbe_bus_speed_100 = 100, 261 txgbe_bus_speed_120 = 120, 262 txgbe_bus_speed_133 = 133, 263 txgbe_bus_speed_2500 = 2500, 264 txgbe_bus_speed_5000 = 5000, 265 txgbe_bus_speed_8000 = 8000, 266 txgbe_bus_speed_reserved 267 }; 268 269 /* PCI bus widths */ 270 enum txgbe_bus_width { 271 txgbe_bus_width_unknown = 0, 272 txgbe_bus_width_pcie_x1 = 1, 273 txgbe_bus_width_pcie_x2 = 2, 274 txgbe_bus_width_pcie_x4 = 4, 275 txgbe_bus_width_pcie_x8 = 8, 276 txgbe_bus_width_32 = 32, 277 txgbe_bus_width_64 = 64, 278 txgbe_bus_width_reserved 279 }; 280 281 struct txgbe_hw; 282 283 struct txgbe_addr_filter_info { 284 u32 num_mc_addrs; 285 u32 rar_used_count; 286 u32 mta_in_use; 287 u32 overflow_promisc; 288 bool user_set_promisc; 289 }; 290 291 /* Bus parameters */ 292 struct txgbe_bus_info { 293 s32 (*get_bus_info)(struct txgbe_hw *hw); 294 void (*set_lan_id)(struct txgbe_hw *hw); 295 296 enum txgbe_bus_speed speed; 297 enum txgbe_bus_width width; 298 enum txgbe_bus_type type; 299 300 u16 func; 301 u8 lan_id; 302 u16 instance_id; 303 }; 304 305 /* Flow control parameters */ 306 struct txgbe_fc_info { 307 u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */ 308 u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */ 309 u16 pause_time; /* Flow Control Pause timer */ 310 bool send_xon; /* Flow control send XON */ 311 bool strict_ieee; /* Strict IEEE mode */ 312 bool disable_fc_autoneg; /* Do not autonegotiate FC */ 313 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 314 enum txgbe_fc_mode current_mode; /* FC mode in effect */ 315 enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */ 316 }; 317 318 /* Statistics counters collected by the MAC */ 319 /* PB[] RxTx */ 320 struct txgbe_pb_stats { 321 u64 tx_pb_xon_packets; 322 u64 rx_pb_xon_packets; 323 u64 tx_pb_xoff_packets; 324 u64 rx_pb_xoff_packets; 325 u64 rx_pb_dropped; 326 u64 rx_pb_mbuf_alloc_errors; 327 u64 tx_pb_xon2off_packets; 328 }; 329 330 /* QP[] RxTx */ 331 struct txgbe_qp_stats { 332 u64 rx_qp_packets; 333 u64 tx_qp_packets; 334 u64 rx_qp_bytes; 335 u64 tx_qp_bytes; 336 u64 rx_qp_mc_packets; 337 }; 338 339 struct txgbe_hw_stats { 340 /* MNG RxTx */ 341 u64 mng_bmc2host_packets; 342 u64 mng_host2bmc_packets; 343 /* Basix RxTx */ 344 u64 rx_packets; 345 u64 tx_packets; 346 u64 rx_bytes; 347 u64 tx_bytes; 348 u64 rx_total_bytes; 349 u64 rx_total_packets; 350 u64 tx_total_packets; 351 u64 rx_total_missed_packets; 352 u64 rx_broadcast_packets; 353 u64 tx_broadcast_packets; 354 u64 rx_multicast_packets; 355 u64 tx_multicast_packets; 356 u64 rx_management_packets; 357 u64 tx_management_packets; 358 u64 rx_management_dropped; 359 u64 rx_dma_drop; 360 361 /* Basic Error */ 362 u64 rx_rdb_drop; 363 u64 rx_crc_errors; 364 u64 rx_illegal_byte_errors; 365 u64 rx_error_bytes; 366 u64 rx_mac_short_packet_dropped; 367 u64 rx_length_errors; 368 u64 rx_undersize_errors; 369 u64 rx_fragment_errors; 370 u64 rx_oversize_cnt; 371 u64 rx_jabber_errors; 372 u64 rx_l3_l4_xsum_error; 373 u64 mac_local_errors; 374 u64 mac_remote_errors; 375 376 /* Flow Director */ 377 u64 flow_director_added_filters; 378 u64 flow_director_removed_filters; 379 u64 flow_director_filter_add_errors; 380 u64 flow_director_filter_remove_errors; 381 u64 flow_director_matched_filters; 382 u64 flow_director_missed_filters; 383 384 /* FCoE */ 385 u64 rx_fcoe_crc_errors; 386 u64 rx_fcoe_mbuf_allocation_errors; 387 u64 rx_fcoe_dropped; 388 u64 rx_fcoe_packets; 389 u64 tx_fcoe_packets; 390 u64 rx_fcoe_bytes; 391 u64 tx_fcoe_bytes; 392 u64 rx_fcoe_no_ddp; 393 u64 rx_fcoe_no_ddp_ext_buff; 394 395 /* MACSEC */ 396 u64 tx_macsec_pkts_untagged; 397 u64 tx_macsec_pkts_encrypted; 398 u64 tx_macsec_pkts_protected; 399 u64 tx_macsec_octets_encrypted; 400 u64 tx_macsec_octets_protected; 401 u64 rx_macsec_pkts_untagged; 402 u64 rx_macsec_pkts_badtag; 403 u64 rx_macsec_pkts_nosci; 404 u64 rx_macsec_pkts_unknownsci; 405 u64 rx_macsec_octets_decrypted; 406 u64 rx_macsec_octets_validated; 407 u64 rx_macsec_sc_pkts_unchecked; 408 u64 rx_macsec_sc_pkts_delayed; 409 u64 rx_macsec_sc_pkts_late; 410 u64 rx_macsec_sa_pkts_ok; 411 u64 rx_macsec_sa_pkts_invalid; 412 u64 rx_macsec_sa_pkts_notvalid; 413 u64 rx_macsec_sa_pkts_unusedsa; 414 u64 rx_macsec_sa_pkts_notusingsa; 415 416 /* MAC RxTx */ 417 u64 rx_size_64_packets; 418 u64 rx_size_65_to_127_packets; 419 u64 rx_size_128_to_255_packets; 420 u64 rx_size_256_to_511_packets; 421 u64 rx_size_512_to_1023_packets; 422 u64 rx_size_1024_to_max_packets; 423 u64 tx_size_64_packets; 424 u64 tx_size_65_to_127_packets; 425 u64 tx_size_128_to_255_packets; 426 u64 tx_size_256_to_511_packets; 427 u64 tx_size_512_to_1023_packets; 428 u64 tx_size_1024_to_max_packets; 429 430 /* Flow Control */ 431 u64 tx_xon_packets; 432 u64 rx_xon_packets; 433 u64 tx_xoff_packets; 434 u64 rx_xoff_packets; 435 436 /* PB[] RxTx */ 437 struct { 438 u64 rx_up_packets; 439 u64 tx_up_packets; 440 u64 rx_up_bytes; 441 u64 tx_up_bytes; 442 u64 rx_up_drop_packets; 443 444 u64 tx_up_xon_packets; 445 u64 rx_up_xon_packets; 446 u64 tx_up_xoff_packets; 447 u64 rx_up_xoff_packets; 448 u64 rx_up_dropped; 449 u64 rx_up_mbuf_alloc_errors; 450 u64 tx_up_xon2off_packets; 451 } up[TXGBE_MAX_UP]; 452 453 /* QP[] RxTx */ 454 struct { 455 u64 rx_qp_packets; 456 u64 tx_qp_packets; 457 u64 rx_qp_bytes; 458 u64 tx_qp_bytes; 459 u64 rx_qp_mc_packets; 460 } qp[TXGBE_MAX_QP]; 461 462 }; 463 464 /* iterator type for walking multicast address lists */ 465 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr, 466 u32 *vmdq); 467 468 struct txgbe_link_info { 469 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val); 470 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 471 u16 *val); 472 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val); 473 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg, 474 u16 val); 475 476 u8 addr; 477 }; 478 479 struct txgbe_rom_info { 480 s32 (*init_params)(struct txgbe_hw *hw); 481 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data); 482 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data); 483 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 484 void *data); 485 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data); 486 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 487 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data); 488 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data); 489 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words, 490 void *data); 491 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data); 492 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data); 493 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val); 494 s32 (*update_checksum)(struct txgbe_hw *hw); 495 s32 (*calc_checksum)(struct txgbe_hw *hw); 496 497 enum txgbe_eeprom_type type; 498 u32 semaphore_delay; 499 u16 word_size; 500 u16 address_bits; 501 u16 word_page_size; 502 u16 ctrl_word_3; 503 504 u32 sw_addr; 505 }; 506 507 struct txgbe_flash_info { 508 u32 semaphore_delay; 509 u32 dword_size; 510 u16 address_bits; 511 }; 512 513 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 514 struct txgbe_mac_info { 515 s32 (*init_hw)(struct txgbe_hw *hw); 516 s32 (*reset_hw)(struct txgbe_hw *hw); 517 s32 (*start_hw)(struct txgbe_hw *hw); 518 s32 (*stop_hw)(struct txgbe_hw *hw); 519 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw); 520 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr); 521 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 522 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr); 523 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps); 524 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix, 525 u16 *wwpn_prefix); 526 s32 (*setup_sfp)(struct txgbe_hw *hw); 527 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval); 528 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw); 529 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw); 530 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw); 531 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw); 532 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask); 533 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask); 534 u64 (*autoc_read)(struct txgbe_hw *hw); 535 void (*autoc_write)(struct txgbe_hw *hw, u64 value); 536 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value); 537 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value); 538 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api); 539 540 /* Link */ 541 void (*disable_tx_laser)(struct txgbe_hw *hw); 542 void (*enable_tx_laser)(struct txgbe_hw *hw); 543 void (*flap_tx_laser)(struct txgbe_hw *hw); 544 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed, 545 bool autoneg_wait_to_complete); 546 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed, 547 bool autoneg_wait_to_complete); 548 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, 549 bool *link_up, bool link_up_wait_to_complete); 550 s32 (*get_link_capabilities)(struct txgbe_hw *hw, 551 u32 *speed, bool *autoneg); 552 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed); 553 554 /* Packet Buffer manipulation */ 555 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom, 556 int strategy); 557 558 /* LED */ 559 s32 (*led_on)(struct txgbe_hw *hw, u32 index); 560 s32 (*led_off)(struct txgbe_hw *hw, u32 index); 561 562 /* RAR, Multicast, VLAN */ 563 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 564 u32 enable_addr); 565 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr); 566 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index); 567 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 568 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq); 569 s32 (*init_rx_addrs)(struct txgbe_hw *hw); 570 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list, 571 u32 mc_addr_count, 572 txgbe_mc_addr_itr func, bool clear); 573 s32 (*clear_vfta)(struct txgbe_hw *hw); 574 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan, 575 u32 vind, bool vlan_on, bool vlvf_bypass); 576 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind, 577 bool vlan_on, u32 *vfta_delta, u32 vfta, 578 bool vlvf_bypass); 579 s32 (*init_uta_tables)(struct txgbe_hw *hw); 580 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf); 581 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw, 582 bool enable, int vf); 583 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode); 584 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size); 585 586 /* Flow Control */ 587 s32 (*fc_enable)(struct txgbe_hw *hw); 588 s32 (*setup_fc)(struct txgbe_hw *hw); 589 void (*fc_autoneg)(struct txgbe_hw *hw); 590 591 /* Manageability interface */ 592 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build, 593 u8 ver, u16 len, const char *driver_ver); 594 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw); 595 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw); 596 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map); 597 void (*disable_rx)(struct txgbe_hw *hw); 598 void (*enable_rx)(struct txgbe_hw *hw); 599 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw, 600 bool enable, int vf); 601 s32 (*dmac_update_tcs)(struct txgbe_hw *hw); 602 s32 (*dmac_config_tcs)(struct txgbe_hw *hw); 603 s32 (*dmac_config)(struct txgbe_hw *hw); 604 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee); 605 606 s32 (*kr_handle)(struct txgbe_hw *hw); 607 void (*bp_down_event)(struct txgbe_hw *hw); 608 609 enum txgbe_mac_type type; 610 u8 addr[ETH_ADDR_LEN]; 611 u8 perm_addr[ETH_ADDR_LEN]; 612 u8 san_addr[ETH_ADDR_LEN]; 613 /* prefix for World Wide Node Name (WWNN) */ 614 u16 wwnn_prefix; 615 /* prefix for World Wide Port Name (WWPN) */ 616 u16 wwpn_prefix; 617 #define TXGBE_MAX_MTA 128 618 u32 mta_shadow[TXGBE_MAX_MTA]; 619 s32 mc_filter_type; 620 u32 mcft_size; 621 u32 vft_size; 622 u32 num_rar_entries; 623 u32 rx_pb_size; 624 u32 max_tx_queues; 625 u32 max_rx_queues; 626 u64 autoc; 627 u64 orig_autoc; /* cached value of AUTOC */ 628 u8 san_mac_rar_index; 629 bool get_link_status; 630 bool orig_link_settings_stored; 631 bool autotry_restart; 632 u8 flags; 633 struct txgbe_thermal_sensor_data thermal_sensor_data; 634 bool set_lben; 635 u32 max_link_up_time; 636 }; 637 638 struct txgbe_phy_info { 639 u32 (*get_media_type)(struct txgbe_hw *hw); 640 s32 (*identify)(struct txgbe_hw *hw); 641 s32 (*identify_sfp)(struct txgbe_hw *hw); 642 s32 (*init)(struct txgbe_hw *hw); 643 s32 (*reset)(struct txgbe_hw *hw); 644 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr, 645 u32 device_type, u16 *phy_data); 646 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr, 647 u32 device_type, u16 phy_data); 648 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 649 u32 device_type, u16 *phy_data); 650 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr, 651 u32 device_type, u16 phy_data); 652 s32 (*setup_link)(struct txgbe_hw *hw); 653 s32 (*setup_internal_link)(struct txgbe_hw *hw); 654 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed, 655 bool autoneg_wait_to_complete); 656 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up); 657 s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version); 658 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 659 u8 dev_addr, u8 *data); 660 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset, 661 u8 dev_addr, u8 data); 662 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset, 663 u8 *sff8472_data); 664 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 665 u8 *eeprom_data); 666 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset, 667 u8 eeprom_data); 668 s32 (*check_overtemp)(struct txgbe_hw *hw); 669 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on); 670 s32 (*handle_lasi)(struct txgbe_hw *hw); 671 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 672 u8 *value); 673 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr, 674 u8 value); 675 676 enum txgbe_phy_type type; 677 u32 addr; 678 u32 id; 679 enum txgbe_sfp_type sfp_type; 680 bool sfp_setup_needed; 681 u32 revision; 682 u32 media_type; 683 u32 phy_semaphore_mask; 684 bool reset_disable; 685 u32 autoneg_advertised; 686 u32 speeds_supported; 687 enum txgbe_smart_speed smart_speed; 688 bool smart_speed_active; 689 bool multispeed_fiber; 690 bool qsfp_shared_i2c_bus; 691 u32 nw_mng_if_sel; 692 u32 link_mode; 693 694 /* Some features need tri-state capability */ 695 u16 ffe_set; 696 u16 ffe_main; 697 u16 ffe_pre; 698 u16 ffe_post; 699 }; 700 701 #define TXGBE_DEVARG_BP_AUTO "auto_neg" 702 #define TXGBE_DEVARG_KR_POLL "poll" 703 #define TXGBE_DEVARG_KR_PRESENT "present" 704 #define TXGBE_DEVARG_KX_SGMII "sgmii" 705 #define TXGBE_DEVARG_FFE_SET "ffe_set" 706 #define TXGBE_DEVARG_FFE_MAIN "ffe_main" 707 #define TXGBE_DEVARG_FFE_PRE "ffe_pre" 708 #define TXGBE_DEVARG_FFE_POST "ffe_post" 709 710 static const char * const txgbe_valid_arguments[] = { 711 TXGBE_DEVARG_BP_AUTO, 712 TXGBE_DEVARG_KR_POLL, 713 TXGBE_DEVARG_KR_PRESENT, 714 TXGBE_DEVARG_KX_SGMII, 715 TXGBE_DEVARG_FFE_SET, 716 TXGBE_DEVARG_FFE_MAIN, 717 TXGBE_DEVARG_FFE_PRE, 718 TXGBE_DEVARG_FFE_POST, 719 NULL 720 }; 721 722 struct txgbe_mbx_stats { 723 u32 msgs_tx; 724 u32 msgs_rx; 725 726 u32 acks; 727 u32 reqs; 728 u32 rsts; 729 }; 730 731 struct txgbe_mbx_info { 732 void (*init_params)(struct txgbe_hw *hw); 733 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 734 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number); 735 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 736 u16 mbx_id); 737 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size, 738 u16 mbx_id); 739 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id); 740 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id); 741 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id); 742 743 struct txgbe_mbx_stats stats; 744 u32 timeout; 745 u32 usec_delay; 746 u32 v2p_mailbox; 747 u16 size; 748 }; 749 750 enum txgbe_isb_idx { 751 TXGBE_ISB_HEADER, 752 TXGBE_ISB_MISC, 753 TXGBE_ISB_VEC0, 754 TXGBE_ISB_VEC1, 755 TXGBE_ISB_MAX 756 }; 757 758 struct txgbe_devargs { 759 u16 auto_neg; 760 u16 poll; 761 u16 present; 762 u16 sgmii; 763 }; 764 765 struct txgbe_hw { 766 void IOMEM *hw_addr; 767 void *back; 768 struct txgbe_mac_info mac; 769 struct txgbe_addr_filter_info addr_ctrl; 770 struct txgbe_fc_info fc; 771 struct txgbe_phy_info phy; 772 struct txgbe_link_info link; 773 struct txgbe_rom_info rom; 774 struct txgbe_flash_info flash; 775 struct txgbe_bus_info bus; 776 struct txgbe_mbx_info mbx; 777 u16 device_id; 778 u16 vendor_id; 779 u16 subsystem_device_id; 780 u16 subsystem_vendor_id; 781 u8 port_id; 782 u8 revision_id; 783 bool adapter_stopped; 784 int api_version; 785 bool allow_unsupported_sfp; 786 bool lldp_enabled; 787 bool need_crosstalk_fix; 788 bool dev_start; 789 bool autoneg; 790 struct txgbe_devargs devarg; 791 792 uint64_t isb_dma; 793 void IOMEM *isb_mem; 794 u16 nb_rx_queues; 795 u16 nb_tx_queues; 796 797 u32 fw_version; 798 u32 mode; 799 enum txgbe_link_status { 800 TXGBE_LINK_STATUS_NONE = 0, 801 TXGBE_LINK_STATUS_KX, 802 TXGBE_LINK_STATUS_KX4 803 } link_status; 804 enum txgbe_reset_type { 805 TXGBE_LAN_RESET = 0, 806 TXGBE_SW_RESET, 807 TXGBE_GLOBAL_RESET 808 } reset_type; 809 810 u32 q_rx_regs[128 * 4]; 811 u32 q_tx_regs[128 * 4]; 812 bool offset_loaded; 813 bool rx_loaded; 814 struct { 815 u64 rx_qp_packets; 816 u64 tx_qp_packets; 817 u64 rx_qp_bytes; 818 u64 tx_qp_bytes; 819 u64 rx_qp_mc_packets; 820 } qp_last[TXGBE_MAX_QP]; 821 }; 822 823 struct txgbe_backplane_ability { 824 u32 next_page; /* Next Page (bit0) */ 825 u32 link_ability; /* Link Ability (bit[7:0]) */ 826 u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */ 827 u32 current_link_mode; /* current link mode for local device */ 828 }; 829 830 #include "txgbe_regs.h" 831 #include "txgbe_dummy.h" 832 833 #endif /* _TXGBE_TYPE_H_ */ 834