1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <rte_dev.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <ethdev_driver.h> 27 #include <ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <rte_bus_pci.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 static int nicvf_dev_stop(struct rte_eth_dev *dev); 48 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 49 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 50 bool cleanup); 51 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 52 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 53 54 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_mbox, mbox, NOTICE); 55 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_init, init, NOTICE); 56 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); 57 58 static void 59 nicvf_link_status_update(struct nicvf *nic, 60 struct rte_eth_link *link) 61 { 62 memset(link, 0, sizeof(*link)); 63 64 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 65 66 if (nic->duplex == NICVF_HALF_DUPLEX) 67 link->link_duplex = ETH_LINK_HALF_DUPLEX; 68 else if (nic->duplex == NICVF_FULL_DUPLEX) 69 link->link_duplex = ETH_LINK_FULL_DUPLEX; 70 link->link_speed = nic->speed; 71 link->link_autoneg = ETH_LINK_AUTONEG; 72 } 73 74 static void 75 nicvf_interrupt(void *arg) 76 { 77 struct rte_eth_dev *dev = arg; 78 struct nicvf *nic = nicvf_pmd_priv(dev); 79 struct rte_eth_link link; 80 81 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 82 if (dev->data->dev_conf.intr_conf.lsc) { 83 nicvf_link_status_update(nic, &link); 84 rte_eth_linkstatus_set(dev, &link); 85 86 rte_eth_dev_callback_process(dev, 87 RTE_ETH_EVENT_INTR_LSC, 88 NULL); 89 } 90 } 91 92 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 93 nicvf_interrupt, dev); 94 } 95 96 static void 97 nicvf_vf_interrupt(void *arg) 98 { 99 struct nicvf *nic = arg; 100 101 nicvf_reg_poll_interrupts(nic); 102 103 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 104 nicvf_vf_interrupt, nic); 105 } 106 107 static int 108 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 109 { 110 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 111 } 112 113 static int 114 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 115 { 116 return rte_eal_alarm_cancel(fn, arg); 117 } 118 119 /* 120 * Return 0 means link status changed, -1 means not changed 121 */ 122 static int 123 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 124 { 125 #define CHECK_INTERVAL 100 /* 100ms */ 126 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 127 struct rte_eth_link link; 128 struct nicvf *nic = nicvf_pmd_priv(dev); 129 int i; 130 131 PMD_INIT_FUNC_TRACE(); 132 133 if (wait_to_complete) { 134 /* rte_eth_link_get() might need to wait up to 9 seconds */ 135 for (i = 0; i < MAX_CHECK_TIME; i++) { 136 nicvf_link_status_update(nic, &link); 137 if (link.link_status == ETH_LINK_UP) 138 break; 139 rte_delay_ms(CHECK_INTERVAL); 140 } 141 } else { 142 nicvf_link_status_update(nic, &link); 143 } 144 145 return rte_eth_linkstatus_set(dev, &link); 146 } 147 148 static int 149 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 150 { 151 struct nicvf *nic = nicvf_pmd_priv(dev); 152 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 153 size_t i; 154 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 155 156 PMD_INIT_FUNC_TRACE(); 157 158 if (frame_size > NIC_HW_MAX_FRS) 159 return -EINVAL; 160 161 if (frame_size < NIC_HW_MIN_FRS) 162 return -EINVAL; 163 164 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 165 166 /* 167 * Refuse mtu that requires the support of scattered packets 168 * when this feature has not been enabled before. 169 */ 170 if (dev->data->dev_started && !dev->data->scattered_rx && 171 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 172 return -EINVAL; 173 174 /* check <seg size> * <max_seg> >= max_frame */ 175 if (dev->data->scattered_rx && 176 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 177 return -EINVAL; 178 179 if (frame_size > NIC_HW_L2_MAX_LEN) 180 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 181 else 182 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 183 184 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 185 return -EINVAL; 186 187 /* Update max_rx_pkt_len */ 188 rxmode->max_rx_pkt_len = mtu + RTE_ETHER_HDR_LEN; 189 nic->mtu = mtu; 190 191 for (i = 0; i < nic->sqs_count; i++) 192 nic->snicvf[i]->mtu = mtu; 193 194 return 0; 195 } 196 197 static int 198 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 199 { 200 uint64_t *data = regs->data; 201 struct nicvf *nic = nicvf_pmd_priv(dev); 202 203 if (data == NULL) { 204 regs->length = nicvf_reg_get_count(); 205 regs->width = THUNDERX_REG_BYTES; 206 return 0; 207 } 208 209 /* Support only full register dump */ 210 if ((regs->length == 0) || 211 (regs->length == (uint32_t)nicvf_reg_get_count())) { 212 regs->version = nic->vendor_id << 16 | nic->device_id; 213 nicvf_reg_dump(nic, data); 214 return 0; 215 } 216 return -ENOTSUP; 217 } 218 219 static int 220 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 221 { 222 uint16_t qidx; 223 struct nicvf_hw_rx_qstats rx_qstats; 224 struct nicvf_hw_tx_qstats tx_qstats; 225 struct nicvf_hw_stats port_stats; 226 struct nicvf *nic = nicvf_pmd_priv(dev); 227 uint16_t rx_start, rx_end; 228 uint16_t tx_start, tx_end; 229 size_t i; 230 231 /* RX queue indices for the first VF */ 232 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 233 234 /* Reading per RX ring stats */ 235 for (qidx = rx_start; qidx <= rx_end; qidx++) { 236 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 237 break; 238 239 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 240 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 241 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 242 } 243 244 /* TX queue indices for the first VF */ 245 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 246 247 /* Reading per TX ring stats */ 248 for (qidx = tx_start; qidx <= tx_end; qidx++) { 249 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 250 break; 251 252 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 253 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 254 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 255 } 256 257 for (i = 0; i < nic->sqs_count; i++) { 258 struct nicvf *snic = nic->snicvf[i]; 259 260 if (snic == NULL) 261 break; 262 263 /* RX queue indices for a secondary VF */ 264 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 265 266 /* Reading per RX ring stats */ 267 for (qidx = rx_start; qidx <= rx_end; qidx++) { 268 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 269 break; 270 271 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 272 qidx % MAX_RCV_QUEUES_PER_QS); 273 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 274 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 275 } 276 277 /* TX queue indices for a secondary VF */ 278 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 279 /* Reading per TX ring stats */ 280 for (qidx = tx_start; qidx <= tx_end; qidx++) { 281 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 282 break; 283 284 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 285 qidx % MAX_SND_QUEUES_PER_QS); 286 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 287 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 288 } 289 } 290 291 nicvf_hw_get_stats(nic, &port_stats); 292 stats->ibytes = port_stats.rx_bytes; 293 stats->ipackets = port_stats.rx_ucast_frames; 294 stats->ipackets += port_stats.rx_bcast_frames; 295 stats->ipackets += port_stats.rx_mcast_frames; 296 stats->ierrors = port_stats.rx_l2_errors; 297 stats->imissed = port_stats.rx_drop_red; 298 stats->imissed += port_stats.rx_drop_overrun; 299 stats->imissed += port_stats.rx_drop_bcast; 300 stats->imissed += port_stats.rx_drop_mcast; 301 stats->imissed += port_stats.rx_drop_l3_bcast; 302 stats->imissed += port_stats.rx_drop_l3_mcast; 303 304 stats->obytes = port_stats.tx_bytes_ok; 305 stats->opackets = port_stats.tx_ucast_frames_ok; 306 stats->opackets += port_stats.tx_bcast_frames_ok; 307 stats->opackets += port_stats.tx_mcast_frames_ok; 308 stats->oerrors = port_stats.tx_drops; 309 310 return 0; 311 } 312 313 static const uint32_t * 314 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 315 { 316 size_t copied; 317 static uint32_t ptypes[32]; 318 struct nicvf *nic = nicvf_pmd_priv(dev); 319 static const uint32_t ptypes_common[] = { 320 RTE_PTYPE_L3_IPV4, 321 RTE_PTYPE_L3_IPV4_EXT, 322 RTE_PTYPE_L3_IPV6, 323 RTE_PTYPE_L3_IPV6_EXT, 324 RTE_PTYPE_L4_TCP, 325 RTE_PTYPE_L4_UDP, 326 RTE_PTYPE_L4_FRAG, 327 }; 328 static const uint32_t ptypes_tunnel[] = { 329 RTE_PTYPE_TUNNEL_GRE, 330 RTE_PTYPE_TUNNEL_GENEVE, 331 RTE_PTYPE_TUNNEL_VXLAN, 332 RTE_PTYPE_TUNNEL_NVGRE, 333 }; 334 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 335 336 copied = sizeof(ptypes_common); 337 memcpy(ptypes, ptypes_common, copied); 338 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 339 memcpy((char *)ptypes + copied, ptypes_tunnel, 340 sizeof(ptypes_tunnel)); 341 copied += sizeof(ptypes_tunnel); 342 } 343 344 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 345 346 /* All Ptypes are supported in all Rx functions. */ 347 return ptypes; 348 } 349 350 static int 351 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 352 { 353 int i; 354 uint16_t rxqs = 0, txqs = 0; 355 struct nicvf *nic = nicvf_pmd_priv(dev); 356 uint16_t rx_start, rx_end; 357 uint16_t tx_start, tx_end; 358 int ret; 359 360 /* Reset all primary nic counters */ 361 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 362 for (i = rx_start; i <= rx_end; i++) 363 rxqs |= (0x3 << (i * 2)); 364 365 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 366 for (i = tx_start; i <= tx_end; i++) 367 txqs |= (0x3 << (i * 2)); 368 369 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 370 if (ret != 0) 371 return ret; 372 373 /* Reset secondary nic queue counters */ 374 for (i = 0; i < nic->sqs_count; i++) { 375 struct nicvf *snic = nic->snicvf[i]; 376 if (snic == NULL) 377 break; 378 379 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 380 for (i = rx_start; i <= rx_end; i++) 381 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 382 383 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 384 for (i = tx_start; i <= tx_end; i++) 385 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 386 387 ret = nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 388 if (ret != 0) 389 return ret; 390 } 391 392 return 0; 393 } 394 395 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 396 static int 397 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 398 { 399 return 0; 400 } 401 402 static inline uint64_t 403 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 404 { 405 uint64_t nic_rss = 0; 406 407 if (ethdev_rss & ETH_RSS_IPV4) 408 nic_rss |= RSS_IP_ENA; 409 410 if (ethdev_rss & ETH_RSS_IPV6) 411 nic_rss |= RSS_IP_ENA; 412 413 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 414 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 415 416 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 417 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 418 419 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 420 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 421 422 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 423 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 424 425 if (ethdev_rss & ETH_RSS_PORT) 426 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 427 428 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 429 if (ethdev_rss & ETH_RSS_VXLAN) 430 nic_rss |= RSS_TUN_VXLAN_ENA; 431 432 if (ethdev_rss & ETH_RSS_GENEVE) 433 nic_rss |= RSS_TUN_GENEVE_ENA; 434 435 if (ethdev_rss & ETH_RSS_NVGRE) 436 nic_rss |= RSS_TUN_NVGRE_ENA; 437 } 438 439 return nic_rss; 440 } 441 442 static inline uint64_t 443 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 444 { 445 uint64_t ethdev_rss = 0; 446 447 if (nic_rss & RSS_IP_ENA) 448 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 449 450 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 451 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 452 ETH_RSS_NONFRAG_IPV6_TCP); 453 454 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 455 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 456 ETH_RSS_NONFRAG_IPV6_UDP); 457 458 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 459 ethdev_rss |= ETH_RSS_PORT; 460 461 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 462 if (nic_rss & RSS_TUN_VXLAN_ENA) 463 ethdev_rss |= ETH_RSS_VXLAN; 464 465 if (nic_rss & RSS_TUN_GENEVE_ENA) 466 ethdev_rss |= ETH_RSS_GENEVE; 467 468 if (nic_rss & RSS_TUN_NVGRE_ENA) 469 ethdev_rss |= ETH_RSS_NVGRE; 470 } 471 return ethdev_rss; 472 } 473 474 static int 475 nicvf_dev_reta_query(struct rte_eth_dev *dev, 476 struct rte_eth_rss_reta_entry64 *reta_conf, 477 uint16_t reta_size) 478 { 479 struct nicvf *nic = nicvf_pmd_priv(dev); 480 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 481 int ret, i, j; 482 483 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 484 PMD_DRV_LOG(ERR, 485 "The size of hash lookup table configured " 486 "(%u) doesn't match the number hardware can supported " 487 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 488 return -EINVAL; 489 } 490 491 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 492 if (ret) 493 return ret; 494 495 /* Copy RETA table */ 496 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 497 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 498 if ((reta_conf[i].mask >> j) & 0x01) 499 reta_conf[i].reta[j] = tbl[j]; 500 } 501 502 return 0; 503 } 504 505 static int 506 nicvf_dev_reta_update(struct rte_eth_dev *dev, 507 struct rte_eth_rss_reta_entry64 *reta_conf, 508 uint16_t reta_size) 509 { 510 struct nicvf *nic = nicvf_pmd_priv(dev); 511 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 512 int ret, i, j; 513 514 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 515 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 516 "(%u) doesn't match the number hardware can supported " 517 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 518 return -EINVAL; 519 } 520 521 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 522 if (ret) 523 return ret; 524 525 /* Copy RETA table */ 526 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 527 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 528 if ((reta_conf[i].mask >> j) & 0x01) 529 tbl[j] = reta_conf[i].reta[j]; 530 } 531 532 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 533 } 534 535 static int 536 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 537 struct rte_eth_rss_conf *rss_conf) 538 { 539 struct nicvf *nic = nicvf_pmd_priv(dev); 540 541 if (rss_conf->rss_key) 542 nicvf_rss_get_key(nic, rss_conf->rss_key); 543 544 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 545 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 546 return 0; 547 } 548 549 static int 550 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 551 struct rte_eth_rss_conf *rss_conf) 552 { 553 struct nicvf *nic = nicvf_pmd_priv(dev); 554 uint64_t nic_rss; 555 556 if (rss_conf->rss_key && 557 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 558 PMD_DRV_LOG(ERR, "Hash key size mismatch %u", 559 rss_conf->rss_key_len); 560 return -EINVAL; 561 } 562 563 if (rss_conf->rss_key) 564 nicvf_rss_set_key(nic, rss_conf->rss_key); 565 566 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 567 nicvf_rss_set_cfg(nic, nic_rss); 568 return 0; 569 } 570 571 static int 572 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 573 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 574 { 575 const struct rte_memzone *rz; 576 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 577 578 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 579 nicvf_netdev_qidx(nic, qidx), ring_size, 580 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 581 if (rz == NULL) { 582 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 583 return -ENOMEM; 584 } 585 586 memset(rz->addr, 0, ring_size); 587 588 rxq->phys = rz->iova; 589 rxq->desc = rz->addr; 590 rxq->qlen_mask = desc_cnt - 1; 591 592 return 0; 593 } 594 595 static int 596 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 597 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 598 { 599 const struct rte_memzone *rz; 600 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 601 602 rz = rte_eth_dma_zone_reserve(dev, "sq", 603 nicvf_netdev_qidx(nic, qidx), ring_size, 604 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 605 if (rz == NULL) { 606 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 607 return -ENOMEM; 608 } 609 610 memset(rz->addr, 0, ring_size); 611 612 sq->phys = rz->iova; 613 sq->desc = rz->addr; 614 sq->qlen_mask = desc_cnt - 1; 615 616 return 0; 617 } 618 619 static int 620 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 621 uint32_t desc_cnt, uint32_t buffsz) 622 { 623 struct nicvf_rbdr *rbdr; 624 const struct rte_memzone *rz; 625 uint32_t ring_size; 626 627 assert(nic->rbdr == NULL); 628 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 629 RTE_CACHE_LINE_SIZE, nic->node); 630 if (rbdr == NULL) { 631 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 632 return -ENOMEM; 633 } 634 635 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 636 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 637 nicvf_netdev_qidx(nic, 0), ring_size, 638 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 639 if (rz == NULL) { 640 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 641 rte_free(rbdr); 642 return -ENOMEM; 643 } 644 645 memset(rz->addr, 0, ring_size); 646 647 rbdr->phys = rz->iova; 648 rbdr->tail = 0; 649 rbdr->next_tail = 0; 650 rbdr->desc = rz->addr; 651 rbdr->buffsz = buffsz; 652 rbdr->qlen_mask = desc_cnt - 1; 653 rbdr->rbdr_status = 654 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 655 rbdr->rbdr_door = 656 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 657 658 nic->rbdr = rbdr; 659 return 0; 660 } 661 662 static void 663 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 664 nicvf_iova_addr_t phy) 665 { 666 uint16_t qidx; 667 void *obj; 668 struct nicvf_rxq *rxq; 669 uint16_t rx_start, rx_end; 670 671 /* Get queue ranges for this VF */ 672 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 673 674 for (qidx = rx_start; qidx <= rx_end; qidx++) { 675 rxq = dev->data->rx_queues[qidx]; 676 if (rxq->precharge_cnt) { 677 obj = (void *)nicvf_mbuff_phy2virt(phy, 678 rxq->mbuf_phys_off); 679 rte_mempool_put(rxq->pool, obj); 680 rxq->precharge_cnt--; 681 break; 682 } 683 } 684 } 685 686 static inline void 687 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 688 { 689 uint32_t qlen_mask, head; 690 struct rbdr_entry_t *entry; 691 struct nicvf_rbdr *rbdr = nic->rbdr; 692 693 qlen_mask = rbdr->qlen_mask; 694 head = rbdr->head; 695 while (head != rbdr->tail) { 696 entry = rbdr->desc + head; 697 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 698 head++; 699 head = head & qlen_mask; 700 } 701 } 702 703 static inline void 704 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 705 { 706 uint32_t head; 707 708 head = txq->head; 709 while (head != txq->tail) { 710 if (txq->txbuffs[head]) { 711 rte_pktmbuf_free_seg(txq->txbuffs[head]); 712 txq->txbuffs[head] = NULL; 713 } 714 head++; 715 head = head & txq->qlen_mask; 716 } 717 } 718 719 static void 720 nicvf_tx_queue_reset(struct nicvf_txq *txq) 721 { 722 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 723 724 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 725 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 726 txq->tail = 0; 727 txq->head = 0; 728 txq->xmit_bufs = 0; 729 } 730 731 static inline int 732 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 733 uint16_t qidx) 734 { 735 struct nicvf_txq *txq; 736 int ret; 737 738 assert(qidx < MAX_SND_QUEUES_PER_QS); 739 740 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 741 RTE_ETH_QUEUE_STATE_STARTED) 742 return 0; 743 744 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 745 txq->pool = NULL; 746 ret = nicvf_qset_sq_config(nic, qidx, txq); 747 if (ret) { 748 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 749 nic->vf_id, qidx, ret); 750 goto config_sq_error; 751 } 752 753 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 754 RTE_ETH_QUEUE_STATE_STARTED; 755 return ret; 756 757 config_sq_error: 758 nicvf_qset_sq_reclaim(nic, qidx); 759 return ret; 760 } 761 762 static inline int 763 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 764 uint16_t qidx) 765 { 766 struct nicvf_txq *txq; 767 int ret; 768 769 assert(qidx < MAX_SND_QUEUES_PER_QS); 770 771 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 772 RTE_ETH_QUEUE_STATE_STOPPED) 773 return 0; 774 775 ret = nicvf_qset_sq_reclaim(nic, qidx); 776 if (ret) 777 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 778 nic->vf_id, qidx, ret); 779 780 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 781 nicvf_tx_queue_release_mbufs(txq); 782 nicvf_tx_queue_reset(txq); 783 784 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 785 RTE_ETH_QUEUE_STATE_STOPPED; 786 return ret; 787 } 788 789 static inline int 790 nicvf_configure_cpi(struct rte_eth_dev *dev) 791 { 792 struct nicvf *nic = nicvf_pmd_priv(dev); 793 uint16_t qidx, qcnt; 794 int ret; 795 796 /* Count started rx queues */ 797 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 798 if (dev->data->rx_queue_state[qidx] == 799 RTE_ETH_QUEUE_STATE_STARTED) 800 qcnt++; 801 802 nic->cpi_alg = CPI_ALG_NONE; 803 ret = nicvf_mbox_config_cpi(nic, qcnt); 804 if (ret) 805 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 806 807 return ret; 808 } 809 810 static inline int 811 nicvf_configure_rss(struct rte_eth_dev *dev) 812 { 813 struct nicvf *nic = nicvf_pmd_priv(dev); 814 uint64_t rsshf; 815 int ret = -EINVAL; 816 817 rsshf = nicvf_rss_ethdev_to_nic(nic, 818 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 819 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 820 dev->data->dev_conf.rxmode.mq_mode, 821 dev->data->nb_rx_queues, 822 dev->data->dev_conf.lpbk_mode, rsshf); 823 824 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 825 ret = nicvf_rss_term(nic); 826 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 827 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 828 if (ret) 829 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 830 831 return ret; 832 } 833 834 static int 835 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 836 { 837 struct nicvf *nic = nicvf_pmd_priv(dev); 838 unsigned int idx, qmap_size; 839 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 840 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 841 842 if (nic->cpi_alg != CPI_ALG_NONE) 843 return -EINVAL; 844 845 /* Prepare queue map */ 846 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 847 if (dev->data->rx_queue_state[idx] == 848 RTE_ETH_QUEUE_STATE_STARTED) 849 qmap[qmap_size++] = idx; 850 } 851 852 /* Update default RSS RETA */ 853 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 854 default_reta[idx] = qmap[idx % qmap_size]; 855 856 return nicvf_rss_reta_update(nic, default_reta, 857 NIC_MAX_RSS_IDR_TBL_SIZE); 858 } 859 860 static void 861 nicvf_dev_tx_queue_release(void *sq) 862 { 863 struct nicvf_txq *txq; 864 865 PMD_INIT_FUNC_TRACE(); 866 867 txq = (struct nicvf_txq *)sq; 868 if (txq) { 869 if (txq->txbuffs != NULL) { 870 nicvf_tx_queue_release_mbufs(txq); 871 rte_free(txq->txbuffs); 872 txq->txbuffs = NULL; 873 } 874 rte_free(txq); 875 } 876 } 877 878 static void 879 nicvf_set_tx_function(struct rte_eth_dev *dev) 880 { 881 struct nicvf_txq *txq = NULL; 882 size_t i; 883 bool multiseg = false; 884 885 for (i = 0; i < dev->data->nb_tx_queues; i++) { 886 txq = dev->data->tx_queues[i]; 887 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) { 888 multiseg = true; 889 break; 890 } 891 } 892 893 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 894 if (multiseg) { 895 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 896 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 897 } else { 898 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 899 dev->tx_pkt_burst = nicvf_xmit_pkts; 900 } 901 902 if (!txq) 903 return; 904 905 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 906 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 907 else 908 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 909 } 910 911 static void 912 nicvf_set_rx_function(struct rte_eth_dev *dev) 913 { 914 struct nicvf *nic = nicvf_pmd_priv(dev); 915 916 const eth_rx_burst_t rx_burst_func[2][2][2] = { 917 /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */ 918 [0][0][0] = nicvf_recv_pkts_no_offload, 919 [0][0][1] = nicvf_recv_pkts_vlan_strip, 920 [0][1][0] = nicvf_recv_pkts_cksum, 921 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip, 922 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload, 923 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip, 924 [1][1][0] = nicvf_recv_pkts_multiseg_cksum, 925 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip, 926 }; 927 928 dev->rx_pkt_burst = 929 rx_burst_func[dev->data->scattered_rx] 930 [nic->offload_cksum][nic->vlan_strip]; 931 } 932 933 static int 934 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 935 uint16_t nb_desc, unsigned int socket_id, 936 const struct rte_eth_txconf *tx_conf) 937 { 938 uint16_t tx_free_thresh; 939 bool is_single_pool; 940 struct nicvf_txq *txq; 941 struct nicvf *nic = nicvf_pmd_priv(dev); 942 uint64_t offloads; 943 944 PMD_INIT_FUNC_TRACE(); 945 946 if (qidx >= MAX_SND_QUEUES_PER_QS) 947 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 948 949 qidx = qidx % MAX_SND_QUEUES_PER_QS; 950 951 /* Socket id check */ 952 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 953 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 954 socket_id, nic->node); 955 956 /* Tx deferred start is not supported */ 957 if (tx_conf->tx_deferred_start) { 958 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 959 return -EINVAL; 960 } 961 962 /* Roundup nb_desc to available qsize and validate max number of desc */ 963 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 964 if (nb_desc == 0) { 965 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 966 return -EINVAL; 967 } 968 969 /* Validate tx_free_thresh */ 970 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 971 tx_conf->tx_free_thresh : 972 NICVF_DEFAULT_TX_FREE_THRESH); 973 974 if (tx_free_thresh > (nb_desc) || 975 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 976 PMD_INIT_LOG(ERR, 977 "tx_free_thresh must be less than the number of TX " 978 "descriptors. (tx_free_thresh=%u port=%d " 979 "queue=%d)", (unsigned int)tx_free_thresh, 980 (int)dev->data->port_id, (int)qidx); 981 return -EINVAL; 982 } 983 984 /* Free memory prior to re-allocation if needed. */ 985 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 986 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 987 nicvf_netdev_qidx(nic, qidx)); 988 nicvf_dev_tx_queue_release( 989 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]); 990 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 991 } 992 993 /* Allocating tx queue data structure */ 994 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 995 RTE_CACHE_LINE_SIZE, nic->node); 996 if (txq == NULL) { 997 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 998 nicvf_netdev_qidx(nic, qidx)); 999 return -ENOMEM; 1000 } 1001 1002 txq->nic = nic; 1003 txq->queue_id = qidx; 1004 txq->tx_free_thresh = tx_free_thresh; 1005 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1006 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1007 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1008 txq->offloads = offloads; 1009 1010 is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); 1011 1012 /* Choose optimum free threshold value for multipool case */ 1013 if (!is_single_pool) { 1014 txq->tx_free_thresh = (uint16_t) 1015 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1016 NICVF_TX_FREE_MPOOL_THRESH : 1017 tx_conf->tx_free_thresh); 1018 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1019 } else { 1020 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1021 } 1022 1023 /* Allocate software ring */ 1024 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1025 nb_desc * sizeof(struct rte_mbuf *), 1026 RTE_CACHE_LINE_SIZE, nic->node); 1027 1028 if (txq->txbuffs == NULL) { 1029 nicvf_dev_tx_queue_release(txq); 1030 return -ENOMEM; 1031 } 1032 1033 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1034 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1035 nicvf_dev_tx_queue_release(txq); 1036 return -ENOMEM; 1037 } 1038 1039 nicvf_tx_queue_reset(txq); 1040 1041 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1042 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1043 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1044 txq->phys, txq->offloads); 1045 1046 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1047 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1048 RTE_ETH_QUEUE_STATE_STOPPED; 1049 return 0; 1050 } 1051 1052 static inline void 1053 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1054 { 1055 uint32_t rxq_cnt; 1056 uint32_t nb_pkts, released_pkts = 0; 1057 uint32_t refill_cnt = 0; 1058 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1059 1060 if (dev->rx_pkt_burst == NULL) 1061 return; 1062 1063 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, 1064 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) { 1065 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1066 NICVF_MAX_RX_FREE_THRESH); 1067 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1068 while (nb_pkts) { 1069 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1070 released_pkts++; 1071 } 1072 } 1073 1074 1075 refill_cnt += nicvf_dev_rbdr_refill(dev, 1076 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1077 1078 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1079 released_pkts, refill_cnt); 1080 } 1081 1082 static void 1083 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1084 { 1085 rxq->head = 0; 1086 rxq->available_space = 0; 1087 rxq->recv_buffers = 0; 1088 } 1089 1090 static inline int 1091 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1092 uint16_t qidx) 1093 { 1094 struct nicvf_rxq *rxq; 1095 int ret; 1096 1097 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1098 1099 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1100 RTE_ETH_QUEUE_STATE_STARTED) 1101 return 0; 1102 1103 /* Update rbdr pointer to all rxq */ 1104 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1105 rxq->shared_rbdr = nic->rbdr; 1106 1107 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1108 if (ret) { 1109 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1110 nic->vf_id, qidx, ret); 1111 goto config_rq_error; 1112 } 1113 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1114 if (ret) { 1115 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1116 nic->vf_id, qidx, ret); 1117 goto config_cq_error; 1118 } 1119 1120 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1121 RTE_ETH_QUEUE_STATE_STARTED; 1122 return 0; 1123 1124 config_cq_error: 1125 nicvf_qset_cq_reclaim(nic, qidx); 1126 config_rq_error: 1127 nicvf_qset_rq_reclaim(nic, qidx); 1128 return ret; 1129 } 1130 1131 static inline int 1132 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1133 uint16_t qidx) 1134 { 1135 struct nicvf_rxq *rxq; 1136 int ret, other_error; 1137 1138 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1139 RTE_ETH_QUEUE_STATE_STOPPED) 1140 return 0; 1141 1142 ret = nicvf_qset_rq_reclaim(nic, qidx); 1143 if (ret) 1144 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1145 nic->vf_id, qidx, ret); 1146 1147 other_error = ret; 1148 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1149 nicvf_rx_queue_release_mbufs(dev, rxq); 1150 nicvf_rx_queue_reset(rxq); 1151 1152 ret = nicvf_qset_cq_reclaim(nic, qidx); 1153 if (ret) 1154 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1155 nic->vf_id, qidx, ret); 1156 1157 other_error |= ret; 1158 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1159 RTE_ETH_QUEUE_STATE_STOPPED; 1160 return other_error; 1161 } 1162 1163 static void 1164 nicvf_dev_rx_queue_release(void *rx_queue) 1165 { 1166 PMD_INIT_FUNC_TRACE(); 1167 1168 rte_free(rx_queue); 1169 } 1170 1171 static int 1172 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1173 { 1174 struct nicvf *nic = nicvf_pmd_priv(dev); 1175 int ret; 1176 1177 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1178 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1179 1180 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1181 1182 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1183 if (ret) 1184 return ret; 1185 1186 ret = nicvf_configure_cpi(dev); 1187 if (ret) 1188 return ret; 1189 1190 return nicvf_configure_rss_reta(dev); 1191 } 1192 1193 static int 1194 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1195 { 1196 int ret; 1197 struct nicvf *nic = nicvf_pmd_priv(dev); 1198 1199 if (qidx >= MAX_SND_QUEUES_PER_QS) 1200 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1201 1202 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1203 1204 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1205 ret |= nicvf_configure_cpi(dev); 1206 ret |= nicvf_configure_rss_reta(dev); 1207 return ret; 1208 } 1209 1210 static int 1211 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1212 { 1213 struct nicvf *nic = nicvf_pmd_priv(dev); 1214 1215 if (qidx >= MAX_SND_QUEUES_PER_QS) 1216 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1217 1218 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1219 1220 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1221 } 1222 1223 static int 1224 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1225 { 1226 struct nicvf *nic = nicvf_pmd_priv(dev); 1227 1228 if (qidx >= MAX_SND_QUEUES_PER_QS) 1229 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1230 1231 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1232 1233 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1234 } 1235 1236 static inline void 1237 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1238 { 1239 uintptr_t p; 1240 struct rte_mbuf mb_def; 1241 struct nicvf *nic = rxq->nic; 1242 1243 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1245 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1246 offsetof(struct rte_mbuf, data_off) != 2); 1247 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1248 offsetof(struct rte_mbuf, data_off) != 4); 1249 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1250 offsetof(struct rte_mbuf, data_off) != 6); 1251 RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) - 1252 offsetof(struct nicvf_rxq, 1253 rxq_fastpath_data_start) > 128); 1254 mb_def.nb_segs = 1; 1255 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1256 mb_def.port = rxq->port_id; 1257 rte_mbuf_refcnt_set(&mb_def, 1); 1258 1259 /* Prevent compiler reordering: rearm_data covers previous fields */ 1260 rte_compiler_barrier(); 1261 p = (uintptr_t)&mb_def.rearm_data; 1262 rxq->mbuf_initializer.value = *(uint64_t *)p; 1263 } 1264 1265 static int 1266 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1267 uint16_t nb_desc, unsigned int socket_id, 1268 const struct rte_eth_rxconf *rx_conf, 1269 struct rte_mempool *mp) 1270 { 1271 uint16_t rx_free_thresh; 1272 struct nicvf_rxq *rxq; 1273 struct nicvf *nic = nicvf_pmd_priv(dev); 1274 uint64_t offloads; 1275 uint32_t buffsz; 1276 struct rte_pktmbuf_pool_private *mbp_priv; 1277 1278 PMD_INIT_FUNC_TRACE(); 1279 1280 /* First skip check */ 1281 mbp_priv = rte_mempool_get_priv(mp); 1282 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1283 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1284 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1285 return -EINVAL; 1286 } 1287 1288 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1289 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1290 1291 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1292 1293 /* Socket id check */ 1294 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1295 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1296 socket_id, nic->node); 1297 1298 /* Mempool memory must be contiguous, so must be one memory segment*/ 1299 if (mp->nb_mem_chunks != 1) { 1300 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1301 return -EINVAL; 1302 } 1303 1304 /* Mempool memory must be physically contiguous */ 1305 if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) { 1306 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1307 return -EINVAL; 1308 } 1309 1310 /* Rx deferred start is not supported */ 1311 if (rx_conf->rx_deferred_start) { 1312 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1313 return -EINVAL; 1314 } 1315 1316 /* Roundup nb_desc to available qsize and validate max number of desc */ 1317 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1318 if (nb_desc == 0) { 1319 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1320 return -EINVAL; 1321 } 1322 1323 1324 /* Check rx_free_thresh upper bound */ 1325 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1326 rx_conf->rx_free_thresh : 1327 NICVF_DEFAULT_RX_FREE_THRESH); 1328 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1329 rx_free_thresh >= nb_desc * .75) { 1330 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1331 rx_free_thresh); 1332 return -EINVAL; 1333 } 1334 1335 /* Free memory prior to re-allocation if needed */ 1336 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1337 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1338 nicvf_netdev_qidx(nic, qidx)); 1339 nicvf_dev_rx_queue_release( 1340 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]); 1341 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1342 } 1343 1344 /* Allocate rxq memory */ 1345 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1346 RTE_CACHE_LINE_SIZE, nic->node); 1347 if (rxq == NULL) { 1348 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1349 nicvf_netdev_qidx(nic, qidx)); 1350 return -ENOMEM; 1351 } 1352 1353 rxq->nic = nic; 1354 rxq->pool = mp; 1355 rxq->queue_id = qidx; 1356 rxq->port_id = dev->data->port_id; 1357 rxq->rx_free_thresh = rx_free_thresh; 1358 rxq->rx_drop_en = rx_conf->rx_drop_en; 1359 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1360 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1361 rxq->precharge_cnt = 0; 1362 1363 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1364 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1365 else 1366 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1367 1368 nicvf_rxq_mbuf_setup(rxq); 1369 1370 /* Alloc completion queue */ 1371 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1372 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1373 nicvf_dev_rx_queue_release(rxq); 1374 return -ENOMEM; 1375 } 1376 1377 nicvf_rx_queue_reset(rxq); 1378 1379 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1380 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1381 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1382 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1383 rte_mempool_avail_count(mp), rxq->phys, offloads); 1384 1385 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1386 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1387 RTE_ETH_QUEUE_STATE_STOPPED; 1388 return 0; 1389 } 1390 1391 static int 1392 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1393 { 1394 struct nicvf *nic = nicvf_pmd_priv(dev); 1395 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1396 1397 PMD_INIT_FUNC_TRACE(); 1398 1399 /* Autonegotiation may be disabled */ 1400 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 1401 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 1402 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 1403 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1404 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 1405 1406 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU; 1407 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN; 1408 dev_info->max_rx_queues = 1409 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1410 dev_info->max_tx_queues = 1411 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1412 dev_info->max_mac_addrs = 1; 1413 dev_info->max_vfs = pci_dev->max_vfs; 1414 1415 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1416 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1417 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1418 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1419 1420 dev_info->reta_size = nic->rss_info.rss_size; 1421 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1422 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1423 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1424 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1425 1426 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1427 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1428 .rx_drop_en = 0, 1429 }; 1430 1431 dev_info->default_txconf = (struct rte_eth_txconf) { 1432 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1433 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE | 1434 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1435 DEV_TX_OFFLOAD_UDP_CKSUM | 1436 DEV_TX_OFFLOAD_TCP_CKSUM, 1437 }; 1438 1439 return 0; 1440 } 1441 1442 static nicvf_iova_addr_t 1443 rbdr_rte_mempool_get(void *dev, void *opaque) 1444 { 1445 uint16_t qidx; 1446 uintptr_t mbuf; 1447 struct nicvf_rxq *rxq; 1448 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1449 struct nicvf *nic = (struct nicvf *)opaque; 1450 uint16_t rx_start, rx_end; 1451 1452 /* Get queue ranges for this VF */ 1453 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1454 1455 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1456 rxq = eth_dev->data->rx_queues[qidx]; 1457 /* Maintain equal buffer count across all pools */ 1458 if (rxq->precharge_cnt >= rxq->qlen_mask) 1459 continue; 1460 rxq->precharge_cnt++; 1461 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1462 if (mbuf) 1463 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1464 } 1465 return 0; 1466 } 1467 1468 static int 1469 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1470 { 1471 int ret; 1472 uint16_t qidx, data_off; 1473 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1474 uint64_t mbuf_phys_off = 0; 1475 struct nicvf_rxq *rxq; 1476 struct rte_mbuf *mbuf; 1477 uint16_t rx_start, rx_end; 1478 uint16_t tx_start, tx_end; 1479 int mask; 1480 1481 PMD_INIT_FUNC_TRACE(); 1482 1483 /* Userspace process exited without proper shutdown in last run */ 1484 if (nicvf_qset_rbdr_active(nic, 0)) 1485 nicvf_vf_stop(dev, nic, false); 1486 1487 /* Get queue ranges for this VF */ 1488 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1489 1490 /* 1491 * Thunderx nicvf PMD can support more than one pool per port only when 1492 * 1) Data payload size is same across all the pools in given port 1493 * AND 1494 * 2) All mbuffs in the pools are from the same hugepage 1495 * AND 1496 * 3) Mbuff metadata size is same across all the pools in given port 1497 * 1498 * This is to support existing application that uses multiple pool/port. 1499 * But, the purpose of using multipool for QoS will not be addressed. 1500 * 1501 */ 1502 1503 /* Validate mempool attributes */ 1504 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1505 rxq = dev->data->rx_queues[qidx]; 1506 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1507 mbuf = rte_pktmbuf_alloc(rxq->pool); 1508 if (mbuf == NULL) { 1509 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1510 "pool=%s", 1511 nic->vf_id, qidx, rxq->pool->name); 1512 return -ENOMEM; 1513 } 1514 data_off = nicvf_mbuff_meta_length(mbuf); 1515 data_off += RTE_PKTMBUF_HEADROOM; 1516 rte_pktmbuf_free(mbuf); 1517 1518 if (data_off % RTE_CACHE_LINE_SIZE) { 1519 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1520 rxq->pool->name, data_off, 1521 data_off % RTE_CACHE_LINE_SIZE); 1522 return -EINVAL; 1523 } 1524 rxq->mbuf_phys_off -= data_off; 1525 rxq->mbuf_phys_off -= nic->skip_bytes; 1526 1527 if (mbuf_phys_off == 0) 1528 mbuf_phys_off = rxq->mbuf_phys_off; 1529 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1530 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1531 PRIx64, rxq->pool->name, nic->vf_id, 1532 mbuf_phys_off); 1533 return -EINVAL; 1534 } 1535 } 1536 1537 /* Check the level of buffers in the pool */ 1538 total_rxq_desc = 0; 1539 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1540 rxq = dev->data->rx_queues[qidx]; 1541 /* Count total numbers of rxq descs */ 1542 total_rxq_desc += rxq->qlen_mask + 1; 1543 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1544 exp_buffs *= dev->data->nb_rx_queues; 1545 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1546 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1547 rxq->pool->name, 1548 rte_mempool_avail_count(rxq->pool), 1549 exp_buffs); 1550 return -ENOENT; 1551 } 1552 } 1553 1554 /* Check RBDR desc overflow */ 1555 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1556 if (ret == 0) { 1557 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1558 "VF%d", nic->vf_id); 1559 return -ENOMEM; 1560 } 1561 1562 /* Enable qset */ 1563 ret = nicvf_qset_config(nic); 1564 if (ret) { 1565 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1566 nic->vf_id); 1567 return ret; 1568 } 1569 1570 /* Allocate RBDR and RBDR ring desc */ 1571 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1572 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1573 if (ret) { 1574 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1575 "VF%d", nic->vf_id); 1576 goto qset_reclaim; 1577 } 1578 1579 /* Enable and configure RBDR registers */ 1580 ret = nicvf_qset_rbdr_config(nic, 0); 1581 if (ret) { 1582 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1583 nic->vf_id); 1584 goto qset_rbdr_free; 1585 } 1586 1587 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1588 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1589 total_rxq_desc); 1590 if (ret) { 1591 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1592 nic->vf_id); 1593 goto qset_rbdr_reclaim; 1594 } 1595 1596 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1597 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1598 1599 /* Configure VLAN Strip */ 1600 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 1601 ETH_VLAN_EXTEND_MASK; 1602 ret = nicvf_vlan_offload_config(dev, mask); 1603 1604 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1605 * to the 64bit memory address. 1606 * The alignment creates a hole in mbuf(between the end of headroom and 1607 * packet data start). The new revision of the HW provides an option to 1608 * disable the L3 alignment feature and make mbuf layout looks 1609 * more like other NICs. For better application compatibility, disabling 1610 * l3 alignment feature on the hardware revisions it supports 1611 */ 1612 nicvf_apad_config(nic, false); 1613 1614 /* Get queue ranges for this VF */ 1615 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1616 1617 /* Configure TX queues */ 1618 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1619 ret = nicvf_vf_start_tx_queue(dev, nic, 1620 qidx % MAX_SND_QUEUES_PER_QS); 1621 if (ret) 1622 goto start_txq_error; 1623 } 1624 1625 /* Configure RX queues */ 1626 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1627 ret = nicvf_vf_start_rx_queue(dev, nic, 1628 qidx % MAX_RCV_QUEUES_PER_QS); 1629 if (ret) 1630 goto start_rxq_error; 1631 } 1632 1633 if (!nic->sqs_mode) { 1634 /* Configure CPI algorithm */ 1635 ret = nicvf_configure_cpi(dev); 1636 if (ret) 1637 goto start_txq_error; 1638 1639 ret = nicvf_mbox_get_rss_size(nic); 1640 if (ret) { 1641 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1642 goto qset_rss_error; 1643 } 1644 1645 /* Configure RSS */ 1646 ret = nicvf_configure_rss(dev); 1647 if (ret) 1648 goto qset_rss_error; 1649 } 1650 1651 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1652 nicvf_mbox_cfg_done(nic); 1653 return 0; 1654 1655 qset_rss_error: 1656 nicvf_rss_term(nic); 1657 start_rxq_error: 1658 for (qidx = rx_start; qidx <= rx_end; qidx++) 1659 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1660 start_txq_error: 1661 for (qidx = tx_start; qidx <= tx_end; qidx++) 1662 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1663 qset_rbdr_reclaim: 1664 nicvf_qset_rbdr_reclaim(nic, 0); 1665 nicvf_rbdr_release_mbufs(dev, nic); 1666 qset_rbdr_free: 1667 if (nic->rbdr) { 1668 rte_free(nic->rbdr); 1669 nic->rbdr = NULL; 1670 } 1671 qset_reclaim: 1672 nicvf_qset_reclaim(nic); 1673 return ret; 1674 } 1675 1676 static int 1677 nicvf_dev_start(struct rte_eth_dev *dev) 1678 { 1679 uint16_t qidx; 1680 int ret; 1681 size_t i; 1682 struct nicvf *nic = nicvf_pmd_priv(dev); 1683 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1684 uint16_t mtu; 1685 uint32_t buffsz = 0, rbdrsz = 0; 1686 struct rte_pktmbuf_pool_private *mbp_priv; 1687 struct nicvf_rxq *rxq; 1688 1689 PMD_INIT_FUNC_TRACE(); 1690 1691 /* This function must be called for a primary device */ 1692 assert_primary(nic); 1693 1694 /* Validate RBDR buff size */ 1695 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1696 rxq = dev->data->rx_queues[qidx]; 1697 mbp_priv = rte_mempool_get_priv(rxq->pool); 1698 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1699 if (buffsz % 128) { 1700 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1701 return -EINVAL; 1702 } 1703 if (rbdrsz == 0) 1704 rbdrsz = buffsz; 1705 if (rbdrsz != buffsz) { 1706 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1707 qidx, rbdrsz, buffsz); 1708 return -EINVAL; 1709 } 1710 } 1711 1712 /* Configure loopback */ 1713 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1714 if (ret) { 1715 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1716 return ret; 1717 } 1718 1719 /* Reset all statistics counters attached to this port */ 1720 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1721 if (ret) { 1722 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1723 return ret; 1724 } 1725 1726 /* Setup scatter mode if needed by jumbo */ 1727 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1728 2 * VLAN_TAG_SIZE > buffsz) 1729 dev->data->scattered_rx = 1; 1730 if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0) 1731 dev->data->scattered_rx = 1; 1732 1733 /* Setup MTU based on max_rx_pkt_len or default */ 1734 mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ? 1735 dev->data->dev_conf.rxmode.max_rx_pkt_len 1736 - RTE_ETHER_HDR_LEN : RTE_ETHER_MTU; 1737 1738 if (nicvf_dev_set_mtu(dev, mtu)) { 1739 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1740 return -EBUSY; 1741 } 1742 1743 ret = nicvf_vf_start(dev, nic, rbdrsz); 1744 if (ret != 0) 1745 return ret; 1746 1747 for (i = 0; i < nic->sqs_count; i++) { 1748 assert(nic->snicvf[i]); 1749 1750 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1751 if (ret != 0) 1752 return ret; 1753 } 1754 1755 /* Configure callbacks based on offloads */ 1756 nicvf_set_tx_function(dev); 1757 nicvf_set_rx_function(dev); 1758 1759 return 0; 1760 } 1761 1762 static void 1763 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1764 { 1765 size_t i; 1766 int ret; 1767 struct nicvf *nic = nicvf_pmd_priv(dev); 1768 1769 PMD_INIT_FUNC_TRACE(); 1770 dev->data->dev_started = 0; 1771 1772 /* Teardown secondary vf first */ 1773 for (i = 0; i < nic->sqs_count; i++) { 1774 if (!nic->snicvf[i]) 1775 continue; 1776 1777 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1778 } 1779 1780 /* Stop the primary VF now */ 1781 nicvf_vf_stop(dev, nic, cleanup); 1782 1783 /* Disable loopback */ 1784 ret = nicvf_loopback_config(nic, 0); 1785 if (ret) 1786 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1787 1788 /* Reclaim CPI configuration */ 1789 ret = nicvf_mbox_config_cpi(nic, 0); 1790 if (ret) 1791 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1792 } 1793 1794 static int 1795 nicvf_dev_stop(struct rte_eth_dev *dev) 1796 { 1797 PMD_INIT_FUNC_TRACE(); 1798 1799 nicvf_dev_stop_cleanup(dev, false); 1800 1801 return 0; 1802 } 1803 1804 static void 1805 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1806 { 1807 int ret; 1808 uint16_t qidx; 1809 uint16_t tx_start, tx_end; 1810 uint16_t rx_start, rx_end; 1811 1812 PMD_INIT_FUNC_TRACE(); 1813 1814 if (cleanup) { 1815 /* Let PF make the BGX's RX and TX switches to OFF position */ 1816 nicvf_mbox_shutdown(nic); 1817 } 1818 1819 /* Disable VLAN Strip */ 1820 nicvf_vlan_hw_strip(nic, 0); 1821 1822 /* Get queue ranges for this VF */ 1823 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1824 1825 for (qidx = tx_start; qidx <= tx_end; qidx++) 1826 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1827 1828 /* Get queue ranges for this VF */ 1829 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1830 1831 /* Reclaim rq */ 1832 for (qidx = rx_start; qidx <= rx_end; qidx++) 1833 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1834 1835 /* Reclaim RBDR */ 1836 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1837 if (ret) 1838 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1839 1840 /* Move all charged buffers in RBDR back to pool */ 1841 if (nic->rbdr != NULL) 1842 nicvf_rbdr_release_mbufs(dev, nic); 1843 1844 /* Disable qset */ 1845 ret = nicvf_qset_reclaim(nic); 1846 if (ret) 1847 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1848 1849 /* Disable all interrupts */ 1850 nicvf_disable_all_interrupts(nic); 1851 1852 /* Free RBDR SW structure */ 1853 if (nic->rbdr) { 1854 rte_free(nic->rbdr); 1855 nic->rbdr = NULL; 1856 } 1857 } 1858 1859 static int 1860 nicvf_dev_close(struct rte_eth_dev *dev) 1861 { 1862 size_t i; 1863 struct nicvf *nic = nicvf_pmd_priv(dev); 1864 1865 PMD_INIT_FUNC_TRACE(); 1866 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1867 return 0; 1868 1869 nicvf_dev_stop_cleanup(dev, true); 1870 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1871 1872 for (i = 0; i < nic->sqs_count; i++) { 1873 if (!nic->snicvf[i]) 1874 continue; 1875 1876 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); 1877 } 1878 1879 return 0; 1880 } 1881 1882 static int 1883 nicvf_request_sqs(struct nicvf *nic) 1884 { 1885 size_t i; 1886 1887 assert_primary(nic); 1888 assert(nic->sqs_count > 0); 1889 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1890 1891 /* Set no of Rx/Tx queues in each of the SQsets */ 1892 for (i = 0; i < nic->sqs_count; i++) { 1893 if (nicvf_svf_empty()) 1894 rte_panic("Cannot assign sufficient number of " 1895 "secondary queues to primary VF%" PRIu8 "\n", 1896 nic->vf_id); 1897 1898 nic->snicvf[i] = nicvf_svf_pop(); 1899 nic->snicvf[i]->sqs_id = i; 1900 } 1901 1902 return nicvf_mbox_request_sqs(nic); 1903 } 1904 1905 static int 1906 nicvf_dev_configure(struct rte_eth_dev *dev) 1907 { 1908 struct rte_eth_dev_data *data = dev->data; 1909 struct rte_eth_conf *conf = &data->dev_conf; 1910 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1911 struct rte_eth_txmode *txmode = &conf->txmode; 1912 struct nicvf *nic = nicvf_pmd_priv(dev); 1913 uint8_t cqcount; 1914 1915 PMD_INIT_FUNC_TRACE(); 1916 1917 if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG) 1918 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1919 1920 if (!rte_eal_has_hugepages()) { 1921 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1922 return -EINVAL; 1923 } 1924 1925 if (txmode->mq_mode) { 1926 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1927 return -EINVAL; 1928 } 1929 1930 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1931 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1932 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1933 return -EINVAL; 1934 } 1935 1936 if (rxmode->split_hdr_size) { 1937 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1938 return -EINVAL; 1939 } 1940 1941 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1942 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1943 return -EINVAL; 1944 } 1945 1946 if (conf->dcb_capability_en) { 1947 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1948 return -EINVAL; 1949 } 1950 1951 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1952 PMD_INIT_LOG(INFO, "Flow director not supported"); 1953 return -EINVAL; 1954 } 1955 1956 assert_primary(nic); 1957 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1958 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1959 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1960 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1961 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1962 } else { 1963 nic->sqs_count = 0; 1964 } 1965 1966 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1967 1968 if (nic->sqs_count > 0) { 1969 if (nicvf_request_sqs(nic)) { 1970 rte_panic("Cannot assign sufficient number of " 1971 "secondary queues to PORT%d VF%" PRIu8 "\n", 1972 dev->data->port_id, nic->vf_id); 1973 } 1974 } 1975 1976 if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) 1977 nic->offload_cksum = 1; 1978 1979 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1980 dev->data->port_id, nicvf_hw_cap(nic)); 1981 1982 return 0; 1983 } 1984 1985 static int 1986 nicvf_dev_set_link_up(struct rte_eth_dev *dev) 1987 { 1988 struct nicvf *nic = nicvf_pmd_priv(dev); 1989 int rc, i; 1990 1991 rc = nicvf_mbox_set_link_up_down(nic, true); 1992 if (rc) 1993 goto done; 1994 1995 /* Start tx queues */ 1996 for (i = 0; i < dev->data->nb_tx_queues; i++) 1997 nicvf_dev_tx_queue_start(dev, i); 1998 1999 done: 2000 return rc; 2001 } 2002 2003 static int 2004 nicvf_dev_set_link_down(struct rte_eth_dev *dev) 2005 { 2006 struct nicvf *nic = nicvf_pmd_priv(dev); 2007 int i; 2008 2009 /* Stop tx queues */ 2010 for (i = 0; i < dev->data->nb_tx_queues; i++) 2011 nicvf_dev_tx_queue_stop(dev, i); 2012 2013 return nicvf_mbox_set_link_up_down(nic, false); 2014 } 2015 2016 /* Initialize and register driver with DPDK Application */ 2017 static const struct eth_dev_ops nicvf_eth_dev_ops = { 2018 .dev_configure = nicvf_dev_configure, 2019 .dev_start = nicvf_dev_start, 2020 .dev_stop = nicvf_dev_stop, 2021 .link_update = nicvf_dev_link_update, 2022 .dev_close = nicvf_dev_close, 2023 .stats_get = nicvf_dev_stats_get, 2024 .stats_reset = nicvf_dev_stats_reset, 2025 .promiscuous_enable = nicvf_dev_promisc_enable, 2026 .dev_infos_get = nicvf_dev_info_get, 2027 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 2028 .mtu_set = nicvf_dev_set_mtu, 2029 .vlan_offload_set = nicvf_vlan_offload_set, 2030 .reta_update = nicvf_dev_reta_update, 2031 .reta_query = nicvf_dev_reta_query, 2032 .rss_hash_update = nicvf_dev_rss_hash_update, 2033 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2034 .rx_queue_start = nicvf_dev_rx_queue_start, 2035 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2036 .tx_queue_start = nicvf_dev_tx_queue_start, 2037 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2038 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2039 .rx_queue_release = nicvf_dev_rx_queue_release, 2040 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2041 .tx_queue_release = nicvf_dev_tx_queue_release, 2042 .dev_set_link_up = nicvf_dev_set_link_up, 2043 .dev_set_link_down = nicvf_dev_set_link_down, 2044 .get_reg = nicvf_dev_get_regs, 2045 }; 2046 2047 static int 2048 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2049 { 2050 struct rte_eth_rxmode *rxmode; 2051 struct nicvf *nic = nicvf_pmd_priv(dev); 2052 rxmode = &dev->data->dev_conf.rxmode; 2053 if (mask & ETH_VLAN_STRIP_MASK) { 2054 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2055 nicvf_vlan_hw_strip(nic, true); 2056 else 2057 nicvf_vlan_hw_strip(nic, false); 2058 } 2059 2060 return 0; 2061 } 2062 2063 static int 2064 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2065 { 2066 nicvf_vlan_offload_config(dev, mask); 2067 2068 return 0; 2069 } 2070 2071 static inline int 2072 nicvf_set_first_skip(struct rte_eth_dev *dev) 2073 { 2074 int bytes_to_skip = 0; 2075 int ret = 0; 2076 unsigned int i; 2077 struct rte_kvargs *kvlist; 2078 static const char *const skip[] = { 2079 SKIP_DATA_BYTES, 2080 NULL}; 2081 struct nicvf *nic = nicvf_pmd_priv(dev); 2082 2083 if (!dev->device->devargs) { 2084 nicvf_first_skip_config(nic, 0); 2085 return ret; 2086 } 2087 2088 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2089 if (!kvlist) 2090 return -EINVAL; 2091 2092 if (kvlist->count == 0) 2093 goto exit; 2094 2095 for (i = 0; i != kvlist->count; ++i) { 2096 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2097 2098 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2099 bytes_to_skip = atoi(pair->value); 2100 } 2101 2102 /*128 bytes amounts to one cache line*/ 2103 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2104 if (!(bytes_to_skip % 8)) { 2105 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2106 nic->skip_bytes = bytes_to_skip; 2107 goto kvlist_free; 2108 } else { 2109 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2110 ret = -EINVAL; 2111 goto exit; 2112 } 2113 } else { 2114 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2115 ret = -EINVAL; 2116 goto exit; 2117 } 2118 exit: 2119 nicvf_first_skip_config(nic, 0); 2120 kvlist_free: 2121 rte_kvargs_free(kvlist); 2122 return ret; 2123 } 2124 static int 2125 nicvf_eth_dev_uninit(struct rte_eth_dev *dev) 2126 { 2127 PMD_INIT_FUNC_TRACE(); 2128 nicvf_dev_close(dev); 2129 return 0; 2130 } 2131 static int 2132 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2133 { 2134 int ret; 2135 struct rte_pci_device *pci_dev; 2136 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2137 2138 PMD_INIT_FUNC_TRACE(); 2139 2140 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2141 eth_dev->rx_queue_count = nicvf_dev_rx_queue_count; 2142 2143 /* For secondary processes, the primary has done all the work */ 2144 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2145 if (nic) { 2146 /* Setup callbacks for secondary process */ 2147 nicvf_set_tx_function(eth_dev); 2148 nicvf_set_rx_function(eth_dev); 2149 return 0; 2150 } else { 2151 /* If nic == NULL than it is secondary function 2152 * so ethdev need to be released by caller */ 2153 return ENOTSUP; 2154 } 2155 } 2156 2157 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2158 rte_eth_copy_pci_info(eth_dev, pci_dev); 2159 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2160 2161 nic->device_id = pci_dev->id.device_id; 2162 nic->vendor_id = pci_dev->id.vendor_id; 2163 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2164 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2165 2166 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2167 pci_dev->id.vendor_id, pci_dev->id.device_id, 2168 pci_dev->addr.domain, pci_dev->addr.bus, 2169 pci_dev->addr.devid, pci_dev->addr.function); 2170 2171 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2172 if (!nic->reg_base) { 2173 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2174 ret = -ENODEV; 2175 goto fail; 2176 } 2177 2178 nicvf_disable_all_interrupts(nic); 2179 2180 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2181 if (ret) { 2182 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2183 goto fail; 2184 } 2185 2186 ret = nicvf_mbox_check_pf_ready(nic); 2187 if (ret) { 2188 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2189 goto alarm_fail; 2190 } else { 2191 PMD_INIT_LOG(INFO, 2192 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2193 nic->node, nic->vf_id, 2194 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2195 nic->sqs_mode ? "true" : "false", 2196 nic->loopback_supported ? "true" : "false" 2197 ); 2198 } 2199 2200 ret = nicvf_base_init(nic); 2201 if (ret) { 2202 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2203 goto malloc_fail; 2204 } 2205 2206 if (nic->sqs_mode) { 2207 /* Push nic to stack of secondary vfs */ 2208 nicvf_svf_push(nic); 2209 2210 /* Steal nic pointer from the device for further reuse */ 2211 eth_dev->data->dev_private = NULL; 2212 2213 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2214 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2215 if (ret) { 2216 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2217 goto fail; 2218 } 2219 2220 /* Detach port by returning positive error number */ 2221 return ENOTSUP; 2222 } 2223 2224 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2225 RTE_ETHER_ADDR_LEN, 0); 2226 if (eth_dev->data->mac_addrs == NULL) { 2227 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2228 ret = -ENOMEM; 2229 goto alarm_fail; 2230 } 2231 if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr)) 2232 rte_eth_random_addr(&nic->mac_addr[0]); 2233 2234 rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr, 2235 ð_dev->data->mac_addrs[0]); 2236 2237 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2238 if (ret) { 2239 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2240 goto malloc_fail; 2241 } 2242 2243 ret = nicvf_set_first_skip(eth_dev); 2244 if (ret) { 2245 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2246 goto malloc_fail; 2247 } 2248 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 2249 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2250 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2251 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2252 2253 return 0; 2254 2255 malloc_fail: 2256 rte_free(eth_dev->data->mac_addrs); 2257 eth_dev->data->mac_addrs = NULL; 2258 alarm_fail: 2259 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2260 fail: 2261 return ret; 2262 } 2263 2264 static const struct rte_pci_id pci_id_nicvf_map[] = { 2265 { 2266 .class_id = RTE_CLASS_ANY_ID, 2267 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2268 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2269 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2270 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2271 }, 2272 { 2273 .class_id = RTE_CLASS_ANY_ID, 2274 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2275 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2276 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2277 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2278 }, 2279 { 2280 .class_id = RTE_CLASS_ANY_ID, 2281 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2282 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2283 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2284 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2285 }, 2286 { 2287 .class_id = RTE_CLASS_ANY_ID, 2288 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2289 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2290 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2291 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2292 }, 2293 { 2294 .vendor_id = 0, 2295 }, 2296 }; 2297 2298 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2299 struct rte_pci_device *pci_dev) 2300 { 2301 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2302 nicvf_eth_dev_init); 2303 } 2304 2305 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2306 { 2307 return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit); 2308 } 2309 2310 static struct rte_pci_driver rte_nicvf_pmd = { 2311 .id_table = pci_id_nicvf_map, 2312 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2313 RTE_PCI_DRV_INTR_LSC, 2314 .probe = nicvf_eth_pci_probe, 2315 .remove = nicvf_eth_pci_remove, 2316 }; 2317 2318 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2319 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2320 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2321 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2322