1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <rte_dev.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <rte_ethdev_driver.h> 27 #include <rte_ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <rte_bus_pci.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 int nicvf_logtype_mbox; 48 int nicvf_logtype_init; 49 int nicvf_logtype_driver; 50 51 static void nicvf_dev_stop(struct rte_eth_dev *dev); 52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 54 bool cleanup); 55 56 RTE_INIT(nicvf_init_log) 57 { 58 nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox"); 59 if (nicvf_logtype_mbox >= 0) 60 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE); 61 62 nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init"); 63 if (nicvf_logtype_init >= 0) 64 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE); 65 66 nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver"); 67 if (nicvf_logtype_driver >= 0) 68 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE); 69 } 70 71 static void 72 nicvf_link_status_update(struct nicvf *nic, 73 struct rte_eth_link *link) 74 { 75 memset(link, 0, sizeof(*link)); 76 77 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 78 79 if (nic->duplex == NICVF_HALF_DUPLEX) 80 link->link_duplex = ETH_LINK_HALF_DUPLEX; 81 else if (nic->duplex == NICVF_FULL_DUPLEX) 82 link->link_duplex = ETH_LINK_FULL_DUPLEX; 83 link->link_speed = nic->speed; 84 link->link_autoneg = ETH_LINK_AUTONEG; 85 } 86 87 static void 88 nicvf_interrupt(void *arg) 89 { 90 struct rte_eth_dev *dev = arg; 91 struct nicvf *nic = nicvf_pmd_priv(dev); 92 struct rte_eth_link link; 93 94 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 95 if (dev->data->dev_conf.intr_conf.lsc) { 96 nicvf_link_status_update(nic, &link); 97 rte_eth_linkstatus_set(dev, &link); 98 99 _rte_eth_dev_callback_process(dev, 100 RTE_ETH_EVENT_INTR_LSC, 101 NULL); 102 } 103 } 104 105 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 106 nicvf_interrupt, dev); 107 } 108 109 static void 110 nicvf_vf_interrupt(void *arg) 111 { 112 struct nicvf *nic = arg; 113 114 nicvf_reg_poll_interrupts(nic); 115 116 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 117 nicvf_vf_interrupt, nic); 118 } 119 120 static int 121 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 122 { 123 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 124 } 125 126 static int 127 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 128 { 129 return rte_eal_alarm_cancel(fn, arg); 130 } 131 132 /* 133 * Return 0 means link status changed, -1 means not changed 134 */ 135 static int 136 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 137 { 138 #define CHECK_INTERVAL 100 /* 100ms */ 139 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 140 struct rte_eth_link link; 141 struct nicvf *nic = nicvf_pmd_priv(dev); 142 int i; 143 144 PMD_INIT_FUNC_TRACE(); 145 146 if (wait_to_complete) { 147 /* rte_eth_link_get() might need to wait up to 9 seconds */ 148 for (i = 0; i < MAX_CHECK_TIME; i++) { 149 nicvf_link_status_update(nic, &link); 150 if (link.link_status == ETH_LINK_UP) 151 break; 152 rte_delay_ms(CHECK_INTERVAL); 153 } 154 } else { 155 nicvf_link_status_update(nic, &link); 156 } 157 158 return rte_eth_linkstatus_set(dev, &link); 159 } 160 161 static int 162 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 163 { 164 struct nicvf *nic = nicvf_pmd_priv(dev); 165 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 166 size_t i; 167 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 168 169 PMD_INIT_FUNC_TRACE(); 170 171 if (frame_size > NIC_HW_MAX_FRS) 172 return -EINVAL; 173 174 if (frame_size < NIC_HW_MIN_FRS) 175 return -EINVAL; 176 177 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 178 179 /* 180 * Refuse mtu that requires the support of scattered packets 181 * when this feature has not been enabled before. 182 */ 183 if (dev->data->dev_started && !dev->data->scattered_rx && 184 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 185 return -EINVAL; 186 187 /* check <seg size> * <max_seg> >= max_frame */ 188 if (dev->data->scattered_rx && 189 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 190 return -EINVAL; 191 192 if (frame_size > ETHER_MAX_LEN) 193 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 194 else 195 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 196 197 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 198 return -EINVAL; 199 200 /* Update max_rx_pkt_len */ 201 rxmode->max_rx_pkt_len = mtu + ETHER_HDR_LEN; 202 nic->mtu = mtu; 203 204 for (i = 0; i < nic->sqs_count; i++) 205 nic->snicvf[i]->mtu = mtu; 206 207 return 0; 208 } 209 210 static int 211 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 212 { 213 uint64_t *data = regs->data; 214 struct nicvf *nic = nicvf_pmd_priv(dev); 215 216 if (data == NULL) { 217 regs->length = nicvf_reg_get_count(); 218 regs->width = THUNDERX_REG_BYTES; 219 return 0; 220 } 221 222 /* Support only full register dump */ 223 if ((regs->length == 0) || 224 (regs->length == (uint32_t)nicvf_reg_get_count())) { 225 regs->version = nic->vendor_id << 16 | nic->device_id; 226 nicvf_reg_dump(nic, data); 227 return 0; 228 } 229 return -ENOTSUP; 230 } 231 232 static int 233 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 234 { 235 uint16_t qidx; 236 struct nicvf_hw_rx_qstats rx_qstats; 237 struct nicvf_hw_tx_qstats tx_qstats; 238 struct nicvf_hw_stats port_stats; 239 struct nicvf *nic = nicvf_pmd_priv(dev); 240 uint16_t rx_start, rx_end; 241 uint16_t tx_start, tx_end; 242 size_t i; 243 244 /* RX queue indices for the first VF */ 245 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 246 247 /* Reading per RX ring stats */ 248 for (qidx = rx_start; qidx <= rx_end; qidx++) { 249 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 250 break; 251 252 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 253 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 254 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 255 } 256 257 /* TX queue indices for the first VF */ 258 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 259 260 /* Reading per TX ring stats */ 261 for (qidx = tx_start; qidx <= tx_end; qidx++) { 262 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 263 break; 264 265 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 266 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 267 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 268 } 269 270 for (i = 0; i < nic->sqs_count; i++) { 271 struct nicvf *snic = nic->snicvf[i]; 272 273 if (snic == NULL) 274 break; 275 276 /* RX queue indices for a secondary VF */ 277 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 278 279 /* Reading per RX ring stats */ 280 for (qidx = rx_start; qidx <= rx_end; qidx++) { 281 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 282 break; 283 284 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 285 qidx % MAX_RCV_QUEUES_PER_QS); 286 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 287 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 288 } 289 290 /* TX queue indices for a secondary VF */ 291 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 292 /* Reading per TX ring stats */ 293 for (qidx = tx_start; qidx <= tx_end; qidx++) { 294 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 295 break; 296 297 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 298 qidx % MAX_SND_QUEUES_PER_QS); 299 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 300 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 301 } 302 } 303 304 nicvf_hw_get_stats(nic, &port_stats); 305 stats->ibytes = port_stats.rx_bytes; 306 stats->ipackets = port_stats.rx_ucast_frames; 307 stats->ipackets += port_stats.rx_bcast_frames; 308 stats->ipackets += port_stats.rx_mcast_frames; 309 stats->ierrors = port_stats.rx_l2_errors; 310 stats->imissed = port_stats.rx_drop_red; 311 stats->imissed += port_stats.rx_drop_overrun; 312 stats->imissed += port_stats.rx_drop_bcast; 313 stats->imissed += port_stats.rx_drop_mcast; 314 stats->imissed += port_stats.rx_drop_l3_bcast; 315 stats->imissed += port_stats.rx_drop_l3_mcast; 316 317 stats->obytes = port_stats.tx_bytes_ok; 318 stats->opackets = port_stats.tx_ucast_frames_ok; 319 stats->opackets += port_stats.tx_bcast_frames_ok; 320 stats->opackets += port_stats.tx_mcast_frames_ok; 321 stats->oerrors = port_stats.tx_drops; 322 323 return 0; 324 } 325 326 static const uint32_t * 327 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 328 { 329 size_t copied; 330 static uint32_t ptypes[32]; 331 struct nicvf *nic = nicvf_pmd_priv(dev); 332 static const uint32_t ptypes_common[] = { 333 RTE_PTYPE_L3_IPV4, 334 RTE_PTYPE_L3_IPV4_EXT, 335 RTE_PTYPE_L3_IPV6, 336 RTE_PTYPE_L3_IPV6_EXT, 337 RTE_PTYPE_L4_TCP, 338 RTE_PTYPE_L4_UDP, 339 RTE_PTYPE_L4_FRAG, 340 }; 341 static const uint32_t ptypes_tunnel[] = { 342 RTE_PTYPE_TUNNEL_GRE, 343 RTE_PTYPE_TUNNEL_GENEVE, 344 RTE_PTYPE_TUNNEL_VXLAN, 345 RTE_PTYPE_TUNNEL_NVGRE, 346 }; 347 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 348 349 copied = sizeof(ptypes_common); 350 memcpy(ptypes, ptypes_common, copied); 351 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 352 memcpy((char *)ptypes + copied, ptypes_tunnel, 353 sizeof(ptypes_tunnel)); 354 copied += sizeof(ptypes_tunnel); 355 } 356 357 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 358 if (dev->rx_pkt_burst == nicvf_recv_pkts || 359 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg) 360 return ptypes; 361 362 return NULL; 363 } 364 365 static void 366 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 367 { 368 int i; 369 uint16_t rxqs = 0, txqs = 0; 370 struct nicvf *nic = nicvf_pmd_priv(dev); 371 uint16_t rx_start, rx_end; 372 uint16_t tx_start, tx_end; 373 374 /* Reset all primary nic counters */ 375 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 376 for (i = rx_start; i <= rx_end; i++) 377 rxqs |= (0x3 << (i * 2)); 378 379 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 380 for (i = tx_start; i <= tx_end; i++) 381 txqs |= (0x3 << (i * 2)); 382 383 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 384 385 /* Reset secondary nic queue counters */ 386 for (i = 0; i < nic->sqs_count; i++) { 387 struct nicvf *snic = nic->snicvf[i]; 388 if (snic == NULL) 389 break; 390 391 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 392 for (i = rx_start; i <= rx_end; i++) 393 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 394 395 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 396 for (i = tx_start; i <= tx_end; i++) 397 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 398 399 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 400 } 401 } 402 403 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 404 static void 405 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 406 { 407 } 408 409 static inline uint64_t 410 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 411 { 412 uint64_t nic_rss = 0; 413 414 if (ethdev_rss & ETH_RSS_IPV4) 415 nic_rss |= RSS_IP_ENA; 416 417 if (ethdev_rss & ETH_RSS_IPV6) 418 nic_rss |= RSS_IP_ENA; 419 420 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 421 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 422 423 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 424 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 425 426 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 427 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 428 429 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 430 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 431 432 if (ethdev_rss & ETH_RSS_PORT) 433 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 434 435 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 436 if (ethdev_rss & ETH_RSS_VXLAN) 437 nic_rss |= RSS_TUN_VXLAN_ENA; 438 439 if (ethdev_rss & ETH_RSS_GENEVE) 440 nic_rss |= RSS_TUN_GENEVE_ENA; 441 442 if (ethdev_rss & ETH_RSS_NVGRE) 443 nic_rss |= RSS_TUN_NVGRE_ENA; 444 } 445 446 return nic_rss; 447 } 448 449 static inline uint64_t 450 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 451 { 452 uint64_t ethdev_rss = 0; 453 454 if (nic_rss & RSS_IP_ENA) 455 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 456 457 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 458 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 459 ETH_RSS_NONFRAG_IPV6_TCP); 460 461 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 462 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 463 ETH_RSS_NONFRAG_IPV6_UDP); 464 465 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 466 ethdev_rss |= ETH_RSS_PORT; 467 468 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 469 if (nic_rss & RSS_TUN_VXLAN_ENA) 470 ethdev_rss |= ETH_RSS_VXLAN; 471 472 if (nic_rss & RSS_TUN_GENEVE_ENA) 473 ethdev_rss |= ETH_RSS_GENEVE; 474 475 if (nic_rss & RSS_TUN_NVGRE_ENA) 476 ethdev_rss |= ETH_RSS_NVGRE; 477 } 478 return ethdev_rss; 479 } 480 481 static int 482 nicvf_dev_reta_query(struct rte_eth_dev *dev, 483 struct rte_eth_rss_reta_entry64 *reta_conf, 484 uint16_t reta_size) 485 { 486 struct nicvf *nic = nicvf_pmd_priv(dev); 487 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 488 int ret, i, j; 489 490 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 491 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 492 "(%d) doesn't match the number hardware can supported " 493 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 494 return -EINVAL; 495 } 496 497 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 498 if (ret) 499 return ret; 500 501 /* Copy RETA table */ 502 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 503 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 504 if ((reta_conf[i].mask >> j) & 0x01) 505 reta_conf[i].reta[j] = tbl[j]; 506 } 507 508 return 0; 509 } 510 511 static int 512 nicvf_dev_reta_update(struct rte_eth_dev *dev, 513 struct rte_eth_rss_reta_entry64 *reta_conf, 514 uint16_t reta_size) 515 { 516 struct nicvf *nic = nicvf_pmd_priv(dev); 517 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 518 int ret, i, j; 519 520 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 521 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 522 "(%d) doesn't match the number hardware can supported " 523 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 524 return -EINVAL; 525 } 526 527 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 528 if (ret) 529 return ret; 530 531 /* Copy RETA table */ 532 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 533 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 534 if ((reta_conf[i].mask >> j) & 0x01) 535 tbl[j] = reta_conf[i].reta[j]; 536 } 537 538 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 539 } 540 541 static int 542 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 543 struct rte_eth_rss_conf *rss_conf) 544 { 545 struct nicvf *nic = nicvf_pmd_priv(dev); 546 547 if (rss_conf->rss_key) 548 nicvf_rss_get_key(nic, rss_conf->rss_key); 549 550 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 551 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 552 return 0; 553 } 554 555 static int 556 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 557 struct rte_eth_rss_conf *rss_conf) 558 { 559 struct nicvf *nic = nicvf_pmd_priv(dev); 560 uint64_t nic_rss; 561 562 if (rss_conf->rss_key && 563 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 564 RTE_LOG(ERR, PMD, "Hash key size mismatch %d", 565 rss_conf->rss_key_len); 566 return -EINVAL; 567 } 568 569 if (rss_conf->rss_key) 570 nicvf_rss_set_key(nic, rss_conf->rss_key); 571 572 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 573 nicvf_rss_set_cfg(nic, nic_rss); 574 return 0; 575 } 576 577 static int 578 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 579 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 580 { 581 const struct rte_memzone *rz; 582 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 583 584 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 585 nicvf_netdev_qidx(nic, qidx), ring_size, 586 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 587 if (rz == NULL) { 588 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 589 return -ENOMEM; 590 } 591 592 memset(rz->addr, 0, ring_size); 593 594 rxq->phys = rz->iova; 595 rxq->desc = rz->addr; 596 rxq->qlen_mask = desc_cnt - 1; 597 598 return 0; 599 } 600 601 static int 602 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 603 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 604 { 605 const struct rte_memzone *rz; 606 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 607 608 rz = rte_eth_dma_zone_reserve(dev, "sq", 609 nicvf_netdev_qidx(nic, qidx), ring_size, 610 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 611 if (rz == NULL) { 612 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 613 return -ENOMEM; 614 } 615 616 memset(rz->addr, 0, ring_size); 617 618 sq->phys = rz->iova; 619 sq->desc = rz->addr; 620 sq->qlen_mask = desc_cnt - 1; 621 622 return 0; 623 } 624 625 static int 626 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 627 uint32_t desc_cnt, uint32_t buffsz) 628 { 629 struct nicvf_rbdr *rbdr; 630 const struct rte_memzone *rz; 631 uint32_t ring_size; 632 633 assert(nic->rbdr == NULL); 634 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 635 RTE_CACHE_LINE_SIZE, nic->node); 636 if (rbdr == NULL) { 637 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 638 return -ENOMEM; 639 } 640 641 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 642 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 643 nicvf_netdev_qidx(nic, 0), ring_size, 644 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 645 if (rz == NULL) { 646 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 647 return -ENOMEM; 648 } 649 650 memset(rz->addr, 0, ring_size); 651 652 rbdr->phys = rz->iova; 653 rbdr->tail = 0; 654 rbdr->next_tail = 0; 655 rbdr->desc = rz->addr; 656 rbdr->buffsz = buffsz; 657 rbdr->qlen_mask = desc_cnt - 1; 658 rbdr->rbdr_status = 659 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 660 rbdr->rbdr_door = 661 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 662 663 nic->rbdr = rbdr; 664 return 0; 665 } 666 667 static void 668 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 669 nicvf_iova_addr_t phy) 670 { 671 uint16_t qidx; 672 void *obj; 673 struct nicvf_rxq *rxq; 674 uint16_t rx_start, rx_end; 675 676 /* Get queue ranges for this VF */ 677 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 678 679 for (qidx = rx_start; qidx <= rx_end; qidx++) { 680 rxq = dev->data->rx_queues[qidx]; 681 if (rxq->precharge_cnt) { 682 obj = (void *)nicvf_mbuff_phy2virt(phy, 683 rxq->mbuf_phys_off); 684 rte_mempool_put(rxq->pool, obj); 685 rxq->precharge_cnt--; 686 break; 687 } 688 } 689 } 690 691 static inline void 692 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 693 { 694 uint32_t qlen_mask, head; 695 struct rbdr_entry_t *entry; 696 struct nicvf_rbdr *rbdr = nic->rbdr; 697 698 qlen_mask = rbdr->qlen_mask; 699 head = rbdr->head; 700 while (head != rbdr->tail) { 701 entry = rbdr->desc + head; 702 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 703 head++; 704 head = head & qlen_mask; 705 } 706 } 707 708 static inline void 709 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 710 { 711 uint32_t head; 712 713 head = txq->head; 714 while (head != txq->tail) { 715 if (txq->txbuffs[head]) { 716 rte_pktmbuf_free_seg(txq->txbuffs[head]); 717 txq->txbuffs[head] = NULL; 718 } 719 head++; 720 head = head & txq->qlen_mask; 721 } 722 } 723 724 static void 725 nicvf_tx_queue_reset(struct nicvf_txq *txq) 726 { 727 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 728 729 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 730 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 731 txq->tail = 0; 732 txq->head = 0; 733 txq->xmit_bufs = 0; 734 } 735 736 static inline int 737 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 738 uint16_t qidx) 739 { 740 struct nicvf_txq *txq; 741 int ret; 742 743 assert(qidx < MAX_SND_QUEUES_PER_QS); 744 745 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 746 RTE_ETH_QUEUE_STATE_STARTED) 747 return 0; 748 749 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 750 txq->pool = NULL; 751 ret = nicvf_qset_sq_config(nic, qidx, txq); 752 if (ret) { 753 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 754 nic->vf_id, qidx, ret); 755 goto config_sq_error; 756 } 757 758 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 759 RTE_ETH_QUEUE_STATE_STARTED; 760 return ret; 761 762 config_sq_error: 763 nicvf_qset_sq_reclaim(nic, qidx); 764 return ret; 765 } 766 767 static inline int 768 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 769 uint16_t qidx) 770 { 771 struct nicvf_txq *txq; 772 int ret; 773 774 assert(qidx < MAX_SND_QUEUES_PER_QS); 775 776 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 777 RTE_ETH_QUEUE_STATE_STOPPED) 778 return 0; 779 780 ret = nicvf_qset_sq_reclaim(nic, qidx); 781 if (ret) 782 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 783 nic->vf_id, qidx, ret); 784 785 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 786 nicvf_tx_queue_release_mbufs(txq); 787 nicvf_tx_queue_reset(txq); 788 789 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 790 RTE_ETH_QUEUE_STATE_STOPPED; 791 return ret; 792 } 793 794 static inline int 795 nicvf_configure_cpi(struct rte_eth_dev *dev) 796 { 797 struct nicvf *nic = nicvf_pmd_priv(dev); 798 uint16_t qidx, qcnt; 799 int ret; 800 801 /* Count started rx queues */ 802 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 803 if (dev->data->rx_queue_state[qidx] == 804 RTE_ETH_QUEUE_STATE_STARTED) 805 qcnt++; 806 807 nic->cpi_alg = CPI_ALG_NONE; 808 ret = nicvf_mbox_config_cpi(nic, qcnt); 809 if (ret) 810 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 811 812 return ret; 813 } 814 815 static inline int 816 nicvf_configure_rss(struct rte_eth_dev *dev) 817 { 818 struct nicvf *nic = nicvf_pmd_priv(dev); 819 uint64_t rsshf; 820 int ret = -EINVAL; 821 822 rsshf = nicvf_rss_ethdev_to_nic(nic, 823 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 824 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 825 dev->data->dev_conf.rxmode.mq_mode, 826 dev->data->nb_rx_queues, 827 dev->data->dev_conf.lpbk_mode, rsshf); 828 829 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 830 ret = nicvf_rss_term(nic); 831 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 832 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 833 if (ret) 834 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 835 836 return ret; 837 } 838 839 static int 840 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 841 { 842 struct nicvf *nic = nicvf_pmd_priv(dev); 843 unsigned int idx, qmap_size; 844 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 845 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 846 847 if (nic->cpi_alg != CPI_ALG_NONE) 848 return -EINVAL; 849 850 /* Prepare queue map */ 851 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 852 if (dev->data->rx_queue_state[idx] == 853 RTE_ETH_QUEUE_STATE_STARTED) 854 qmap[qmap_size++] = idx; 855 } 856 857 /* Update default RSS RETA */ 858 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 859 default_reta[idx] = qmap[idx % qmap_size]; 860 861 return nicvf_rss_reta_update(nic, default_reta, 862 NIC_MAX_RSS_IDR_TBL_SIZE); 863 } 864 865 static void 866 nicvf_dev_tx_queue_release(void *sq) 867 { 868 struct nicvf_txq *txq; 869 870 PMD_INIT_FUNC_TRACE(); 871 872 txq = (struct nicvf_txq *)sq; 873 if (txq) { 874 if (txq->txbuffs != NULL) { 875 nicvf_tx_queue_release_mbufs(txq); 876 rte_free(txq->txbuffs); 877 txq->txbuffs = NULL; 878 } 879 rte_free(txq); 880 } 881 } 882 883 static void 884 nicvf_set_tx_function(struct rte_eth_dev *dev) 885 { 886 struct nicvf_txq *txq = NULL; 887 size_t i; 888 bool multiseg = false; 889 890 for (i = 0; i < dev->data->nb_tx_queues; i++) { 891 txq = dev->data->tx_queues[i]; 892 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) { 893 multiseg = true; 894 break; 895 } 896 } 897 898 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 899 if (multiseg) { 900 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 901 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 902 } else { 903 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 904 dev->tx_pkt_burst = nicvf_xmit_pkts; 905 } 906 907 if (!txq) 908 return; 909 910 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 911 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 912 else 913 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 914 } 915 916 static void 917 nicvf_set_rx_function(struct rte_eth_dev *dev) 918 { 919 if (dev->data->scattered_rx) { 920 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback"); 921 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg; 922 } else { 923 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback"); 924 dev->rx_pkt_burst = nicvf_recv_pkts; 925 } 926 } 927 928 static int 929 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 930 uint16_t nb_desc, unsigned int socket_id, 931 const struct rte_eth_txconf *tx_conf) 932 { 933 uint16_t tx_free_thresh; 934 bool is_single_pool; 935 struct nicvf_txq *txq; 936 struct nicvf *nic = nicvf_pmd_priv(dev); 937 uint64_t offloads; 938 939 PMD_INIT_FUNC_TRACE(); 940 941 if (qidx >= MAX_SND_QUEUES_PER_QS) 942 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 943 944 qidx = qidx % MAX_SND_QUEUES_PER_QS; 945 946 /* Socket id check */ 947 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 948 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 949 socket_id, nic->node); 950 951 /* Tx deferred start is not supported */ 952 if (tx_conf->tx_deferred_start) { 953 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 954 return -EINVAL; 955 } 956 957 /* Roundup nb_desc to available qsize and validate max number of desc */ 958 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 959 if (nb_desc == 0) { 960 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 961 return -EINVAL; 962 } 963 964 /* Validate tx_free_thresh */ 965 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 966 tx_conf->tx_free_thresh : 967 NICVF_DEFAULT_TX_FREE_THRESH); 968 969 if (tx_free_thresh > (nb_desc) || 970 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 971 PMD_INIT_LOG(ERR, 972 "tx_free_thresh must be less than the number of TX " 973 "descriptors. (tx_free_thresh=%u port=%d " 974 "queue=%d)", (unsigned int)tx_free_thresh, 975 (int)dev->data->port_id, (int)qidx); 976 return -EINVAL; 977 } 978 979 /* Free memory prior to re-allocation if needed. */ 980 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 981 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 982 nicvf_netdev_qidx(nic, qidx)); 983 nicvf_dev_tx_queue_release( 984 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]); 985 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 986 } 987 988 /* Allocating tx queue data structure */ 989 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 990 RTE_CACHE_LINE_SIZE, nic->node); 991 if (txq == NULL) { 992 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 993 nicvf_netdev_qidx(nic, qidx)); 994 return -ENOMEM; 995 } 996 997 txq->nic = nic; 998 txq->queue_id = qidx; 999 txq->tx_free_thresh = tx_free_thresh; 1000 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1001 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1002 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1003 txq->offloads = offloads; 1004 1005 is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); 1006 1007 /* Choose optimum free threshold value for multipool case */ 1008 if (!is_single_pool) { 1009 txq->tx_free_thresh = (uint16_t) 1010 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1011 NICVF_TX_FREE_MPOOL_THRESH : 1012 tx_conf->tx_free_thresh); 1013 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1014 } else { 1015 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1016 } 1017 1018 /* Allocate software ring */ 1019 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1020 nb_desc * sizeof(struct rte_mbuf *), 1021 RTE_CACHE_LINE_SIZE, nic->node); 1022 1023 if (txq->txbuffs == NULL) { 1024 nicvf_dev_tx_queue_release(txq); 1025 return -ENOMEM; 1026 } 1027 1028 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1029 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1030 nicvf_dev_tx_queue_release(txq); 1031 return -ENOMEM; 1032 } 1033 1034 nicvf_tx_queue_reset(txq); 1035 1036 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1037 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1038 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1039 txq->phys, txq->offloads); 1040 1041 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1042 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1043 RTE_ETH_QUEUE_STATE_STOPPED; 1044 return 0; 1045 } 1046 1047 static inline void 1048 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1049 { 1050 uint32_t rxq_cnt; 1051 uint32_t nb_pkts, released_pkts = 0; 1052 uint32_t refill_cnt = 0; 1053 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1054 1055 if (dev->rx_pkt_burst == NULL) 1056 return; 1057 1058 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, 1059 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) { 1060 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1061 NICVF_MAX_RX_FREE_THRESH); 1062 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1063 while (nb_pkts) { 1064 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1065 released_pkts++; 1066 } 1067 } 1068 1069 1070 refill_cnt += nicvf_dev_rbdr_refill(dev, 1071 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1072 1073 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1074 released_pkts, refill_cnt); 1075 } 1076 1077 static void 1078 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1079 { 1080 rxq->head = 0; 1081 rxq->available_space = 0; 1082 rxq->recv_buffers = 0; 1083 } 1084 1085 static inline int 1086 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1087 uint16_t qidx) 1088 { 1089 struct nicvf_rxq *rxq; 1090 int ret; 1091 1092 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1093 1094 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1095 RTE_ETH_QUEUE_STATE_STARTED) 1096 return 0; 1097 1098 /* Update rbdr pointer to all rxq */ 1099 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1100 rxq->shared_rbdr = nic->rbdr; 1101 1102 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1103 if (ret) { 1104 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1105 nic->vf_id, qidx, ret); 1106 goto config_rq_error; 1107 } 1108 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1109 if (ret) { 1110 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1111 nic->vf_id, qidx, ret); 1112 goto config_cq_error; 1113 } 1114 1115 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1116 RTE_ETH_QUEUE_STATE_STARTED; 1117 return 0; 1118 1119 config_cq_error: 1120 nicvf_qset_cq_reclaim(nic, qidx); 1121 config_rq_error: 1122 nicvf_qset_rq_reclaim(nic, qidx); 1123 return ret; 1124 } 1125 1126 static inline int 1127 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1128 uint16_t qidx) 1129 { 1130 struct nicvf_rxq *rxq; 1131 int ret, other_error; 1132 1133 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1134 RTE_ETH_QUEUE_STATE_STOPPED) 1135 return 0; 1136 1137 ret = nicvf_qset_rq_reclaim(nic, qidx); 1138 if (ret) 1139 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1140 nic->vf_id, qidx, ret); 1141 1142 other_error = ret; 1143 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1144 nicvf_rx_queue_release_mbufs(dev, rxq); 1145 nicvf_rx_queue_reset(rxq); 1146 1147 ret = nicvf_qset_cq_reclaim(nic, qidx); 1148 if (ret) 1149 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1150 nic->vf_id, qidx, ret); 1151 1152 other_error |= ret; 1153 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1154 RTE_ETH_QUEUE_STATE_STOPPED; 1155 return other_error; 1156 } 1157 1158 static void 1159 nicvf_dev_rx_queue_release(void *rx_queue) 1160 { 1161 PMD_INIT_FUNC_TRACE(); 1162 1163 rte_free(rx_queue); 1164 } 1165 1166 static int 1167 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1168 { 1169 struct nicvf *nic = nicvf_pmd_priv(dev); 1170 int ret; 1171 1172 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1173 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1174 1175 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1176 1177 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1178 if (ret) 1179 return ret; 1180 1181 ret = nicvf_configure_cpi(dev); 1182 if (ret) 1183 return ret; 1184 1185 return nicvf_configure_rss_reta(dev); 1186 } 1187 1188 static int 1189 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1190 { 1191 int ret; 1192 struct nicvf *nic = nicvf_pmd_priv(dev); 1193 1194 if (qidx >= MAX_SND_QUEUES_PER_QS) 1195 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1196 1197 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1198 1199 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1200 ret |= nicvf_configure_cpi(dev); 1201 ret |= nicvf_configure_rss_reta(dev); 1202 return ret; 1203 } 1204 1205 static int 1206 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1207 { 1208 struct nicvf *nic = nicvf_pmd_priv(dev); 1209 1210 if (qidx >= MAX_SND_QUEUES_PER_QS) 1211 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1212 1213 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1214 1215 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1216 } 1217 1218 static int 1219 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1220 { 1221 struct nicvf *nic = nicvf_pmd_priv(dev); 1222 1223 if (qidx >= MAX_SND_QUEUES_PER_QS) 1224 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1225 1226 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1227 1228 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1229 } 1230 1231 static inline void 1232 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1233 { 1234 uintptr_t p; 1235 struct rte_mbuf mb_def; 1236 struct nicvf *nic = rxq->nic; 1237 1238 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1239 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1240 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1241 offsetof(struct rte_mbuf, data_off) != 2); 1242 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1243 offsetof(struct rte_mbuf, data_off) != 4); 1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1245 offsetof(struct rte_mbuf, data_off) != 6); 1246 mb_def.nb_segs = 1; 1247 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1248 mb_def.port = rxq->port_id; 1249 rte_mbuf_refcnt_set(&mb_def, 1); 1250 1251 /* Prevent compiler reordering: rearm_data covers previous fields */ 1252 rte_compiler_barrier(); 1253 p = (uintptr_t)&mb_def.rearm_data; 1254 rxq->mbuf_initializer.value = *(uint64_t *)p; 1255 } 1256 1257 static int 1258 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1259 uint16_t nb_desc, unsigned int socket_id, 1260 const struct rte_eth_rxconf *rx_conf, 1261 struct rte_mempool *mp) 1262 { 1263 uint16_t rx_free_thresh; 1264 struct nicvf_rxq *rxq; 1265 struct nicvf *nic = nicvf_pmd_priv(dev); 1266 uint64_t offloads; 1267 uint32_t buffsz; 1268 struct rte_pktmbuf_pool_private *mbp_priv; 1269 1270 PMD_INIT_FUNC_TRACE(); 1271 1272 /* First skip check */ 1273 mbp_priv = rte_mempool_get_priv(mp); 1274 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1275 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1276 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1277 return -EINVAL; 1278 } 1279 1280 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1281 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1282 1283 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1284 1285 /* Socket id check */ 1286 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1287 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1288 socket_id, nic->node); 1289 1290 /* Mempool memory must be contiguous, so must be one memory segment*/ 1291 if (mp->nb_mem_chunks != 1) { 1292 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1293 return -EINVAL; 1294 } 1295 1296 /* Mempool memory must be physically contiguous */ 1297 if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) { 1298 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1299 return -EINVAL; 1300 } 1301 1302 /* Rx deferred start is not supported */ 1303 if (rx_conf->rx_deferred_start) { 1304 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1305 return -EINVAL; 1306 } 1307 1308 /* Roundup nb_desc to available qsize and validate max number of desc */ 1309 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1310 if (nb_desc == 0) { 1311 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1312 return -EINVAL; 1313 } 1314 1315 1316 /* Check rx_free_thresh upper bound */ 1317 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1318 rx_conf->rx_free_thresh : 1319 NICVF_DEFAULT_RX_FREE_THRESH); 1320 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1321 rx_free_thresh >= nb_desc * .75) { 1322 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1323 rx_free_thresh); 1324 return -EINVAL; 1325 } 1326 1327 /* Free memory prior to re-allocation if needed */ 1328 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1329 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1330 nicvf_netdev_qidx(nic, qidx)); 1331 nicvf_dev_rx_queue_release( 1332 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]); 1333 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1334 } 1335 1336 /* Allocate rxq memory */ 1337 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1338 RTE_CACHE_LINE_SIZE, nic->node); 1339 if (rxq == NULL) { 1340 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1341 nicvf_netdev_qidx(nic, qidx)); 1342 return -ENOMEM; 1343 } 1344 1345 rxq->nic = nic; 1346 rxq->pool = mp; 1347 rxq->queue_id = qidx; 1348 rxq->port_id = dev->data->port_id; 1349 rxq->rx_free_thresh = rx_free_thresh; 1350 rxq->rx_drop_en = rx_conf->rx_drop_en; 1351 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1352 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1353 rxq->precharge_cnt = 0; 1354 1355 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1356 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1357 else 1358 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1359 1360 nicvf_rxq_mbuf_setup(rxq); 1361 1362 /* Alloc completion queue */ 1363 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1364 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1365 nicvf_dev_rx_queue_release(rxq); 1366 return -ENOMEM; 1367 } 1368 1369 nicvf_rx_queue_reset(rxq); 1370 1371 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1372 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1373 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1374 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1375 rte_mempool_avail_count(mp), rxq->phys, offloads); 1376 1377 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1378 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1379 RTE_ETH_QUEUE_STATE_STOPPED; 1380 return 0; 1381 } 1382 1383 static void 1384 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1385 { 1386 struct nicvf *nic = nicvf_pmd_priv(dev); 1387 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1388 1389 PMD_INIT_FUNC_TRACE(); 1390 1391 /* Autonegotiation may be disabled */ 1392 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 1393 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 1394 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 1395 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1396 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 1397 1398 dev_info->min_rx_bufsize = ETHER_MIN_MTU; 1399 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN; 1400 dev_info->max_rx_queues = 1401 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1402 dev_info->max_tx_queues = 1403 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1404 dev_info->max_mac_addrs = 1; 1405 dev_info->max_vfs = pci_dev->max_vfs; 1406 1407 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1408 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1409 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1410 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1411 1412 dev_info->reta_size = nic->rss_info.rss_size; 1413 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1414 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1415 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1416 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1417 1418 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1419 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1420 .rx_drop_en = 0, 1421 .offloads = DEV_RX_OFFLOAD_CRC_STRIP, 1422 }; 1423 1424 dev_info->default_txconf = (struct rte_eth_txconf) { 1425 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1426 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE | 1427 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1428 DEV_TX_OFFLOAD_UDP_CKSUM | 1429 DEV_TX_OFFLOAD_TCP_CKSUM, 1430 }; 1431 } 1432 1433 static nicvf_iova_addr_t 1434 rbdr_rte_mempool_get(void *dev, void *opaque) 1435 { 1436 uint16_t qidx; 1437 uintptr_t mbuf; 1438 struct nicvf_rxq *rxq; 1439 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1440 struct nicvf *nic = (struct nicvf *)opaque; 1441 uint16_t rx_start, rx_end; 1442 1443 /* Get queue ranges for this VF */ 1444 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1445 1446 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1447 rxq = eth_dev->data->rx_queues[qidx]; 1448 /* Maintain equal buffer count across all pools */ 1449 if (rxq->precharge_cnt >= rxq->qlen_mask) 1450 continue; 1451 rxq->precharge_cnt++; 1452 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1453 if (mbuf) 1454 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1455 } 1456 return 0; 1457 } 1458 1459 static int 1460 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1461 { 1462 int ret; 1463 uint16_t qidx, data_off; 1464 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1465 uint64_t mbuf_phys_off = 0; 1466 struct nicvf_rxq *rxq; 1467 struct rte_mbuf *mbuf; 1468 uint16_t rx_start, rx_end; 1469 uint16_t tx_start, tx_end; 1470 bool vlan_strip; 1471 1472 PMD_INIT_FUNC_TRACE(); 1473 1474 /* Userspace process exited without proper shutdown in last run */ 1475 if (nicvf_qset_rbdr_active(nic, 0)) 1476 nicvf_vf_stop(dev, nic, false); 1477 1478 /* Get queue ranges for this VF */ 1479 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1480 1481 /* 1482 * Thunderx nicvf PMD can support more than one pool per port only when 1483 * 1) Data payload size is same across all the pools in given port 1484 * AND 1485 * 2) All mbuffs in the pools are from the same hugepage 1486 * AND 1487 * 3) Mbuff metadata size is same across all the pools in given port 1488 * 1489 * This is to support existing application that uses multiple pool/port. 1490 * But, the purpose of using multipool for QoS will not be addressed. 1491 * 1492 */ 1493 1494 /* Validate mempool attributes */ 1495 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1496 rxq = dev->data->rx_queues[qidx]; 1497 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1498 mbuf = rte_pktmbuf_alloc(rxq->pool); 1499 if (mbuf == NULL) { 1500 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1501 "pool=%s", 1502 nic->vf_id, qidx, rxq->pool->name); 1503 return -ENOMEM; 1504 } 1505 data_off = nicvf_mbuff_meta_length(mbuf); 1506 data_off += RTE_PKTMBUF_HEADROOM; 1507 rte_pktmbuf_free(mbuf); 1508 1509 if (data_off % RTE_CACHE_LINE_SIZE) { 1510 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1511 rxq->pool->name, data_off, 1512 data_off % RTE_CACHE_LINE_SIZE); 1513 return -EINVAL; 1514 } 1515 rxq->mbuf_phys_off -= data_off; 1516 rxq->mbuf_phys_off -= nic->skip_bytes; 1517 1518 if (mbuf_phys_off == 0) 1519 mbuf_phys_off = rxq->mbuf_phys_off; 1520 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1521 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1522 PRIx64, rxq->pool->name, nic->vf_id, 1523 mbuf_phys_off); 1524 return -EINVAL; 1525 } 1526 } 1527 1528 /* Check the level of buffers in the pool */ 1529 total_rxq_desc = 0; 1530 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1531 rxq = dev->data->rx_queues[qidx]; 1532 /* Count total numbers of rxq descs */ 1533 total_rxq_desc += rxq->qlen_mask + 1; 1534 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1535 exp_buffs *= dev->data->nb_rx_queues; 1536 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1537 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1538 rxq->pool->name, 1539 rte_mempool_avail_count(rxq->pool), 1540 exp_buffs); 1541 return -ENOENT; 1542 } 1543 } 1544 1545 /* Check RBDR desc overflow */ 1546 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1547 if (ret == 0) { 1548 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1549 "VF%d", nic->vf_id); 1550 return -ENOMEM; 1551 } 1552 1553 /* Enable qset */ 1554 ret = nicvf_qset_config(nic); 1555 if (ret) { 1556 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1557 nic->vf_id); 1558 return ret; 1559 } 1560 1561 /* Allocate RBDR and RBDR ring desc */ 1562 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1563 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1564 if (ret) { 1565 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1566 "VF%d", nic->vf_id); 1567 goto qset_reclaim; 1568 } 1569 1570 /* Enable and configure RBDR registers */ 1571 ret = nicvf_qset_rbdr_config(nic, 0); 1572 if (ret) { 1573 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1574 nic->vf_id); 1575 goto qset_rbdr_free; 1576 } 1577 1578 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1579 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1580 total_rxq_desc); 1581 if (ret) { 1582 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1583 nic->vf_id); 1584 goto qset_rbdr_reclaim; 1585 } 1586 1587 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1588 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1589 1590 /* Configure VLAN Strip */ 1591 vlan_strip = !!(dev->data->dev_conf.rxmode.offloads & 1592 DEV_RX_OFFLOAD_VLAN_STRIP); 1593 nicvf_vlan_hw_strip(nic, vlan_strip); 1594 1595 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1596 * to the 64bit memory address. 1597 * The alignment creates a hole in mbuf(between the end of headroom and 1598 * packet data start). The new revision of the HW provides an option to 1599 * disable the L3 alignment feature and make mbuf layout looks 1600 * more like other NICs. For better application compatibility, disabling 1601 * l3 alignment feature on the hardware revisions it supports 1602 */ 1603 nicvf_apad_config(nic, false); 1604 1605 /* Get queue ranges for this VF */ 1606 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1607 1608 /* Configure TX queues */ 1609 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1610 ret = nicvf_vf_start_tx_queue(dev, nic, 1611 qidx % MAX_SND_QUEUES_PER_QS); 1612 if (ret) 1613 goto start_txq_error; 1614 } 1615 1616 /* Configure RX queues */ 1617 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1618 ret = nicvf_vf_start_rx_queue(dev, nic, 1619 qidx % MAX_RCV_QUEUES_PER_QS); 1620 if (ret) 1621 goto start_rxq_error; 1622 } 1623 1624 if (!nic->sqs_mode) { 1625 /* Configure CPI algorithm */ 1626 ret = nicvf_configure_cpi(dev); 1627 if (ret) 1628 goto start_txq_error; 1629 1630 ret = nicvf_mbox_get_rss_size(nic); 1631 if (ret) { 1632 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1633 goto qset_rss_error; 1634 } 1635 1636 /* Configure RSS */ 1637 ret = nicvf_configure_rss(dev); 1638 if (ret) 1639 goto qset_rss_error; 1640 } 1641 1642 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1643 nicvf_mbox_cfg_done(nic); 1644 return 0; 1645 1646 qset_rss_error: 1647 nicvf_rss_term(nic); 1648 start_rxq_error: 1649 for (qidx = rx_start; qidx <= rx_end; qidx++) 1650 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1651 start_txq_error: 1652 for (qidx = tx_start; qidx <= tx_end; qidx++) 1653 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1654 qset_rbdr_reclaim: 1655 nicvf_qset_rbdr_reclaim(nic, 0); 1656 nicvf_rbdr_release_mbufs(dev, nic); 1657 qset_rbdr_free: 1658 if (nic->rbdr) { 1659 rte_free(nic->rbdr); 1660 nic->rbdr = NULL; 1661 } 1662 qset_reclaim: 1663 nicvf_qset_reclaim(nic); 1664 return ret; 1665 } 1666 1667 static int 1668 nicvf_dev_start(struct rte_eth_dev *dev) 1669 { 1670 uint16_t qidx; 1671 int ret; 1672 size_t i; 1673 struct nicvf *nic = nicvf_pmd_priv(dev); 1674 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1675 uint16_t mtu; 1676 uint32_t buffsz = 0, rbdrsz = 0; 1677 struct rte_pktmbuf_pool_private *mbp_priv; 1678 struct nicvf_rxq *rxq; 1679 1680 PMD_INIT_FUNC_TRACE(); 1681 1682 /* This function must be called for a primary device */ 1683 assert_primary(nic); 1684 1685 /* Validate RBDR buff size */ 1686 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1687 rxq = dev->data->rx_queues[qidx]; 1688 mbp_priv = rte_mempool_get_priv(rxq->pool); 1689 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1690 if (buffsz % 128) { 1691 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1692 return -EINVAL; 1693 } 1694 if (rbdrsz == 0) 1695 rbdrsz = buffsz; 1696 if (rbdrsz != buffsz) { 1697 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1698 qidx, rbdrsz, buffsz); 1699 return -EINVAL; 1700 } 1701 } 1702 1703 /* Configure loopback */ 1704 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1705 if (ret) { 1706 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1707 return ret; 1708 } 1709 1710 /* Reset all statistics counters attached to this port */ 1711 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1712 if (ret) { 1713 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1714 return ret; 1715 } 1716 1717 /* Setup scatter mode if needed by jumbo */ 1718 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1719 2 * VLAN_TAG_SIZE > buffsz) 1720 dev->data->scattered_rx = 1; 1721 if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0) 1722 dev->data->scattered_rx = 1; 1723 1724 /* Setup MTU based on max_rx_pkt_len or default */ 1725 mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ? 1726 dev->data->dev_conf.rxmode.max_rx_pkt_len 1727 - ETHER_HDR_LEN : ETHER_MTU; 1728 1729 if (nicvf_dev_set_mtu(dev, mtu)) { 1730 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1731 return -EBUSY; 1732 } 1733 1734 ret = nicvf_vf_start(dev, nic, rbdrsz); 1735 if (ret != 0) 1736 return ret; 1737 1738 for (i = 0; i < nic->sqs_count; i++) { 1739 assert(nic->snicvf[i]); 1740 1741 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1742 if (ret != 0) 1743 return ret; 1744 } 1745 1746 /* Configure callbacks based on scatter mode */ 1747 nicvf_set_tx_function(dev); 1748 nicvf_set_rx_function(dev); 1749 1750 return 0; 1751 } 1752 1753 static void 1754 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1755 { 1756 size_t i; 1757 int ret; 1758 struct nicvf *nic = nicvf_pmd_priv(dev); 1759 1760 PMD_INIT_FUNC_TRACE(); 1761 1762 /* Teardown secondary vf first */ 1763 for (i = 0; i < nic->sqs_count; i++) { 1764 if (!nic->snicvf[i]) 1765 continue; 1766 1767 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1768 } 1769 1770 /* Stop the primary VF now */ 1771 nicvf_vf_stop(dev, nic, cleanup); 1772 1773 /* Disable loopback */ 1774 ret = nicvf_loopback_config(nic, 0); 1775 if (ret) 1776 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1777 1778 /* Reclaim CPI configuration */ 1779 ret = nicvf_mbox_config_cpi(nic, 0); 1780 if (ret) 1781 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1782 } 1783 1784 static void 1785 nicvf_dev_stop(struct rte_eth_dev *dev) 1786 { 1787 PMD_INIT_FUNC_TRACE(); 1788 1789 nicvf_dev_stop_cleanup(dev, false); 1790 } 1791 1792 static void 1793 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1794 { 1795 int ret; 1796 uint16_t qidx; 1797 uint16_t tx_start, tx_end; 1798 uint16_t rx_start, rx_end; 1799 1800 PMD_INIT_FUNC_TRACE(); 1801 1802 if (cleanup) { 1803 /* Let PF make the BGX's RX and TX switches to OFF position */ 1804 nicvf_mbox_shutdown(nic); 1805 } 1806 1807 /* Disable VLAN Strip */ 1808 nicvf_vlan_hw_strip(nic, 0); 1809 1810 /* Get queue ranges for this VF */ 1811 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1812 1813 for (qidx = tx_start; qidx <= tx_end; qidx++) 1814 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1815 1816 /* Get queue ranges for this VF */ 1817 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1818 1819 /* Reclaim rq */ 1820 for (qidx = rx_start; qidx <= rx_end; qidx++) 1821 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1822 1823 /* Reclaim RBDR */ 1824 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1825 if (ret) 1826 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1827 1828 /* Move all charged buffers in RBDR back to pool */ 1829 if (nic->rbdr != NULL) 1830 nicvf_rbdr_release_mbufs(dev, nic); 1831 1832 /* Disable qset */ 1833 ret = nicvf_qset_reclaim(nic); 1834 if (ret) 1835 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1836 1837 /* Disable all interrupts */ 1838 nicvf_disable_all_interrupts(nic); 1839 1840 /* Free RBDR SW structure */ 1841 if (nic->rbdr) { 1842 rte_free(nic->rbdr); 1843 nic->rbdr = NULL; 1844 } 1845 } 1846 1847 static void 1848 nicvf_dev_close(struct rte_eth_dev *dev) 1849 { 1850 size_t i; 1851 struct nicvf *nic = nicvf_pmd_priv(dev); 1852 1853 PMD_INIT_FUNC_TRACE(); 1854 1855 nicvf_dev_stop_cleanup(dev, true); 1856 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1857 1858 for (i = 0; i < nic->sqs_count; i++) { 1859 if (!nic->snicvf[i]) 1860 continue; 1861 1862 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); 1863 } 1864 } 1865 1866 static int 1867 nicvf_request_sqs(struct nicvf *nic) 1868 { 1869 size_t i; 1870 1871 assert_primary(nic); 1872 assert(nic->sqs_count > 0); 1873 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1874 1875 /* Set no of Rx/Tx queues in each of the SQsets */ 1876 for (i = 0; i < nic->sqs_count; i++) { 1877 if (nicvf_svf_empty()) 1878 rte_panic("Cannot assign sufficient number of " 1879 "secondary queues to primary VF%" PRIu8 "\n", 1880 nic->vf_id); 1881 1882 nic->snicvf[i] = nicvf_svf_pop(); 1883 nic->snicvf[i]->sqs_id = i; 1884 } 1885 1886 return nicvf_mbox_request_sqs(nic); 1887 } 1888 1889 static int 1890 nicvf_dev_configure(struct rte_eth_dev *dev) 1891 { 1892 struct rte_eth_dev_data *data = dev->data; 1893 struct rte_eth_conf *conf = &data->dev_conf; 1894 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1895 struct rte_eth_txmode *txmode = &conf->txmode; 1896 struct nicvf *nic = nicvf_pmd_priv(dev); 1897 uint8_t cqcount; 1898 1899 PMD_INIT_FUNC_TRACE(); 1900 1901 if (!rte_eal_has_hugepages()) { 1902 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1903 return -EINVAL; 1904 } 1905 1906 /* KEEP_CRC offload flag is not supported by PMD 1907 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed 1908 */ 1909 if (rte_eth_dev_must_keep_crc(rxmode->offloads)) { 1910 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip"); 1911 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP; 1912 } 1913 1914 if (txmode->mq_mode) { 1915 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1916 return -EINVAL; 1917 } 1918 1919 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1920 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1921 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1922 return -EINVAL; 1923 } 1924 1925 if (rxmode->split_hdr_size) { 1926 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1927 return -EINVAL; 1928 } 1929 1930 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1931 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1932 return -EINVAL; 1933 } 1934 1935 if (conf->dcb_capability_en) { 1936 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1937 return -EINVAL; 1938 } 1939 1940 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1941 PMD_INIT_LOG(INFO, "Flow director not supported"); 1942 return -EINVAL; 1943 } 1944 1945 assert_primary(nic); 1946 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1947 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1948 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1949 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1950 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1951 } else { 1952 nic->sqs_count = 0; 1953 } 1954 1955 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1956 1957 if (nic->sqs_count > 0) { 1958 if (nicvf_request_sqs(nic)) { 1959 rte_panic("Cannot assign sufficient number of " 1960 "secondary queues to PORT%d VF%" PRIu8 "\n", 1961 dev->data->port_id, nic->vf_id); 1962 } 1963 } 1964 1965 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1966 dev->data->port_id, nicvf_hw_cap(nic)); 1967 1968 return 0; 1969 } 1970 1971 /* Initialize and register driver with DPDK Application */ 1972 static const struct eth_dev_ops nicvf_eth_dev_ops = { 1973 .dev_configure = nicvf_dev_configure, 1974 .dev_start = nicvf_dev_start, 1975 .dev_stop = nicvf_dev_stop, 1976 .link_update = nicvf_dev_link_update, 1977 .dev_close = nicvf_dev_close, 1978 .stats_get = nicvf_dev_stats_get, 1979 .stats_reset = nicvf_dev_stats_reset, 1980 .promiscuous_enable = nicvf_dev_promisc_enable, 1981 .dev_infos_get = nicvf_dev_info_get, 1982 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 1983 .mtu_set = nicvf_dev_set_mtu, 1984 .reta_update = nicvf_dev_reta_update, 1985 .reta_query = nicvf_dev_reta_query, 1986 .rss_hash_update = nicvf_dev_rss_hash_update, 1987 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 1988 .rx_queue_start = nicvf_dev_rx_queue_start, 1989 .rx_queue_stop = nicvf_dev_rx_queue_stop, 1990 .tx_queue_start = nicvf_dev_tx_queue_start, 1991 .tx_queue_stop = nicvf_dev_tx_queue_stop, 1992 .rx_queue_setup = nicvf_dev_rx_queue_setup, 1993 .rx_queue_release = nicvf_dev_rx_queue_release, 1994 .rx_queue_count = nicvf_dev_rx_queue_count, 1995 .tx_queue_setup = nicvf_dev_tx_queue_setup, 1996 .tx_queue_release = nicvf_dev_tx_queue_release, 1997 .get_reg = nicvf_dev_get_regs, 1998 }; 1999 2000 static inline int 2001 nicvf_set_first_skip(struct rte_eth_dev *dev) 2002 { 2003 int bytes_to_skip = 0; 2004 int ret = 0; 2005 unsigned int i; 2006 struct rte_kvargs *kvlist; 2007 static const char *const skip[] = { 2008 SKIP_DATA_BYTES, 2009 NULL}; 2010 struct nicvf *nic = nicvf_pmd_priv(dev); 2011 2012 if (!dev->device->devargs) { 2013 nicvf_first_skip_config(nic, 0); 2014 return ret; 2015 } 2016 2017 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2018 if (!kvlist) 2019 return -EINVAL; 2020 2021 if (kvlist->count == 0) 2022 goto exit; 2023 2024 for (i = 0; i != kvlist->count; ++i) { 2025 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2026 2027 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2028 bytes_to_skip = atoi(pair->value); 2029 } 2030 2031 /*128 bytes amounts to one cache line*/ 2032 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2033 if (!(bytes_to_skip % 8)) { 2034 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2035 nic->skip_bytes = bytes_to_skip; 2036 goto kvlist_free; 2037 } else { 2038 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2039 ret = -EINVAL; 2040 goto exit; 2041 } 2042 } else { 2043 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2044 ret = -EINVAL; 2045 goto exit; 2046 } 2047 exit: 2048 nicvf_first_skip_config(nic, 0); 2049 kvlist_free: 2050 rte_kvargs_free(kvlist); 2051 return ret; 2052 } 2053 static int 2054 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2055 { 2056 int ret; 2057 struct rte_pci_device *pci_dev; 2058 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2059 2060 PMD_INIT_FUNC_TRACE(); 2061 2062 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2063 2064 /* For secondary processes, the primary has done all the work */ 2065 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2066 if (nic) { 2067 /* Setup callbacks for secondary process */ 2068 nicvf_set_tx_function(eth_dev); 2069 nicvf_set_rx_function(eth_dev); 2070 return 0; 2071 } else { 2072 /* If nic == NULL than it is secondary function 2073 * so ethdev need to be released by caller */ 2074 return ENOTSUP; 2075 } 2076 } 2077 2078 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2079 rte_eth_copy_pci_info(eth_dev, pci_dev); 2080 2081 nic->device_id = pci_dev->id.device_id; 2082 nic->vendor_id = pci_dev->id.vendor_id; 2083 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2084 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2085 2086 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2087 pci_dev->id.vendor_id, pci_dev->id.device_id, 2088 pci_dev->addr.domain, pci_dev->addr.bus, 2089 pci_dev->addr.devid, pci_dev->addr.function); 2090 2091 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2092 if (!nic->reg_base) { 2093 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2094 ret = -ENODEV; 2095 goto fail; 2096 } 2097 2098 nicvf_disable_all_interrupts(nic); 2099 2100 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2101 if (ret) { 2102 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2103 goto fail; 2104 } 2105 2106 ret = nicvf_mbox_check_pf_ready(nic); 2107 if (ret) { 2108 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2109 goto alarm_fail; 2110 } else { 2111 PMD_INIT_LOG(INFO, 2112 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2113 nic->node, nic->vf_id, 2114 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2115 nic->sqs_mode ? "true" : "false", 2116 nic->loopback_supported ? "true" : "false" 2117 ); 2118 } 2119 2120 ret = nicvf_base_init(nic); 2121 if (ret) { 2122 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2123 goto malloc_fail; 2124 } 2125 2126 if (nic->sqs_mode) { 2127 /* Push nic to stack of secondary vfs */ 2128 nicvf_svf_push(nic); 2129 2130 /* Steal nic pointer from the device for further reuse */ 2131 eth_dev->data->dev_private = NULL; 2132 2133 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2134 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2135 if (ret) { 2136 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2137 goto fail; 2138 } 2139 2140 /* Detach port by returning positive error number */ 2141 return ENOTSUP; 2142 } 2143 2144 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); 2145 if (eth_dev->data->mac_addrs == NULL) { 2146 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2147 ret = -ENOMEM; 2148 goto alarm_fail; 2149 } 2150 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr)) 2151 eth_random_addr(&nic->mac_addr[0]); 2152 2153 ether_addr_copy((struct ether_addr *)nic->mac_addr, 2154 ð_dev->data->mac_addrs[0]); 2155 2156 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2157 if (ret) { 2158 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2159 goto malloc_fail; 2160 } 2161 2162 ret = nicvf_set_first_skip(eth_dev); 2163 if (ret) { 2164 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2165 goto malloc_fail; 2166 } 2167 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 2168 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2169 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2170 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2171 2172 return 0; 2173 2174 malloc_fail: 2175 rte_free(eth_dev->data->mac_addrs); 2176 alarm_fail: 2177 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2178 fail: 2179 return ret; 2180 } 2181 2182 static const struct rte_pci_id pci_id_nicvf_map[] = { 2183 { 2184 .class_id = RTE_CLASS_ANY_ID, 2185 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2186 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2187 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2188 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2189 }, 2190 { 2191 .class_id = RTE_CLASS_ANY_ID, 2192 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2193 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2194 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2195 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2196 }, 2197 { 2198 .class_id = RTE_CLASS_ANY_ID, 2199 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2200 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2201 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2202 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2203 }, 2204 { 2205 .class_id = RTE_CLASS_ANY_ID, 2206 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2207 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2208 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2209 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2210 }, 2211 { 2212 .vendor_id = 0, 2213 }, 2214 }; 2215 2216 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2217 struct rte_pci_device *pci_dev) 2218 { 2219 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2220 nicvf_eth_dev_init); 2221 } 2222 2223 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2224 { 2225 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 2226 } 2227 2228 static struct rte_pci_driver rte_nicvf_pmd = { 2229 .id_table = pci_id_nicvf_map, 2230 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2231 RTE_PCI_DRV_INTR_LSC, 2232 .probe = nicvf_eth_pci_probe, 2233 .remove = nicvf_eth_pci_remove, 2234 }; 2235 2236 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2237 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2238 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2239 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2240