1 /* 2 * BSD LICENSE 3 * 4 * Copyright (C) Cavium, Inc. 2016. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Cavium, Inc nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <assert.h> 34 #include <stdio.h> 35 #include <stdbool.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 #include <sys/queue.h> 44 45 #include <rte_alarm.h> 46 #include <rte_atomic.h> 47 #include <rte_branch_prediction.h> 48 #include <rte_byteorder.h> 49 #include <rte_common.h> 50 #include <rte_cycles.h> 51 #include <rte_debug.h> 52 #include <rte_dev.h> 53 #include <rte_eal.h> 54 #include <rte_ether.h> 55 #include <rte_ethdev.h> 56 #include <rte_ethdev_pci.h> 57 #include <rte_interrupts.h> 58 #include <rte_log.h> 59 #include <rte_memory.h> 60 #include <rte_memzone.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_pci.h> 64 #include <rte_tailq.h> 65 66 #include "base/nicvf_plat.h" 67 68 #include "nicvf_ethdev.h" 69 #include "nicvf_rxtx.h" 70 #include "nicvf_svf.h" 71 #include "nicvf_logs.h" 72 73 static void nicvf_dev_stop(struct rte_eth_dev *dev); 74 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 75 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 76 bool cleanup); 77 78 static inline int 79 nicvf_atomic_write_link_status(struct rte_eth_dev *dev, 80 struct rte_eth_link *link) 81 { 82 struct rte_eth_link *dst = &dev->data->dev_link; 83 struct rte_eth_link *src = link; 84 85 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 86 *(uint64_t *)src) == 0) 87 return -1; 88 89 return 0; 90 } 91 92 static inline void 93 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link) 94 { 95 link->link_status = nic->link_up; 96 link->link_duplex = ETH_LINK_AUTONEG; 97 if (nic->duplex == NICVF_HALF_DUPLEX) 98 link->link_duplex = ETH_LINK_HALF_DUPLEX; 99 else if (nic->duplex == NICVF_FULL_DUPLEX) 100 link->link_duplex = ETH_LINK_FULL_DUPLEX; 101 link->link_speed = nic->speed; 102 link->link_autoneg = ETH_LINK_SPEED_AUTONEG; 103 } 104 105 static void 106 nicvf_interrupt(void *arg) 107 { 108 struct rte_eth_dev *dev = arg; 109 struct nicvf *nic = nicvf_pmd_priv(dev); 110 111 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 112 if (dev->data->dev_conf.intr_conf.lsc) 113 nicvf_set_eth_link_status(nic, &dev->data->dev_link); 114 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 115 NULL, NULL); 116 } 117 118 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 119 nicvf_interrupt, dev); 120 } 121 122 static void 123 nicvf_vf_interrupt(void *arg) 124 { 125 struct nicvf *nic = arg; 126 127 nicvf_reg_poll_interrupts(nic); 128 129 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 130 nicvf_vf_interrupt, nic); 131 } 132 133 static int 134 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 135 { 136 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 137 } 138 139 static int 140 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 141 { 142 return rte_eal_alarm_cancel(fn, arg); 143 } 144 145 /* 146 * Return 0 means link status changed, -1 means not changed 147 */ 148 static int 149 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 150 { 151 #define CHECK_INTERVAL 100 /* 100ms */ 152 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 153 struct rte_eth_link link; 154 struct nicvf *nic = nicvf_pmd_priv(dev); 155 int i; 156 157 PMD_INIT_FUNC_TRACE(); 158 159 if (wait_to_complete) { 160 /* rte_eth_link_get() might need to wait up to 9 seconds */ 161 for (i = 0; i < MAX_CHECK_TIME; i++) { 162 memset(&link, 0, sizeof(link)); 163 nicvf_set_eth_link_status(nic, &link); 164 if (link.link_status) 165 break; 166 rte_delay_ms(CHECK_INTERVAL); 167 } 168 } else { 169 memset(&link, 0, sizeof(link)); 170 nicvf_set_eth_link_status(nic, &link); 171 } 172 return nicvf_atomic_write_link_status(dev, &link); 173 } 174 175 static int 176 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 177 { 178 struct nicvf *nic = nicvf_pmd_priv(dev); 179 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 180 size_t i; 181 182 PMD_INIT_FUNC_TRACE(); 183 184 if (frame_size > NIC_HW_MAX_FRS) 185 return -EINVAL; 186 187 if (frame_size < NIC_HW_MIN_FRS) 188 return -EINVAL; 189 190 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 191 192 /* 193 * Refuse mtu that requires the support of scattered packets 194 * when this feature has not been enabled before. 195 */ 196 if (!dev->data->scattered_rx && 197 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 198 return -EINVAL; 199 200 /* check <seg size> * <max_seg> >= max_frame */ 201 if (dev->data->scattered_rx && 202 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 203 return -EINVAL; 204 205 if (frame_size > ETHER_MAX_LEN) 206 dev->data->dev_conf.rxmode.jumbo_frame = 1; 207 else 208 dev->data->dev_conf.rxmode.jumbo_frame = 0; 209 210 if (nicvf_mbox_update_hw_max_frs(nic, frame_size)) 211 return -EINVAL; 212 213 /* Update max frame size */ 214 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size; 215 nic->mtu = mtu; 216 217 for (i = 0; i < nic->sqs_count; i++) 218 nic->snicvf[i]->mtu = mtu; 219 220 return 0; 221 } 222 223 static int 224 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 225 { 226 uint64_t *data = regs->data; 227 struct nicvf *nic = nicvf_pmd_priv(dev); 228 229 if (data == NULL) { 230 regs->length = nicvf_reg_get_count(); 231 regs->width = THUNDERX_REG_BYTES; 232 return 0; 233 } 234 235 /* Support only full register dump */ 236 if ((regs->length == 0) || 237 (regs->length == (uint32_t)nicvf_reg_get_count())) { 238 regs->version = nic->vendor_id << 16 | nic->device_id; 239 nicvf_reg_dump(nic, data); 240 return 0; 241 } 242 return -ENOTSUP; 243 } 244 245 static int 246 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 247 { 248 uint16_t qidx; 249 struct nicvf_hw_rx_qstats rx_qstats; 250 struct nicvf_hw_tx_qstats tx_qstats; 251 struct nicvf_hw_stats port_stats; 252 struct nicvf *nic = nicvf_pmd_priv(dev); 253 uint16_t rx_start, rx_end; 254 uint16_t tx_start, tx_end; 255 size_t i; 256 257 /* RX queue indices for the first VF */ 258 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 259 260 /* Reading per RX ring stats */ 261 for (qidx = rx_start; qidx <= rx_end; qidx++) { 262 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 263 break; 264 265 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 266 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 267 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 268 } 269 270 /* TX queue indices for the first VF */ 271 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 272 273 /* Reading per TX ring stats */ 274 for (qidx = tx_start; qidx <= tx_end; qidx++) { 275 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 276 break; 277 278 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 279 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 280 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 281 } 282 283 for (i = 0; i < nic->sqs_count; i++) { 284 struct nicvf *snic = nic->snicvf[i]; 285 286 if (snic == NULL) 287 break; 288 289 /* RX queue indices for a secondary VF */ 290 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 291 292 /* Reading per RX ring stats */ 293 for (qidx = rx_start; qidx <= rx_end; qidx++) { 294 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 295 break; 296 297 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 298 qidx % MAX_RCV_QUEUES_PER_QS); 299 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 300 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 301 } 302 303 /* TX queue indices for a secondary VF */ 304 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 305 /* Reading per TX ring stats */ 306 for (qidx = tx_start; qidx <= tx_end; qidx++) { 307 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 308 break; 309 310 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 311 qidx % MAX_SND_QUEUES_PER_QS); 312 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 313 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 314 } 315 } 316 317 nicvf_hw_get_stats(nic, &port_stats); 318 stats->ibytes = port_stats.rx_bytes; 319 stats->ipackets = port_stats.rx_ucast_frames; 320 stats->ipackets += port_stats.rx_bcast_frames; 321 stats->ipackets += port_stats.rx_mcast_frames; 322 stats->ierrors = port_stats.rx_l2_errors; 323 stats->imissed = port_stats.rx_drop_red; 324 stats->imissed += port_stats.rx_drop_overrun; 325 stats->imissed += port_stats.rx_drop_bcast; 326 stats->imissed += port_stats.rx_drop_mcast; 327 stats->imissed += port_stats.rx_drop_l3_bcast; 328 stats->imissed += port_stats.rx_drop_l3_mcast; 329 330 stats->obytes = port_stats.tx_bytes_ok; 331 stats->opackets = port_stats.tx_ucast_frames_ok; 332 stats->opackets += port_stats.tx_bcast_frames_ok; 333 stats->opackets += port_stats.tx_mcast_frames_ok; 334 stats->oerrors = port_stats.tx_drops; 335 336 return 0; 337 } 338 339 static const uint32_t * 340 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 341 { 342 size_t copied; 343 static uint32_t ptypes[32]; 344 struct nicvf *nic = nicvf_pmd_priv(dev); 345 static const uint32_t ptypes_common[] = { 346 RTE_PTYPE_L3_IPV4, 347 RTE_PTYPE_L3_IPV4_EXT, 348 RTE_PTYPE_L3_IPV6, 349 RTE_PTYPE_L3_IPV6_EXT, 350 RTE_PTYPE_L4_TCP, 351 RTE_PTYPE_L4_UDP, 352 RTE_PTYPE_L4_FRAG, 353 }; 354 static const uint32_t ptypes_tunnel[] = { 355 RTE_PTYPE_TUNNEL_GRE, 356 RTE_PTYPE_TUNNEL_GENEVE, 357 RTE_PTYPE_TUNNEL_VXLAN, 358 RTE_PTYPE_TUNNEL_NVGRE, 359 }; 360 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 361 362 copied = sizeof(ptypes_common); 363 memcpy(ptypes, ptypes_common, copied); 364 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 365 memcpy((char *)ptypes + copied, ptypes_tunnel, 366 sizeof(ptypes_tunnel)); 367 copied += sizeof(ptypes_tunnel); 368 } 369 370 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 371 if (dev->rx_pkt_burst == nicvf_recv_pkts || 372 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg) 373 return ptypes; 374 375 return NULL; 376 } 377 378 static void 379 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 380 { 381 int i; 382 uint16_t rxqs = 0, txqs = 0; 383 struct nicvf *nic = nicvf_pmd_priv(dev); 384 uint16_t rx_start, rx_end; 385 uint16_t tx_start, tx_end; 386 387 /* Reset all primary nic counters */ 388 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 389 for (i = rx_start; i <= rx_end; i++) 390 rxqs |= (0x3 << (i * 2)); 391 392 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 393 for (i = tx_start; i <= tx_end; i++) 394 txqs |= (0x3 << (i * 2)); 395 396 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 397 398 /* Reset secondary nic queue counters */ 399 for (i = 0; i < nic->sqs_count; i++) { 400 struct nicvf *snic = nic->snicvf[i]; 401 if (snic == NULL) 402 break; 403 404 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 405 for (i = rx_start; i <= rx_end; i++) 406 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 407 408 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 409 for (i = tx_start; i <= tx_end; i++) 410 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 411 412 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 413 } 414 } 415 416 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 417 static void 418 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 419 { 420 } 421 422 static inline uint64_t 423 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 424 { 425 uint64_t nic_rss = 0; 426 427 if (ethdev_rss & ETH_RSS_IPV4) 428 nic_rss |= RSS_IP_ENA; 429 430 if (ethdev_rss & ETH_RSS_IPV6) 431 nic_rss |= RSS_IP_ENA; 432 433 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 434 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 435 436 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 437 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 438 439 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 440 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 441 442 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 443 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 444 445 if (ethdev_rss & ETH_RSS_PORT) 446 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 447 448 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 449 if (ethdev_rss & ETH_RSS_VXLAN) 450 nic_rss |= RSS_TUN_VXLAN_ENA; 451 452 if (ethdev_rss & ETH_RSS_GENEVE) 453 nic_rss |= RSS_TUN_GENEVE_ENA; 454 455 if (ethdev_rss & ETH_RSS_NVGRE) 456 nic_rss |= RSS_TUN_NVGRE_ENA; 457 } 458 459 return nic_rss; 460 } 461 462 static inline uint64_t 463 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 464 { 465 uint64_t ethdev_rss = 0; 466 467 if (nic_rss & RSS_IP_ENA) 468 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 469 470 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 471 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 472 ETH_RSS_NONFRAG_IPV6_TCP); 473 474 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 475 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 476 ETH_RSS_NONFRAG_IPV6_UDP); 477 478 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 479 ethdev_rss |= ETH_RSS_PORT; 480 481 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 482 if (nic_rss & RSS_TUN_VXLAN_ENA) 483 ethdev_rss |= ETH_RSS_VXLAN; 484 485 if (nic_rss & RSS_TUN_GENEVE_ENA) 486 ethdev_rss |= ETH_RSS_GENEVE; 487 488 if (nic_rss & RSS_TUN_NVGRE_ENA) 489 ethdev_rss |= ETH_RSS_NVGRE; 490 } 491 return ethdev_rss; 492 } 493 494 static int 495 nicvf_dev_reta_query(struct rte_eth_dev *dev, 496 struct rte_eth_rss_reta_entry64 *reta_conf, 497 uint16_t reta_size) 498 { 499 struct nicvf *nic = nicvf_pmd_priv(dev); 500 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 501 int ret, i, j; 502 503 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 504 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 505 "(%d) doesn't match the number hardware can supported " 506 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 507 return -EINVAL; 508 } 509 510 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 511 if (ret) 512 return ret; 513 514 /* Copy RETA table */ 515 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 516 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 517 if ((reta_conf[i].mask >> j) & 0x01) 518 reta_conf[i].reta[j] = tbl[j]; 519 } 520 521 return 0; 522 } 523 524 static int 525 nicvf_dev_reta_update(struct rte_eth_dev *dev, 526 struct rte_eth_rss_reta_entry64 *reta_conf, 527 uint16_t reta_size) 528 { 529 struct nicvf *nic = nicvf_pmd_priv(dev); 530 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 531 int ret, i, j; 532 533 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 534 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 535 "(%d) doesn't match the number hardware can supported " 536 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 537 return -EINVAL; 538 } 539 540 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 541 if (ret) 542 return ret; 543 544 /* Copy RETA table */ 545 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 546 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 547 if ((reta_conf[i].mask >> j) & 0x01) 548 tbl[j] = reta_conf[i].reta[j]; 549 } 550 551 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 552 } 553 554 static int 555 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 556 struct rte_eth_rss_conf *rss_conf) 557 { 558 struct nicvf *nic = nicvf_pmd_priv(dev); 559 560 if (rss_conf->rss_key) 561 nicvf_rss_get_key(nic, rss_conf->rss_key); 562 563 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 564 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 565 return 0; 566 } 567 568 static int 569 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 570 struct rte_eth_rss_conf *rss_conf) 571 { 572 struct nicvf *nic = nicvf_pmd_priv(dev); 573 uint64_t nic_rss; 574 575 if (rss_conf->rss_key && 576 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 577 RTE_LOG(ERR, PMD, "Hash key size mismatch %d", 578 rss_conf->rss_key_len); 579 return -EINVAL; 580 } 581 582 if (rss_conf->rss_key) 583 nicvf_rss_set_key(nic, rss_conf->rss_key); 584 585 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 586 nicvf_rss_set_cfg(nic, nic_rss); 587 return 0; 588 } 589 590 static int 591 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 592 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 593 { 594 const struct rte_memzone *rz; 595 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 596 597 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 598 nicvf_netdev_qidx(nic, qidx), ring_size, 599 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 600 if (rz == NULL) { 601 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 602 return -ENOMEM; 603 } 604 605 memset(rz->addr, 0, ring_size); 606 607 rxq->phys = rz->phys_addr; 608 rxq->desc = rz->addr; 609 rxq->qlen_mask = desc_cnt - 1; 610 611 return 0; 612 } 613 614 static int 615 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 616 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 617 { 618 const struct rte_memzone *rz; 619 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 620 621 rz = rte_eth_dma_zone_reserve(dev, "sq", 622 nicvf_netdev_qidx(nic, qidx), ring_size, 623 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 624 if (rz == NULL) { 625 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 626 return -ENOMEM; 627 } 628 629 memset(rz->addr, 0, ring_size); 630 631 sq->phys = rz->phys_addr; 632 sq->desc = rz->addr; 633 sq->qlen_mask = desc_cnt - 1; 634 635 return 0; 636 } 637 638 static int 639 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 640 uint32_t desc_cnt, uint32_t buffsz) 641 { 642 struct nicvf_rbdr *rbdr; 643 const struct rte_memzone *rz; 644 uint32_t ring_size; 645 646 assert(nic->rbdr == NULL); 647 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 648 RTE_CACHE_LINE_SIZE, nic->node); 649 if (rbdr == NULL) { 650 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 651 return -ENOMEM; 652 } 653 654 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 655 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 656 nicvf_netdev_qidx(nic, 0), ring_size, 657 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 658 if (rz == NULL) { 659 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 660 return -ENOMEM; 661 } 662 663 memset(rz->addr, 0, ring_size); 664 665 rbdr->phys = rz->phys_addr; 666 rbdr->tail = 0; 667 rbdr->next_tail = 0; 668 rbdr->desc = rz->addr; 669 rbdr->buffsz = buffsz; 670 rbdr->qlen_mask = desc_cnt - 1; 671 rbdr->rbdr_status = 672 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 673 rbdr->rbdr_door = 674 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 675 676 nic->rbdr = rbdr; 677 return 0; 678 } 679 680 static void 681 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 682 nicvf_phys_addr_t phy) 683 { 684 uint16_t qidx; 685 void *obj; 686 struct nicvf_rxq *rxq; 687 uint16_t rx_start, rx_end; 688 689 /* Get queue ranges for this VF */ 690 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 691 692 for (qidx = rx_start; qidx <= rx_end; qidx++) { 693 rxq = dev->data->rx_queues[qidx]; 694 if (rxq->precharge_cnt) { 695 obj = (void *)nicvf_mbuff_phy2virt(phy, 696 rxq->mbuf_phys_off); 697 rte_mempool_put(rxq->pool, obj); 698 rxq->precharge_cnt--; 699 break; 700 } 701 } 702 } 703 704 static inline void 705 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 706 { 707 uint32_t qlen_mask, head; 708 struct rbdr_entry_t *entry; 709 struct nicvf_rbdr *rbdr = nic->rbdr; 710 711 qlen_mask = rbdr->qlen_mask; 712 head = rbdr->head; 713 while (head != rbdr->tail) { 714 entry = rbdr->desc + head; 715 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 716 head++; 717 head = head & qlen_mask; 718 } 719 } 720 721 static inline void 722 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 723 { 724 uint32_t head; 725 726 head = txq->head; 727 while (head != txq->tail) { 728 if (txq->txbuffs[head]) { 729 rte_pktmbuf_free_seg(txq->txbuffs[head]); 730 txq->txbuffs[head] = NULL; 731 } 732 head++; 733 head = head & txq->qlen_mask; 734 } 735 } 736 737 static void 738 nicvf_tx_queue_reset(struct nicvf_txq *txq) 739 { 740 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 741 742 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 743 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 744 txq->tail = 0; 745 txq->head = 0; 746 txq->xmit_bufs = 0; 747 } 748 749 static inline int 750 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 751 uint16_t qidx) 752 { 753 struct nicvf_txq *txq; 754 int ret; 755 756 assert(qidx < MAX_SND_QUEUES_PER_QS); 757 758 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 759 RTE_ETH_QUEUE_STATE_STARTED) 760 return 0; 761 762 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 763 txq->pool = NULL; 764 ret = nicvf_qset_sq_config(nic, qidx, txq); 765 if (ret) { 766 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 767 nic->vf_id, qidx, ret); 768 goto config_sq_error; 769 } 770 771 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 772 RTE_ETH_QUEUE_STATE_STARTED; 773 return ret; 774 775 config_sq_error: 776 nicvf_qset_sq_reclaim(nic, qidx); 777 return ret; 778 } 779 780 static inline int 781 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 782 uint16_t qidx) 783 { 784 struct nicvf_txq *txq; 785 int ret; 786 787 assert(qidx < MAX_SND_QUEUES_PER_QS); 788 789 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 790 RTE_ETH_QUEUE_STATE_STOPPED) 791 return 0; 792 793 ret = nicvf_qset_sq_reclaim(nic, qidx); 794 if (ret) 795 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 796 nic->vf_id, qidx, ret); 797 798 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 799 nicvf_tx_queue_release_mbufs(txq); 800 nicvf_tx_queue_reset(txq); 801 802 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 803 RTE_ETH_QUEUE_STATE_STOPPED; 804 return ret; 805 } 806 807 static inline int 808 nicvf_configure_cpi(struct rte_eth_dev *dev) 809 { 810 struct nicvf *nic = nicvf_pmd_priv(dev); 811 uint16_t qidx, qcnt; 812 int ret; 813 814 /* Count started rx queues */ 815 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 816 if (dev->data->rx_queue_state[qidx] == 817 RTE_ETH_QUEUE_STATE_STARTED) 818 qcnt++; 819 820 nic->cpi_alg = CPI_ALG_NONE; 821 ret = nicvf_mbox_config_cpi(nic, qcnt); 822 if (ret) 823 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 824 825 return ret; 826 } 827 828 static inline int 829 nicvf_configure_rss(struct rte_eth_dev *dev) 830 { 831 struct nicvf *nic = nicvf_pmd_priv(dev); 832 uint64_t rsshf; 833 int ret = -EINVAL; 834 835 rsshf = nicvf_rss_ethdev_to_nic(nic, 836 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 837 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 838 dev->data->dev_conf.rxmode.mq_mode, 839 dev->data->nb_rx_queues, 840 dev->data->dev_conf.lpbk_mode, rsshf); 841 842 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 843 ret = nicvf_rss_term(nic); 844 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 845 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 846 if (ret) 847 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 848 849 return ret; 850 } 851 852 static int 853 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 854 { 855 struct nicvf *nic = nicvf_pmd_priv(dev); 856 unsigned int idx, qmap_size; 857 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 858 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 859 860 if (nic->cpi_alg != CPI_ALG_NONE) 861 return -EINVAL; 862 863 /* Prepare queue map */ 864 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 865 if (dev->data->rx_queue_state[idx] == 866 RTE_ETH_QUEUE_STATE_STARTED) 867 qmap[qmap_size++] = idx; 868 } 869 870 /* Update default RSS RETA */ 871 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 872 default_reta[idx] = qmap[idx % qmap_size]; 873 874 return nicvf_rss_reta_update(nic, default_reta, 875 NIC_MAX_RSS_IDR_TBL_SIZE); 876 } 877 878 static void 879 nicvf_dev_tx_queue_release(void *sq) 880 { 881 struct nicvf_txq *txq; 882 883 PMD_INIT_FUNC_TRACE(); 884 885 txq = (struct nicvf_txq *)sq; 886 if (txq) { 887 if (txq->txbuffs != NULL) { 888 nicvf_tx_queue_release_mbufs(txq); 889 rte_free(txq->txbuffs); 890 txq->txbuffs = NULL; 891 } 892 rte_free(txq); 893 } 894 } 895 896 static void 897 nicvf_set_tx_function(struct rte_eth_dev *dev) 898 { 899 struct nicvf_txq *txq; 900 size_t i; 901 bool multiseg = false; 902 903 for (i = 0; i < dev->data->nb_tx_queues; i++) { 904 txq = dev->data->tx_queues[i]; 905 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) { 906 multiseg = true; 907 break; 908 } 909 } 910 911 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 912 if (multiseg) { 913 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 914 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 915 } else { 916 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 917 dev->tx_pkt_burst = nicvf_xmit_pkts; 918 } 919 920 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 921 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 922 else 923 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 924 } 925 926 static void 927 nicvf_set_rx_function(struct rte_eth_dev *dev) 928 { 929 if (dev->data->scattered_rx) { 930 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback"); 931 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg; 932 } else { 933 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback"); 934 dev->rx_pkt_burst = nicvf_recv_pkts; 935 } 936 } 937 938 static int 939 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 940 uint16_t nb_desc, unsigned int socket_id, 941 const struct rte_eth_txconf *tx_conf) 942 { 943 uint16_t tx_free_thresh; 944 uint8_t is_single_pool; 945 struct nicvf_txq *txq; 946 struct nicvf *nic = nicvf_pmd_priv(dev); 947 948 PMD_INIT_FUNC_TRACE(); 949 950 if (qidx >= MAX_SND_QUEUES_PER_QS) 951 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 952 953 qidx = qidx % MAX_SND_QUEUES_PER_QS; 954 955 /* Socket id check */ 956 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 957 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 958 socket_id, nic->node); 959 960 /* Tx deferred start is not supported */ 961 if (tx_conf->tx_deferred_start) { 962 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 963 return -EINVAL; 964 } 965 966 /* Roundup nb_desc to available qsize and validate max number of desc */ 967 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 968 if (nb_desc == 0) { 969 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 970 return -EINVAL; 971 } 972 973 /* Validate tx_free_thresh */ 974 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 975 tx_conf->tx_free_thresh : 976 NICVF_DEFAULT_TX_FREE_THRESH); 977 978 if (tx_free_thresh > (nb_desc) || 979 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 980 PMD_INIT_LOG(ERR, 981 "tx_free_thresh must be less than the number of TX " 982 "descriptors. (tx_free_thresh=%u port=%d " 983 "queue=%d)", (unsigned int)tx_free_thresh, 984 (int)dev->data->port_id, (int)qidx); 985 return -EINVAL; 986 } 987 988 /* Free memory prior to re-allocation if needed. */ 989 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 990 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 991 nicvf_netdev_qidx(nic, qidx)); 992 nicvf_dev_tx_queue_release( 993 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]); 994 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 995 } 996 997 /* Allocating tx queue data structure */ 998 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 999 RTE_CACHE_LINE_SIZE, nic->node); 1000 if (txq == NULL) { 1001 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 1002 nicvf_netdev_qidx(nic, qidx)); 1003 return -ENOMEM; 1004 } 1005 1006 txq->nic = nic; 1007 txq->queue_id = qidx; 1008 txq->tx_free_thresh = tx_free_thresh; 1009 txq->txq_flags = tx_conf->txq_flags; 1010 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1011 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1012 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT && 1013 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP); 1014 1015 /* Choose optimum free threshold value for multipool case */ 1016 if (!is_single_pool) { 1017 txq->tx_free_thresh = (uint16_t) 1018 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1019 NICVF_TX_FREE_MPOOL_THRESH : 1020 tx_conf->tx_free_thresh); 1021 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1022 } else { 1023 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1024 } 1025 1026 /* Allocate software ring */ 1027 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1028 nb_desc * sizeof(struct rte_mbuf *), 1029 RTE_CACHE_LINE_SIZE, nic->node); 1030 1031 if (txq->txbuffs == NULL) { 1032 nicvf_dev_tx_queue_release(txq); 1033 return -ENOMEM; 1034 } 1035 1036 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1037 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1038 nicvf_dev_tx_queue_release(txq); 1039 return -ENOMEM; 1040 } 1041 1042 nicvf_tx_queue_reset(txq); 1043 1044 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64, 1045 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1046 txq->phys); 1047 1048 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1049 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1050 RTE_ETH_QUEUE_STATE_STOPPED; 1051 return 0; 1052 } 1053 1054 static inline void 1055 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1056 { 1057 uint32_t rxq_cnt; 1058 uint32_t nb_pkts, released_pkts = 0; 1059 uint32_t refill_cnt = 0; 1060 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1061 1062 if (dev->rx_pkt_burst == NULL) 1063 return; 1064 1065 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, 1066 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) { 1067 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1068 NICVF_MAX_RX_FREE_THRESH); 1069 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1070 while (nb_pkts) { 1071 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1072 released_pkts++; 1073 } 1074 } 1075 1076 1077 refill_cnt += nicvf_dev_rbdr_refill(dev, 1078 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1079 1080 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1081 released_pkts, refill_cnt); 1082 } 1083 1084 static void 1085 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1086 { 1087 rxq->head = 0; 1088 rxq->available_space = 0; 1089 rxq->recv_buffers = 0; 1090 } 1091 1092 static inline int 1093 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1094 uint16_t qidx) 1095 { 1096 struct nicvf_rxq *rxq; 1097 int ret; 1098 1099 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1100 1101 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1102 RTE_ETH_QUEUE_STATE_STARTED) 1103 return 0; 1104 1105 /* Update rbdr pointer to all rxq */ 1106 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1107 rxq->shared_rbdr = nic->rbdr; 1108 1109 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1110 if (ret) { 1111 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1112 nic->vf_id, qidx, ret); 1113 goto config_rq_error; 1114 } 1115 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1116 if (ret) { 1117 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1118 nic->vf_id, qidx, ret); 1119 goto config_cq_error; 1120 } 1121 1122 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1123 RTE_ETH_QUEUE_STATE_STARTED; 1124 return 0; 1125 1126 config_cq_error: 1127 nicvf_qset_cq_reclaim(nic, qidx); 1128 config_rq_error: 1129 nicvf_qset_rq_reclaim(nic, qidx); 1130 return ret; 1131 } 1132 1133 static inline int 1134 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1135 uint16_t qidx) 1136 { 1137 struct nicvf_rxq *rxq; 1138 int ret, other_error; 1139 1140 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1141 RTE_ETH_QUEUE_STATE_STOPPED) 1142 return 0; 1143 1144 ret = nicvf_qset_rq_reclaim(nic, qidx); 1145 if (ret) 1146 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1147 nic->vf_id, qidx, ret); 1148 1149 other_error = ret; 1150 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1151 nicvf_rx_queue_release_mbufs(dev, rxq); 1152 nicvf_rx_queue_reset(rxq); 1153 1154 ret = nicvf_qset_cq_reclaim(nic, qidx); 1155 if (ret) 1156 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1157 nic->vf_id, qidx, ret); 1158 1159 other_error |= ret; 1160 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1161 RTE_ETH_QUEUE_STATE_STOPPED; 1162 return other_error; 1163 } 1164 1165 static void 1166 nicvf_dev_rx_queue_release(void *rx_queue) 1167 { 1168 PMD_INIT_FUNC_TRACE(); 1169 1170 rte_free(rx_queue); 1171 } 1172 1173 static int 1174 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1175 { 1176 struct nicvf *nic = nicvf_pmd_priv(dev); 1177 int ret; 1178 1179 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1180 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1181 1182 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1183 1184 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1185 if (ret) 1186 return ret; 1187 1188 ret = nicvf_configure_cpi(dev); 1189 if (ret) 1190 return ret; 1191 1192 return nicvf_configure_rss_reta(dev); 1193 } 1194 1195 static int 1196 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1197 { 1198 int ret; 1199 struct nicvf *nic = nicvf_pmd_priv(dev); 1200 1201 if (qidx >= MAX_SND_QUEUES_PER_QS) 1202 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1203 1204 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1205 1206 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1207 ret |= nicvf_configure_cpi(dev); 1208 ret |= nicvf_configure_rss_reta(dev); 1209 return ret; 1210 } 1211 1212 static int 1213 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1214 { 1215 struct nicvf *nic = nicvf_pmd_priv(dev); 1216 1217 if (qidx >= MAX_SND_QUEUES_PER_QS) 1218 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1219 1220 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1221 1222 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1223 } 1224 1225 static int 1226 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1227 { 1228 struct nicvf *nic = nicvf_pmd_priv(dev); 1229 1230 if (qidx >= MAX_SND_QUEUES_PER_QS) 1231 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1232 1233 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1234 1235 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1236 } 1237 1238 static inline void 1239 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1240 { 1241 uintptr_t p; 1242 struct rte_mbuf mb_def; 1243 1244 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1245 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1246 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1247 offsetof(struct rte_mbuf, data_off) != 2); 1248 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1249 offsetof(struct rte_mbuf, data_off) != 4); 1250 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1251 offsetof(struct rte_mbuf, data_off) != 6); 1252 mb_def.nb_segs = 1; 1253 mb_def.data_off = RTE_PKTMBUF_HEADROOM; 1254 mb_def.port = rxq->port_id; 1255 rte_mbuf_refcnt_set(&mb_def, 1); 1256 1257 /* Prevent compiler reordering: rearm_data covers previous fields */ 1258 rte_compiler_barrier(); 1259 p = (uintptr_t)&mb_def.rearm_data; 1260 rxq->mbuf_initializer.value = *(uint64_t *)p; 1261 } 1262 1263 static int 1264 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1265 uint16_t nb_desc, unsigned int socket_id, 1266 const struct rte_eth_rxconf *rx_conf, 1267 struct rte_mempool *mp) 1268 { 1269 uint16_t rx_free_thresh; 1270 struct nicvf_rxq *rxq; 1271 struct nicvf *nic = nicvf_pmd_priv(dev); 1272 1273 PMD_INIT_FUNC_TRACE(); 1274 1275 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1276 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1277 1278 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1279 1280 /* Socket id check */ 1281 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1282 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1283 socket_id, nic->node); 1284 1285 /* Mempool memory must be contiguous, so must be one memory segment*/ 1286 if (mp->nb_mem_chunks != 1) { 1287 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1288 return -EINVAL; 1289 } 1290 1291 /* Mempool memory must be physically contiguous */ 1292 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) { 1293 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1294 return -EINVAL; 1295 } 1296 1297 /* Rx deferred start is not supported */ 1298 if (rx_conf->rx_deferred_start) { 1299 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1300 return -EINVAL; 1301 } 1302 1303 /* Roundup nb_desc to available qsize and validate max number of desc */ 1304 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1305 if (nb_desc == 0) { 1306 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1307 return -EINVAL; 1308 } 1309 1310 /* Check rx_free_thresh upper bound */ 1311 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1312 rx_conf->rx_free_thresh : 1313 NICVF_DEFAULT_RX_FREE_THRESH); 1314 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1315 rx_free_thresh >= nb_desc * .75) { 1316 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1317 rx_free_thresh); 1318 return -EINVAL; 1319 } 1320 1321 /* Free memory prior to re-allocation if needed */ 1322 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1323 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1324 nicvf_netdev_qidx(nic, qidx)); 1325 nicvf_dev_rx_queue_release( 1326 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]); 1327 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1328 } 1329 1330 /* Allocate rxq memory */ 1331 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1332 RTE_CACHE_LINE_SIZE, nic->node); 1333 if (rxq == NULL) { 1334 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1335 nicvf_netdev_qidx(nic, qidx)); 1336 return -ENOMEM; 1337 } 1338 1339 rxq->nic = nic; 1340 rxq->pool = mp; 1341 rxq->queue_id = qidx; 1342 rxq->port_id = dev->data->port_id; 1343 rxq->rx_free_thresh = rx_free_thresh; 1344 rxq->rx_drop_en = rx_conf->rx_drop_en; 1345 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1346 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1347 rxq->precharge_cnt = 0; 1348 1349 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1350 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1351 else 1352 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1353 1354 nicvf_rxq_mbuf_setup(rxq); 1355 1356 /* Alloc completion queue */ 1357 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1358 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1359 nicvf_dev_rx_queue_release(rxq); 1360 return -ENOMEM; 1361 } 1362 1363 nicvf_rx_queue_reset(rxq); 1364 1365 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64, 1366 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1367 rte_mempool_avail_count(mp), rxq->phys); 1368 1369 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1370 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1371 RTE_ETH_QUEUE_STATE_STOPPED; 1372 return 0; 1373 } 1374 1375 static void 1376 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1377 { 1378 struct nicvf *nic = nicvf_pmd_priv(dev); 1379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1380 1381 PMD_INIT_FUNC_TRACE(); 1382 1383 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1384 1385 /* Autonegotiation may be disabled */ 1386 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 1387 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 1388 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 1389 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1390 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 1391 1392 dev_info->min_rx_bufsize = ETHER_MIN_MTU; 1393 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS; 1394 dev_info->max_rx_queues = 1395 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1396 dev_info->max_tx_queues = 1397 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1398 dev_info->max_mac_addrs = 1; 1399 dev_info->max_vfs = pci_dev->max_vfs; 1400 1401 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP; 1402 dev_info->tx_offload_capa = 1403 DEV_TX_OFFLOAD_IPV4_CKSUM | 1404 DEV_TX_OFFLOAD_UDP_CKSUM | 1405 DEV_TX_OFFLOAD_TCP_CKSUM | 1406 DEV_TX_OFFLOAD_TCP_TSO | 1407 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 1408 1409 dev_info->reta_size = nic->rss_info.rss_size; 1410 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1411 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1412 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1413 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1414 1415 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1416 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1417 .rx_drop_en = 0, 1418 }; 1419 1420 dev_info->default_txconf = (struct rte_eth_txconf) { 1421 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1422 .txq_flags = 1423 ETH_TXQ_FLAGS_NOMULTSEGS | 1424 ETH_TXQ_FLAGS_NOREFCOUNT | 1425 ETH_TXQ_FLAGS_NOMULTMEMP | 1426 ETH_TXQ_FLAGS_NOVLANOFFL | 1427 ETH_TXQ_FLAGS_NOXSUMSCTP, 1428 }; 1429 } 1430 1431 static nicvf_phys_addr_t 1432 rbdr_rte_mempool_get(void *dev, void *opaque) 1433 { 1434 uint16_t qidx; 1435 uintptr_t mbuf; 1436 struct nicvf_rxq *rxq; 1437 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1438 struct nicvf *nic = (struct nicvf *)opaque; 1439 uint16_t rx_start, rx_end; 1440 1441 /* Get queue ranges for this VF */ 1442 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1443 1444 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1445 rxq = eth_dev->data->rx_queues[qidx]; 1446 /* Maintain equal buffer count across all pools */ 1447 if (rxq->precharge_cnt >= rxq->qlen_mask) 1448 continue; 1449 rxq->precharge_cnt++; 1450 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1451 if (mbuf) 1452 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1453 } 1454 return 0; 1455 } 1456 1457 static int 1458 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1459 { 1460 int ret; 1461 uint16_t qidx, data_off; 1462 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1463 uint64_t mbuf_phys_off = 0; 1464 struct nicvf_rxq *rxq; 1465 struct rte_mbuf *mbuf; 1466 uint16_t rx_start, rx_end; 1467 uint16_t tx_start, tx_end; 1468 1469 PMD_INIT_FUNC_TRACE(); 1470 1471 /* Userspace process exited without proper shutdown in last run */ 1472 if (nicvf_qset_rbdr_active(nic, 0)) 1473 nicvf_vf_stop(dev, nic, false); 1474 1475 /* Get queue ranges for this VF */ 1476 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1477 1478 /* 1479 * Thunderx nicvf PMD can support more than one pool per port only when 1480 * 1) Data payload size is same across all the pools in given port 1481 * AND 1482 * 2) All mbuffs in the pools are from the same hugepage 1483 * AND 1484 * 3) Mbuff metadata size is same across all the pools in given port 1485 * 1486 * This is to support existing application that uses multiple pool/port. 1487 * But, the purpose of using multipool for QoS will not be addressed. 1488 * 1489 */ 1490 1491 /* Validate mempool attributes */ 1492 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1493 rxq = dev->data->rx_queues[qidx]; 1494 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1495 mbuf = rte_pktmbuf_alloc(rxq->pool); 1496 if (mbuf == NULL) { 1497 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1498 "pool=%s", 1499 nic->vf_id, qidx, rxq->pool->name); 1500 return -ENOMEM; 1501 } 1502 data_off = nicvf_mbuff_meta_length(mbuf); 1503 data_off += RTE_PKTMBUF_HEADROOM; 1504 rte_pktmbuf_free(mbuf); 1505 1506 if (data_off % RTE_CACHE_LINE_SIZE) { 1507 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1508 rxq->pool->name, data_off, 1509 data_off % RTE_CACHE_LINE_SIZE); 1510 return -EINVAL; 1511 } 1512 rxq->mbuf_phys_off -= data_off; 1513 1514 if (mbuf_phys_off == 0) 1515 mbuf_phys_off = rxq->mbuf_phys_off; 1516 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1517 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1518 PRIx64, rxq->pool->name, nic->vf_id, 1519 mbuf_phys_off); 1520 return -EINVAL; 1521 } 1522 } 1523 1524 /* Check the level of buffers in the pool */ 1525 total_rxq_desc = 0; 1526 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1527 rxq = dev->data->rx_queues[qidx]; 1528 /* Count total numbers of rxq descs */ 1529 total_rxq_desc += rxq->qlen_mask + 1; 1530 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1531 exp_buffs *= dev->data->nb_rx_queues; 1532 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1533 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1534 rxq->pool->name, 1535 rte_mempool_avail_count(rxq->pool), 1536 exp_buffs); 1537 return -ENOENT; 1538 } 1539 } 1540 1541 /* Check RBDR desc overflow */ 1542 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1543 if (ret == 0) { 1544 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1545 "VF%d", nic->vf_id); 1546 return -ENOMEM; 1547 } 1548 1549 /* Enable qset */ 1550 ret = nicvf_qset_config(nic); 1551 if (ret) { 1552 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1553 nic->vf_id); 1554 return ret; 1555 } 1556 1557 /* Allocate RBDR and RBDR ring desc */ 1558 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1559 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1560 if (ret) { 1561 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1562 "VF%d", nic->vf_id); 1563 goto qset_reclaim; 1564 } 1565 1566 /* Enable and configure RBDR registers */ 1567 ret = nicvf_qset_rbdr_config(nic, 0); 1568 if (ret) { 1569 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1570 nic->vf_id); 1571 goto qset_rbdr_free; 1572 } 1573 1574 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1575 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1576 total_rxq_desc); 1577 if (ret) { 1578 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1579 nic->vf_id); 1580 goto qset_rbdr_reclaim; 1581 } 1582 1583 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1584 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1585 1586 /* Configure VLAN Strip */ 1587 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip); 1588 1589 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1590 * to the 64bit memory address. 1591 * The alignment creates a hole in mbuf(between the end of headroom and 1592 * packet data start). The new revision of the HW provides an option to 1593 * disable the L3 alignment feature and make mbuf layout looks 1594 * more like other NICs. For better application compatibility, disabling 1595 * l3 alignment feature on the hardware revisions it supports 1596 */ 1597 nicvf_apad_config(nic, false); 1598 1599 /* Get queue ranges for this VF */ 1600 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1601 1602 /* Configure TX queues */ 1603 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1604 ret = nicvf_vf_start_tx_queue(dev, nic, 1605 qidx % MAX_SND_QUEUES_PER_QS); 1606 if (ret) 1607 goto start_txq_error; 1608 } 1609 1610 /* Configure RX queues */ 1611 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1612 ret = nicvf_vf_start_rx_queue(dev, nic, 1613 qidx % MAX_RCV_QUEUES_PER_QS); 1614 if (ret) 1615 goto start_rxq_error; 1616 } 1617 1618 if (!nic->sqs_mode) { 1619 /* Configure CPI algorithm */ 1620 ret = nicvf_configure_cpi(dev); 1621 if (ret) 1622 goto start_txq_error; 1623 1624 ret = nicvf_mbox_get_rss_size(nic); 1625 if (ret) { 1626 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1627 goto qset_rss_error; 1628 } 1629 1630 /* Configure RSS */ 1631 ret = nicvf_configure_rss(dev); 1632 if (ret) 1633 goto qset_rss_error; 1634 } 1635 1636 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1637 nicvf_mbox_cfg_done(nic); 1638 return 0; 1639 1640 qset_rss_error: 1641 nicvf_rss_term(nic); 1642 start_rxq_error: 1643 for (qidx = rx_start; qidx <= rx_end; qidx++) 1644 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1645 start_txq_error: 1646 for (qidx = tx_start; qidx <= tx_end; qidx++) 1647 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1648 qset_rbdr_reclaim: 1649 nicvf_qset_rbdr_reclaim(nic, 0); 1650 nicvf_rbdr_release_mbufs(dev, nic); 1651 qset_rbdr_free: 1652 if (nic->rbdr) { 1653 rte_free(nic->rbdr); 1654 nic->rbdr = NULL; 1655 } 1656 qset_reclaim: 1657 nicvf_qset_reclaim(nic); 1658 return ret; 1659 } 1660 1661 static int 1662 nicvf_dev_start(struct rte_eth_dev *dev) 1663 { 1664 uint16_t qidx; 1665 int ret; 1666 size_t i; 1667 struct nicvf *nic = nicvf_pmd_priv(dev); 1668 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1669 uint16_t mtu; 1670 uint32_t buffsz = 0, rbdrsz = 0; 1671 struct rte_pktmbuf_pool_private *mbp_priv; 1672 struct nicvf_rxq *rxq; 1673 1674 PMD_INIT_FUNC_TRACE(); 1675 1676 /* This function must be called for a primary device */ 1677 assert_primary(nic); 1678 1679 /* Validate RBDR buff size */ 1680 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1681 rxq = dev->data->rx_queues[qidx]; 1682 mbp_priv = rte_mempool_get_priv(rxq->pool); 1683 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1684 if (buffsz % 128) { 1685 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1686 return -EINVAL; 1687 } 1688 if (rbdrsz == 0) 1689 rbdrsz = buffsz; 1690 if (rbdrsz != buffsz) { 1691 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1692 qidx, rbdrsz, buffsz); 1693 return -EINVAL; 1694 } 1695 } 1696 1697 /* Configure loopback */ 1698 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1699 if (ret) { 1700 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1701 return ret; 1702 } 1703 1704 /* Reset all statistics counters attached to this port */ 1705 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1706 if (ret) { 1707 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1708 return ret; 1709 } 1710 1711 /* Setup scatter mode if needed by jumbo */ 1712 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1713 2 * VLAN_TAG_SIZE > buffsz) 1714 dev->data->scattered_rx = 1; 1715 if (rx_conf->enable_scatter) 1716 dev->data->scattered_rx = 1; 1717 1718 /* Setup MTU based on max_rx_pkt_len or default */ 1719 mtu = dev->data->dev_conf.rxmode.jumbo_frame ? 1720 dev->data->dev_conf.rxmode.max_rx_pkt_len 1721 - ETHER_HDR_LEN - ETHER_CRC_LEN 1722 : ETHER_MTU; 1723 1724 if (nicvf_dev_set_mtu(dev, mtu)) { 1725 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1726 return -EBUSY; 1727 } 1728 1729 ret = nicvf_vf_start(dev, nic, rbdrsz); 1730 if (ret != 0) 1731 return ret; 1732 1733 for (i = 0; i < nic->sqs_count; i++) { 1734 assert(nic->snicvf[i]); 1735 1736 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1737 if (ret != 0) 1738 return ret; 1739 } 1740 1741 /* Configure callbacks based on scatter mode */ 1742 nicvf_set_tx_function(dev); 1743 nicvf_set_rx_function(dev); 1744 1745 return 0; 1746 } 1747 1748 static void 1749 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1750 { 1751 size_t i; 1752 int ret; 1753 struct nicvf *nic = nicvf_pmd_priv(dev); 1754 1755 PMD_INIT_FUNC_TRACE(); 1756 1757 /* Teardown secondary vf first */ 1758 for (i = 0; i < nic->sqs_count; i++) { 1759 if (!nic->snicvf[i]) 1760 continue; 1761 1762 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1763 } 1764 1765 /* Stop the primary VF now */ 1766 nicvf_vf_stop(dev, nic, cleanup); 1767 1768 /* Disable loopback */ 1769 ret = nicvf_loopback_config(nic, 0); 1770 if (ret) 1771 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1772 1773 /* Reclaim CPI configuration */ 1774 ret = nicvf_mbox_config_cpi(nic, 0); 1775 if (ret) 1776 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1777 } 1778 1779 static void 1780 nicvf_dev_stop(struct rte_eth_dev *dev) 1781 { 1782 PMD_INIT_FUNC_TRACE(); 1783 1784 nicvf_dev_stop_cleanup(dev, false); 1785 } 1786 1787 static void 1788 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1789 { 1790 int ret; 1791 uint16_t qidx; 1792 uint16_t tx_start, tx_end; 1793 uint16_t rx_start, rx_end; 1794 1795 PMD_INIT_FUNC_TRACE(); 1796 1797 if (cleanup) { 1798 /* Let PF make the BGX's RX and TX switches to OFF position */ 1799 nicvf_mbox_shutdown(nic); 1800 } 1801 1802 /* Disable VLAN Strip */ 1803 nicvf_vlan_hw_strip(nic, 0); 1804 1805 /* Get queue ranges for this VF */ 1806 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1807 1808 for (qidx = tx_start; qidx <= tx_end; qidx++) 1809 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1810 1811 /* Get queue ranges for this VF */ 1812 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1813 1814 /* Reclaim rq */ 1815 for (qidx = rx_start; qidx <= rx_end; qidx++) 1816 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1817 1818 /* Reclaim RBDR */ 1819 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1820 if (ret) 1821 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1822 1823 /* Move all charged buffers in RBDR back to pool */ 1824 if (nic->rbdr != NULL) 1825 nicvf_rbdr_release_mbufs(dev, nic); 1826 1827 /* Disable qset */ 1828 ret = nicvf_qset_reclaim(nic); 1829 if (ret) 1830 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1831 1832 /* Disable all interrupts */ 1833 nicvf_disable_all_interrupts(nic); 1834 1835 /* Free RBDR SW structure */ 1836 if (nic->rbdr) { 1837 rte_free(nic->rbdr); 1838 nic->rbdr = NULL; 1839 } 1840 } 1841 1842 static void 1843 nicvf_dev_close(struct rte_eth_dev *dev) 1844 { 1845 size_t i; 1846 struct nicvf *nic = nicvf_pmd_priv(dev); 1847 1848 PMD_INIT_FUNC_TRACE(); 1849 1850 nicvf_dev_stop_cleanup(dev, true); 1851 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1852 1853 for (i = 0; i < nic->sqs_count; i++) { 1854 if (!nic->snicvf[i]) 1855 continue; 1856 1857 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); 1858 } 1859 } 1860 1861 static int 1862 nicvf_request_sqs(struct nicvf *nic) 1863 { 1864 size_t i; 1865 1866 assert_primary(nic); 1867 assert(nic->sqs_count > 0); 1868 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1869 1870 /* Set no of Rx/Tx queues in each of the SQsets */ 1871 for (i = 0; i < nic->sqs_count; i++) { 1872 if (nicvf_svf_empty()) 1873 rte_panic("Cannot assign sufficient number of " 1874 "secondary queues to primary VF%" PRIu8 "\n", 1875 nic->vf_id); 1876 1877 nic->snicvf[i] = nicvf_svf_pop(); 1878 nic->snicvf[i]->sqs_id = i; 1879 } 1880 1881 return nicvf_mbox_request_sqs(nic); 1882 } 1883 1884 static int 1885 nicvf_dev_configure(struct rte_eth_dev *dev) 1886 { 1887 struct rte_eth_dev_data *data = dev->data; 1888 struct rte_eth_conf *conf = &data->dev_conf; 1889 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1890 struct rte_eth_txmode *txmode = &conf->txmode; 1891 struct nicvf *nic = nicvf_pmd_priv(dev); 1892 uint8_t cqcount; 1893 1894 PMD_INIT_FUNC_TRACE(); 1895 1896 if (!rte_eal_has_hugepages()) { 1897 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1898 return -EINVAL; 1899 } 1900 1901 if (txmode->mq_mode) { 1902 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1903 return -EINVAL; 1904 } 1905 1906 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1907 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1908 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1909 return -EINVAL; 1910 } 1911 1912 if (!rxmode->hw_strip_crc) { 1913 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip"); 1914 rxmode->hw_strip_crc = 1; 1915 } 1916 1917 if (rxmode->hw_ip_checksum) { 1918 PMD_INIT_LOG(NOTICE, "Rxcksum not supported"); 1919 rxmode->hw_ip_checksum = 0; 1920 } 1921 1922 if (rxmode->split_hdr_size) { 1923 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1924 return -EINVAL; 1925 } 1926 1927 if (rxmode->hw_vlan_filter) { 1928 PMD_INIT_LOG(INFO, "VLAN filter not supported"); 1929 return -EINVAL; 1930 } 1931 1932 if (rxmode->hw_vlan_extend) { 1933 PMD_INIT_LOG(INFO, "VLAN extended not supported"); 1934 return -EINVAL; 1935 } 1936 1937 if (rxmode->enable_lro) { 1938 PMD_INIT_LOG(INFO, "LRO not supported"); 1939 return -EINVAL; 1940 } 1941 1942 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1943 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1944 return -EINVAL; 1945 } 1946 1947 if (conf->dcb_capability_en) { 1948 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1949 return -EINVAL; 1950 } 1951 1952 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1953 PMD_INIT_LOG(INFO, "Flow director not supported"); 1954 return -EINVAL; 1955 } 1956 1957 assert_primary(nic); 1958 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1959 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1960 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1961 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1962 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1963 } else { 1964 nic->sqs_count = 0; 1965 } 1966 1967 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1968 1969 if (nic->sqs_count > 0) { 1970 if (nicvf_request_sqs(nic)) { 1971 rte_panic("Cannot assign sufficient number of " 1972 "secondary queues to PORT%d VF%" PRIu8 "\n", 1973 dev->data->port_id, nic->vf_id); 1974 } 1975 } 1976 1977 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1978 dev->data->port_id, nicvf_hw_cap(nic)); 1979 1980 return 0; 1981 } 1982 1983 /* Initialize and register driver with DPDK Application */ 1984 static const struct eth_dev_ops nicvf_eth_dev_ops = { 1985 .dev_configure = nicvf_dev_configure, 1986 .dev_start = nicvf_dev_start, 1987 .dev_stop = nicvf_dev_stop, 1988 .link_update = nicvf_dev_link_update, 1989 .dev_close = nicvf_dev_close, 1990 .stats_get = nicvf_dev_stats_get, 1991 .stats_reset = nicvf_dev_stats_reset, 1992 .promiscuous_enable = nicvf_dev_promisc_enable, 1993 .dev_infos_get = nicvf_dev_info_get, 1994 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 1995 .mtu_set = nicvf_dev_set_mtu, 1996 .reta_update = nicvf_dev_reta_update, 1997 .reta_query = nicvf_dev_reta_query, 1998 .rss_hash_update = nicvf_dev_rss_hash_update, 1999 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2000 .rx_queue_start = nicvf_dev_rx_queue_start, 2001 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2002 .tx_queue_start = nicvf_dev_tx_queue_start, 2003 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2004 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2005 .rx_queue_release = nicvf_dev_rx_queue_release, 2006 .rx_queue_count = nicvf_dev_rx_queue_count, 2007 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2008 .tx_queue_release = nicvf_dev_tx_queue_release, 2009 .get_reg = nicvf_dev_get_regs, 2010 }; 2011 2012 static int 2013 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2014 { 2015 int ret; 2016 struct rte_pci_device *pci_dev; 2017 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2018 2019 PMD_INIT_FUNC_TRACE(); 2020 2021 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2022 2023 /* For secondary processes, the primary has done all the work */ 2024 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2025 if (nic) { 2026 /* Setup callbacks for secondary process */ 2027 nicvf_set_tx_function(eth_dev); 2028 nicvf_set_rx_function(eth_dev); 2029 return 0; 2030 } else { 2031 /* If nic == NULL than it is secondary function 2032 * so ethdev need to be released by caller */ 2033 return ENOTSUP; 2034 } 2035 } 2036 2037 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2038 rte_eth_copy_pci_info(eth_dev, pci_dev); 2039 2040 nic->device_id = pci_dev->id.device_id; 2041 nic->vendor_id = pci_dev->id.vendor_id; 2042 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2043 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2044 2045 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2046 pci_dev->id.vendor_id, pci_dev->id.device_id, 2047 pci_dev->addr.domain, pci_dev->addr.bus, 2048 pci_dev->addr.devid, pci_dev->addr.function); 2049 2050 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2051 if (!nic->reg_base) { 2052 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2053 ret = -ENODEV; 2054 goto fail; 2055 } 2056 2057 nicvf_disable_all_interrupts(nic); 2058 2059 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2060 if (ret) { 2061 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2062 goto fail; 2063 } 2064 2065 ret = nicvf_mbox_check_pf_ready(nic); 2066 if (ret) { 2067 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2068 goto alarm_fail; 2069 } else { 2070 PMD_INIT_LOG(INFO, 2071 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2072 nic->node, nic->vf_id, 2073 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2074 nic->sqs_mode ? "true" : "false", 2075 nic->loopback_supported ? "true" : "false" 2076 ); 2077 } 2078 2079 ret = nicvf_base_init(nic); 2080 if (ret) { 2081 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2082 goto malloc_fail; 2083 } 2084 2085 if (nic->sqs_mode) { 2086 /* Push nic to stack of secondary vfs */ 2087 nicvf_svf_push(nic); 2088 2089 /* Steal nic pointer from the device for further reuse */ 2090 eth_dev->data->dev_private = NULL; 2091 2092 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2093 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2094 if (ret) { 2095 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2096 goto fail; 2097 } 2098 2099 /* Detach port by returning positive error number */ 2100 return ENOTSUP; 2101 } 2102 2103 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); 2104 if (eth_dev->data->mac_addrs == NULL) { 2105 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2106 ret = -ENOMEM; 2107 goto alarm_fail; 2108 } 2109 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr)) 2110 eth_random_addr(&nic->mac_addr[0]); 2111 2112 ether_addr_copy((struct ether_addr *)nic->mac_addr, 2113 ð_dev->data->mac_addrs[0]); 2114 2115 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2116 if (ret) { 2117 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2118 goto malloc_fail; 2119 } 2120 2121 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 2122 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2123 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2124 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2125 2126 return 0; 2127 2128 malloc_fail: 2129 rte_free(eth_dev->data->mac_addrs); 2130 alarm_fail: 2131 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2132 fail: 2133 return ret; 2134 } 2135 2136 static const struct rte_pci_id pci_id_nicvf_map[] = { 2137 { 2138 .class_id = RTE_CLASS_ANY_ID, 2139 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2140 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2141 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2142 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2143 }, 2144 { 2145 .class_id = RTE_CLASS_ANY_ID, 2146 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2147 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2148 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2149 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2150 }, 2151 { 2152 .class_id = RTE_CLASS_ANY_ID, 2153 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2154 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2155 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2156 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2157 }, 2158 { 2159 .class_id = RTE_CLASS_ANY_ID, 2160 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2161 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2162 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2163 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2164 }, 2165 { 2166 .vendor_id = 0, 2167 }, 2168 }; 2169 2170 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2171 struct rte_pci_device *pci_dev) 2172 { 2173 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2174 nicvf_eth_dev_init); 2175 } 2176 2177 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2178 { 2179 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 2180 } 2181 2182 static struct rte_pci_driver rte_nicvf_pmd = { 2183 .id_table = pci_id_nicvf_map, 2184 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2185 RTE_PCI_DRV_INTR_LSC, 2186 .probe = nicvf_eth_pci_probe, 2187 .remove = nicvf_eth_pci_remove, 2188 }; 2189 2190 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2191 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2192 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2193