1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <rte_dev.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <ethdev_driver.h> 27 #include <ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <rte_bus_pci.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 static int nicvf_dev_stop(struct rte_eth_dev *dev); 48 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 49 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 50 bool cleanup); 51 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 52 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 53 54 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_mbox, mbox, NOTICE); 55 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_init, init, NOTICE); 56 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); 57 58 static void 59 nicvf_link_status_update(struct nicvf *nic, 60 struct rte_eth_link *link) 61 { 62 memset(link, 0, sizeof(*link)); 63 64 link->link_status = nic->link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 65 66 if (nic->duplex == NICVF_HALF_DUPLEX) 67 link->link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 68 else if (nic->duplex == NICVF_FULL_DUPLEX) 69 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 70 link->link_speed = nic->speed; 71 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 72 } 73 74 /*Poll for link status change by sending NIC_MBOX_MSG_BGX_LINK_CHANGE msg 75 * periodically to PF. 76 */ 77 static void 78 nicvf_interrupt(void *arg) 79 { 80 struct rte_eth_dev *dev = arg; 81 struct nicvf *nic = nicvf_pmd_priv(dev); 82 struct rte_eth_link link; 83 84 rte_eth_linkstatus_get(dev, &link); 85 86 nicvf_mbox_link_change(nic); 87 if (nic->link_up != link.link_status) { 88 if (dev->data->dev_conf.intr_conf.lsc) { 89 nicvf_link_status_update(nic, &link); 90 rte_eth_linkstatus_set(dev, &link); 91 92 rte_eth_dev_callback_process(dev, 93 RTE_ETH_EVENT_INTR_LSC, 94 NULL); 95 } 96 } 97 98 rte_eal_alarm_set(NICVF_INTR_LINK_POLL_INTERVAL_MS * 1000, 99 nicvf_interrupt, dev); 100 } 101 102 static void 103 nicvf_vf_interrupt(void *arg) 104 { 105 struct nicvf *nic = arg; 106 107 nicvf_reg_poll_interrupts(nic); 108 109 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 110 nicvf_vf_interrupt, nic); 111 } 112 113 static int 114 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 115 { 116 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 117 } 118 119 static int 120 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 121 { 122 return rte_eal_alarm_cancel(fn, arg); 123 } 124 125 /* 126 * Return 0 means link status changed, -1 means not changed 127 */ 128 static int 129 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 130 { 131 #define CHECK_INTERVAL 100 /* 100ms */ 132 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 133 struct rte_eth_link link; 134 struct nicvf *nic = nicvf_pmd_priv(dev); 135 int i; 136 137 PMD_INIT_FUNC_TRACE(); 138 139 if (wait_to_complete) { 140 /* rte_eth_link_get() might need to wait up to 9 seconds */ 141 for (i = 0; i < MAX_CHECK_TIME; i++) { 142 nicvf_link_status_update(nic, &link); 143 if (link.link_status == RTE_ETH_LINK_UP) 144 break; 145 rte_delay_ms(CHECK_INTERVAL); 146 } 147 } else { 148 nicvf_link_status_update(nic, &link); 149 } 150 151 return rte_eth_linkstatus_set(dev, &link); 152 } 153 154 static int 155 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 156 { 157 struct nicvf *nic = nicvf_pmd_priv(dev); 158 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 159 size_t i; 160 161 PMD_INIT_FUNC_TRACE(); 162 163 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 164 165 /* 166 * Refuse mtu that requires the support of scattered packets 167 * when this feature has not been enabled before. 168 */ 169 if (dev->data->dev_started && !dev->data->scattered_rx && 170 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 171 return -EINVAL; 172 173 /* check <seg size> * <max_seg> >= max_frame */ 174 if (dev->data->scattered_rx && 175 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 176 return -EINVAL; 177 178 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 179 return -EINVAL; 180 181 nic->mtu = mtu; 182 183 for (i = 0; i < nic->sqs_count; i++) 184 nic->snicvf[i]->mtu = mtu; 185 186 return 0; 187 } 188 189 static int 190 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 191 { 192 uint64_t *data = regs->data; 193 struct nicvf *nic = nicvf_pmd_priv(dev); 194 195 if (data == NULL) { 196 regs->length = nicvf_reg_get_count(); 197 regs->width = THUNDERX_REG_BYTES; 198 return 0; 199 } 200 201 /* Support only full register dump */ 202 if ((regs->length == 0) || 203 (regs->length == (uint32_t)nicvf_reg_get_count())) { 204 regs->version = nic->vendor_id << 16 | nic->device_id; 205 nicvf_reg_dump(nic, data); 206 return 0; 207 } 208 return -ENOTSUP; 209 } 210 211 static int 212 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 213 { 214 uint16_t qidx; 215 struct nicvf_hw_rx_qstats rx_qstats; 216 struct nicvf_hw_tx_qstats tx_qstats; 217 struct nicvf_hw_stats port_stats; 218 struct nicvf *nic = nicvf_pmd_priv(dev); 219 uint16_t rx_start, rx_end; 220 uint16_t tx_start, tx_end; 221 size_t i; 222 223 /* RX queue indices for the first VF */ 224 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 225 226 /* Reading per RX ring stats */ 227 for (qidx = rx_start; qidx <= rx_end; qidx++) { 228 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 229 break; 230 231 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 232 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 233 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 234 } 235 236 /* TX queue indices for the first VF */ 237 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 238 239 /* Reading per TX ring stats */ 240 for (qidx = tx_start; qidx <= tx_end; qidx++) { 241 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 242 break; 243 244 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 245 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 246 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 247 } 248 249 for (i = 0; i < nic->sqs_count; i++) { 250 struct nicvf *snic = nic->snicvf[i]; 251 252 if (snic == NULL) 253 break; 254 255 /* RX queue indices for a secondary VF */ 256 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 257 258 /* Reading per RX ring stats */ 259 for (qidx = rx_start; qidx <= rx_end; qidx++) { 260 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 261 break; 262 263 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 264 qidx % MAX_RCV_QUEUES_PER_QS); 265 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 266 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 267 } 268 269 /* TX queue indices for a secondary VF */ 270 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 271 /* Reading per TX ring stats */ 272 for (qidx = tx_start; qidx <= tx_end; qidx++) { 273 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 274 break; 275 276 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 277 qidx % MAX_SND_QUEUES_PER_QS); 278 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 279 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 280 } 281 } 282 283 nicvf_hw_get_stats(nic, &port_stats); 284 stats->ibytes = port_stats.rx_bytes; 285 stats->ipackets = port_stats.rx_ucast_frames; 286 stats->ipackets += port_stats.rx_bcast_frames; 287 stats->ipackets += port_stats.rx_mcast_frames; 288 stats->ierrors = port_stats.rx_l2_errors; 289 stats->imissed = port_stats.rx_drop_red; 290 stats->imissed += port_stats.rx_drop_overrun; 291 stats->imissed += port_stats.rx_drop_bcast; 292 stats->imissed += port_stats.rx_drop_mcast; 293 stats->imissed += port_stats.rx_drop_l3_bcast; 294 stats->imissed += port_stats.rx_drop_l3_mcast; 295 296 stats->obytes = port_stats.tx_bytes_ok; 297 stats->opackets = port_stats.tx_ucast_frames_ok; 298 stats->opackets += port_stats.tx_bcast_frames_ok; 299 stats->opackets += port_stats.tx_mcast_frames_ok; 300 stats->oerrors = port_stats.tx_drops; 301 302 return 0; 303 } 304 305 static const uint32_t * 306 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 307 { 308 size_t copied; 309 static uint32_t ptypes[32]; 310 struct nicvf *nic = nicvf_pmd_priv(dev); 311 static const uint32_t ptypes_common[] = { 312 RTE_PTYPE_L3_IPV4, 313 RTE_PTYPE_L3_IPV4_EXT, 314 RTE_PTYPE_L3_IPV6, 315 RTE_PTYPE_L3_IPV6_EXT, 316 RTE_PTYPE_L4_TCP, 317 RTE_PTYPE_L4_UDP, 318 RTE_PTYPE_L4_FRAG, 319 }; 320 static const uint32_t ptypes_tunnel[] = { 321 RTE_PTYPE_TUNNEL_GRE, 322 RTE_PTYPE_TUNNEL_GENEVE, 323 RTE_PTYPE_TUNNEL_VXLAN, 324 RTE_PTYPE_TUNNEL_NVGRE, 325 }; 326 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 327 328 copied = sizeof(ptypes_common); 329 memcpy(ptypes, ptypes_common, copied); 330 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 331 memcpy((char *)ptypes + copied, ptypes_tunnel, 332 sizeof(ptypes_tunnel)); 333 copied += sizeof(ptypes_tunnel); 334 } 335 336 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 337 338 /* All Ptypes are supported in all Rx functions. */ 339 return ptypes; 340 } 341 342 static int 343 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 344 { 345 int i; 346 uint16_t rxqs = 0, txqs = 0; 347 struct nicvf *nic = nicvf_pmd_priv(dev); 348 uint16_t rx_start, rx_end; 349 uint16_t tx_start, tx_end; 350 int ret; 351 352 /* Reset all primary nic counters */ 353 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 354 for (i = rx_start; i <= rx_end; i++) 355 rxqs |= (0x3 << (i * 2)); 356 357 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 358 for (i = tx_start; i <= tx_end; i++) 359 txqs |= (0x3 << (i * 2)); 360 361 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 362 if (ret != 0) 363 return ret; 364 365 /* Reset secondary nic queue counters */ 366 for (i = 0; i < nic->sqs_count; i++) { 367 struct nicvf *snic = nic->snicvf[i]; 368 if (snic == NULL) 369 break; 370 371 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 372 for (i = rx_start; i <= rx_end; i++) 373 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 374 375 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 376 for (i = tx_start; i <= tx_end; i++) 377 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 378 379 ret = nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 380 if (ret != 0) 381 return ret; 382 } 383 384 return 0; 385 } 386 387 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 388 static int 389 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 390 { 391 return 0; 392 } 393 394 static inline uint64_t 395 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 396 { 397 uint64_t nic_rss = 0; 398 399 if (ethdev_rss & RTE_ETH_RSS_IPV4) 400 nic_rss |= RSS_IP_ENA; 401 402 if (ethdev_rss & RTE_ETH_RSS_IPV6) 403 nic_rss |= RSS_IP_ENA; 404 405 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 406 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 407 408 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 409 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 410 411 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 412 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 413 414 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 415 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 416 417 if (ethdev_rss & RTE_ETH_RSS_PORT) 418 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 419 420 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 421 if (ethdev_rss & RTE_ETH_RSS_VXLAN) 422 nic_rss |= RSS_TUN_VXLAN_ENA; 423 424 if (ethdev_rss & RTE_ETH_RSS_GENEVE) 425 nic_rss |= RSS_TUN_GENEVE_ENA; 426 427 if (ethdev_rss & RTE_ETH_RSS_NVGRE) 428 nic_rss |= RSS_TUN_NVGRE_ENA; 429 } 430 431 return nic_rss; 432 } 433 434 static inline uint64_t 435 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 436 { 437 uint64_t ethdev_rss = 0; 438 439 if (nic_rss & RSS_IP_ENA) 440 ethdev_rss |= (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6); 441 442 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 443 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_TCP | 444 RTE_ETH_RSS_NONFRAG_IPV6_TCP); 445 446 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 447 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_UDP | 448 RTE_ETH_RSS_NONFRAG_IPV6_UDP); 449 450 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 451 ethdev_rss |= RTE_ETH_RSS_PORT; 452 453 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 454 if (nic_rss & RSS_TUN_VXLAN_ENA) 455 ethdev_rss |= RTE_ETH_RSS_VXLAN; 456 457 if (nic_rss & RSS_TUN_GENEVE_ENA) 458 ethdev_rss |= RTE_ETH_RSS_GENEVE; 459 460 if (nic_rss & RSS_TUN_NVGRE_ENA) 461 ethdev_rss |= RTE_ETH_RSS_NVGRE; 462 } 463 return ethdev_rss; 464 } 465 466 static int 467 nicvf_dev_reta_query(struct rte_eth_dev *dev, 468 struct rte_eth_rss_reta_entry64 *reta_conf, 469 uint16_t reta_size) 470 { 471 struct nicvf *nic = nicvf_pmd_priv(dev); 472 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 473 int ret, i, j; 474 475 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 476 PMD_DRV_LOG(ERR, 477 "The size of hash lookup table configured " 478 "(%u) doesn't match the number hardware can supported " 479 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 480 return -EINVAL; 481 } 482 483 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 484 if (ret) 485 return ret; 486 487 /* Copy RETA table */ 488 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 489 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 490 if ((reta_conf[i].mask >> j) & 0x01) 491 reta_conf[i].reta[j] = tbl[j]; 492 } 493 494 return 0; 495 } 496 497 static int 498 nicvf_dev_reta_update(struct rte_eth_dev *dev, 499 struct rte_eth_rss_reta_entry64 *reta_conf, 500 uint16_t reta_size) 501 { 502 struct nicvf *nic = nicvf_pmd_priv(dev); 503 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 504 int ret, i, j; 505 506 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 507 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 508 "(%u) doesn't match the number hardware can supported " 509 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 510 return -EINVAL; 511 } 512 513 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 514 if (ret) 515 return ret; 516 517 /* Copy RETA table */ 518 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 519 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 520 if ((reta_conf[i].mask >> j) & 0x01) 521 tbl[j] = reta_conf[i].reta[j]; 522 } 523 524 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 525 } 526 527 static int 528 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 529 struct rte_eth_rss_conf *rss_conf) 530 { 531 struct nicvf *nic = nicvf_pmd_priv(dev); 532 533 if (rss_conf->rss_key) 534 nicvf_rss_get_key(nic, rss_conf->rss_key); 535 536 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 537 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 538 return 0; 539 } 540 541 static int 542 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 543 struct rte_eth_rss_conf *rss_conf) 544 { 545 struct nicvf *nic = nicvf_pmd_priv(dev); 546 uint64_t nic_rss; 547 548 if (rss_conf->rss_key && 549 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 550 PMD_DRV_LOG(ERR, "Hash key size mismatch %u", 551 rss_conf->rss_key_len); 552 return -EINVAL; 553 } 554 555 if (rss_conf->rss_key) 556 nicvf_rss_set_key(nic, rss_conf->rss_key); 557 558 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 559 nicvf_rss_set_cfg(nic, nic_rss); 560 return 0; 561 } 562 563 static int 564 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 565 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 566 { 567 const struct rte_memzone *rz; 568 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 569 570 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 571 nicvf_netdev_qidx(nic, qidx), ring_size, 572 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 573 if (rz == NULL) { 574 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 575 return -ENOMEM; 576 } 577 578 memset(rz->addr, 0, ring_size); 579 580 rxq->phys = rz->iova; 581 rxq->desc = rz->addr; 582 rxq->qlen_mask = desc_cnt - 1; 583 584 return 0; 585 } 586 587 static int 588 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 589 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 590 { 591 const struct rte_memzone *rz; 592 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 593 594 rz = rte_eth_dma_zone_reserve(dev, "sq", 595 nicvf_netdev_qidx(nic, qidx), ring_size, 596 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 597 if (rz == NULL) { 598 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 599 return -ENOMEM; 600 } 601 602 memset(rz->addr, 0, ring_size); 603 604 sq->phys = rz->iova; 605 sq->desc = rz->addr; 606 sq->qlen_mask = desc_cnt - 1; 607 608 return 0; 609 } 610 611 static int 612 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 613 uint32_t desc_cnt, uint32_t buffsz) 614 { 615 struct nicvf_rbdr *rbdr; 616 const struct rte_memzone *rz; 617 uint32_t ring_size; 618 619 assert(nic->rbdr == NULL); 620 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 621 RTE_CACHE_LINE_SIZE, nic->node); 622 if (rbdr == NULL) { 623 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 624 return -ENOMEM; 625 } 626 627 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 628 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 629 nicvf_netdev_qidx(nic, 0), ring_size, 630 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 631 if (rz == NULL) { 632 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 633 rte_free(rbdr); 634 return -ENOMEM; 635 } 636 637 memset(rz->addr, 0, ring_size); 638 639 rbdr->phys = rz->iova; 640 rbdr->tail = 0; 641 rbdr->next_tail = 0; 642 rbdr->desc = rz->addr; 643 rbdr->buffsz = buffsz; 644 rbdr->qlen_mask = desc_cnt - 1; 645 rbdr->rbdr_status = 646 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 647 rbdr->rbdr_door = 648 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 649 650 nic->rbdr = rbdr; 651 return 0; 652 } 653 654 static void 655 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 656 nicvf_iova_addr_t phy) 657 { 658 uint16_t qidx; 659 void *obj; 660 struct nicvf_rxq *rxq; 661 uint16_t rx_start, rx_end; 662 663 /* Get queue ranges for this VF */ 664 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 665 666 for (qidx = rx_start; qidx <= rx_end; qidx++) { 667 rxq = dev->data->rx_queues[qidx]; 668 if (rxq->precharge_cnt) { 669 obj = (void *)nicvf_mbuff_phy2virt(phy, 670 rxq->mbuf_phys_off); 671 rte_mempool_put(rxq->pool, obj); 672 rxq->precharge_cnt--; 673 break; 674 } 675 } 676 } 677 678 static inline void 679 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 680 { 681 uint32_t qlen_mask, head; 682 struct rbdr_entry_t *entry; 683 struct nicvf_rbdr *rbdr = nic->rbdr; 684 685 qlen_mask = rbdr->qlen_mask; 686 head = rbdr->head; 687 while (head != rbdr->tail) { 688 entry = rbdr->desc + head; 689 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 690 head++; 691 head = head & qlen_mask; 692 } 693 } 694 695 static inline void 696 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 697 { 698 uint32_t head; 699 700 head = txq->head; 701 while (head != txq->tail) { 702 if (txq->txbuffs[head]) { 703 rte_pktmbuf_free_seg(txq->txbuffs[head]); 704 txq->txbuffs[head] = NULL; 705 } 706 head++; 707 head = head & txq->qlen_mask; 708 } 709 } 710 711 static void 712 nicvf_tx_queue_reset(struct nicvf_txq *txq) 713 { 714 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 715 716 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 717 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 718 txq->tail = 0; 719 txq->head = 0; 720 txq->xmit_bufs = 0; 721 } 722 723 static inline int 724 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 725 uint16_t qidx) 726 { 727 struct nicvf_txq *txq; 728 int ret; 729 730 assert(qidx < MAX_SND_QUEUES_PER_QS); 731 732 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 733 RTE_ETH_QUEUE_STATE_STARTED) 734 return 0; 735 736 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 737 txq->pool = NULL; 738 ret = nicvf_qset_sq_config(nic, qidx, txq); 739 if (ret) { 740 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 741 nic->vf_id, qidx, ret); 742 goto config_sq_error; 743 } 744 745 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 746 RTE_ETH_QUEUE_STATE_STARTED; 747 return ret; 748 749 config_sq_error: 750 nicvf_qset_sq_reclaim(nic, qidx); 751 return ret; 752 } 753 754 static inline int 755 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 756 uint16_t qidx) 757 { 758 struct nicvf_txq *txq; 759 int ret; 760 761 assert(qidx < MAX_SND_QUEUES_PER_QS); 762 763 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 764 RTE_ETH_QUEUE_STATE_STOPPED) 765 return 0; 766 767 ret = nicvf_qset_sq_reclaim(nic, qidx); 768 if (ret) 769 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 770 nic->vf_id, qidx, ret); 771 772 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 773 nicvf_tx_queue_release_mbufs(txq); 774 nicvf_tx_queue_reset(txq); 775 776 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 777 RTE_ETH_QUEUE_STATE_STOPPED; 778 return ret; 779 } 780 781 static inline int 782 nicvf_configure_cpi(struct rte_eth_dev *dev) 783 { 784 struct nicvf *nic = nicvf_pmd_priv(dev); 785 uint16_t qidx, qcnt; 786 int ret; 787 788 /* Count started rx queues */ 789 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 790 if (dev->data->rx_queue_state[qidx] == 791 RTE_ETH_QUEUE_STATE_STARTED) 792 qcnt++; 793 794 nic->cpi_alg = CPI_ALG_NONE; 795 ret = nicvf_mbox_config_cpi(nic, qcnt); 796 if (ret) 797 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 798 799 return ret; 800 } 801 802 static inline int 803 nicvf_configure_rss(struct rte_eth_dev *dev) 804 { 805 struct nicvf *nic = nicvf_pmd_priv(dev); 806 uint64_t rsshf; 807 int ret = -EINVAL; 808 809 rsshf = nicvf_rss_ethdev_to_nic(nic, 810 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 811 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 812 dev->data->dev_conf.rxmode.mq_mode, 813 dev->data->nb_rx_queues, 814 dev->data->dev_conf.lpbk_mode, rsshf); 815 816 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 817 ret = nicvf_rss_term(nic); 818 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 819 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 820 if (ret) 821 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 822 823 return ret; 824 } 825 826 static int 827 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 828 { 829 struct nicvf *nic = nicvf_pmd_priv(dev); 830 unsigned int idx, qmap_size; 831 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 832 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 833 834 if (nic->cpi_alg != CPI_ALG_NONE) 835 return -EINVAL; 836 837 /* Prepare queue map */ 838 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 839 if (dev->data->rx_queue_state[idx] == 840 RTE_ETH_QUEUE_STATE_STARTED) 841 qmap[qmap_size++] = idx; 842 } 843 844 /* Update default RSS RETA */ 845 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 846 default_reta[idx] = qmap[idx % qmap_size]; 847 848 return nicvf_rss_reta_update(nic, default_reta, 849 NIC_MAX_RSS_IDR_TBL_SIZE); 850 } 851 852 static void 853 nicvf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 854 { 855 struct nicvf_txq *txq = dev->data->tx_queues[qid]; 856 857 PMD_INIT_FUNC_TRACE(); 858 859 if (txq) { 860 if (txq->txbuffs != NULL) { 861 nicvf_tx_queue_release_mbufs(txq); 862 rte_free(txq->txbuffs); 863 txq->txbuffs = NULL; 864 } 865 rte_free(txq); 866 dev->data->tx_queues[qid] = NULL; 867 } 868 } 869 870 static void 871 nicvf_set_tx_function(struct rte_eth_dev *dev) 872 { 873 struct nicvf_txq *txq = NULL; 874 size_t i; 875 bool multiseg = false; 876 877 for (i = 0; i < dev->data->nb_tx_queues; i++) { 878 txq = dev->data->tx_queues[i]; 879 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) { 880 multiseg = true; 881 break; 882 } 883 } 884 885 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 886 if (multiseg) { 887 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 888 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 889 } else { 890 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 891 dev->tx_pkt_burst = nicvf_xmit_pkts; 892 } 893 894 if (!txq) 895 return; 896 897 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 898 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 899 else 900 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 901 } 902 903 static void 904 nicvf_set_rx_function(struct rte_eth_dev *dev) 905 { 906 struct nicvf *nic = nicvf_pmd_priv(dev); 907 908 const eth_rx_burst_t rx_burst_func[2][2][2] = { 909 /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */ 910 [0][0][0] = nicvf_recv_pkts_no_offload, 911 [0][0][1] = nicvf_recv_pkts_vlan_strip, 912 [0][1][0] = nicvf_recv_pkts_cksum, 913 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip, 914 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload, 915 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip, 916 [1][1][0] = nicvf_recv_pkts_multiseg_cksum, 917 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip, 918 }; 919 920 dev->rx_pkt_burst = 921 rx_burst_func[dev->data->scattered_rx] 922 [nic->offload_cksum][nic->vlan_strip]; 923 } 924 925 static int 926 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 927 uint16_t nb_desc, unsigned int socket_id, 928 const struct rte_eth_txconf *tx_conf) 929 { 930 uint16_t tx_free_thresh; 931 bool is_single_pool; 932 struct nicvf_txq *txq; 933 struct nicvf *nic = nicvf_pmd_priv(dev); 934 uint64_t offloads; 935 936 PMD_INIT_FUNC_TRACE(); 937 938 if (qidx >= MAX_SND_QUEUES_PER_QS) 939 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 940 941 qidx = qidx % MAX_SND_QUEUES_PER_QS; 942 943 /* Socket id check */ 944 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 945 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 946 socket_id, nic->node); 947 948 /* Tx deferred start is not supported */ 949 if (tx_conf->tx_deferred_start) { 950 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 951 return -EINVAL; 952 } 953 954 /* Roundup nb_desc to available qsize and validate max number of desc */ 955 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 956 if (nb_desc == 0) { 957 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 958 return -EINVAL; 959 } 960 961 /* Validate tx_free_thresh */ 962 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 963 tx_conf->tx_free_thresh : 964 NICVF_DEFAULT_TX_FREE_THRESH); 965 966 if (tx_free_thresh > (nb_desc) || 967 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 968 PMD_INIT_LOG(ERR, 969 "tx_free_thresh must be less than the number of TX " 970 "descriptors. (tx_free_thresh=%u port=%d " 971 "queue=%d)", (unsigned int)tx_free_thresh, 972 (int)dev->data->port_id, (int)qidx); 973 return -EINVAL; 974 } 975 976 /* Free memory prior to re-allocation if needed. */ 977 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 978 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 979 nicvf_netdev_qidx(nic, qidx)); 980 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 981 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 982 } 983 984 /* Allocating tx queue data structure */ 985 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 986 RTE_CACHE_LINE_SIZE, nic->node); 987 if (txq == NULL) { 988 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 989 nicvf_netdev_qidx(nic, qidx)); 990 return -ENOMEM; 991 } 992 993 txq->nic = nic; 994 txq->queue_id = qidx; 995 txq->tx_free_thresh = tx_free_thresh; 996 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 997 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 998 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 999 txq->offloads = offloads; 1000 1001 is_single_pool = !!(offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE); 1002 1003 /* Choose optimum free threshold value for multipool case */ 1004 if (!is_single_pool) { 1005 txq->tx_free_thresh = (uint16_t) 1006 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1007 NICVF_TX_FREE_MPOOL_THRESH : 1008 tx_conf->tx_free_thresh); 1009 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1010 } else { 1011 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1012 } 1013 1014 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1015 1016 /* Allocate software ring */ 1017 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1018 nb_desc * sizeof(struct rte_mbuf *), 1019 RTE_CACHE_LINE_SIZE, nic->node); 1020 1021 if (txq->txbuffs == NULL) { 1022 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1023 return -ENOMEM; 1024 } 1025 1026 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1027 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1028 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1029 return -ENOMEM; 1030 } 1031 1032 nicvf_tx_queue_reset(txq); 1033 1034 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1035 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1036 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1037 txq->phys, txq->offloads); 1038 1039 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1040 RTE_ETH_QUEUE_STATE_STOPPED; 1041 return 0; 1042 } 1043 1044 static inline void 1045 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1046 { 1047 uint32_t rxq_cnt; 1048 uint32_t nb_pkts, released_pkts = 0; 1049 uint32_t refill_cnt = 0; 1050 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1051 1052 if (dev->rx_pkt_burst == NULL) 1053 return; 1054 1055 while ((rxq_cnt = nicvf_dev_rx_queue_count(rxq))) { 1056 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1057 NICVF_MAX_RX_FREE_THRESH); 1058 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1059 while (nb_pkts) { 1060 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1061 released_pkts++; 1062 } 1063 } 1064 1065 1066 refill_cnt += nicvf_dev_rbdr_refill(dev, 1067 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1068 1069 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1070 released_pkts, refill_cnt); 1071 } 1072 1073 static void 1074 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1075 { 1076 rxq->head = 0; 1077 rxq->available_space = 0; 1078 rxq->recv_buffers = 0; 1079 } 1080 1081 static inline int 1082 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1083 uint16_t qidx) 1084 { 1085 struct nicvf_rxq *rxq; 1086 int ret; 1087 1088 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1089 1090 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1091 RTE_ETH_QUEUE_STATE_STARTED) 1092 return 0; 1093 1094 /* Update rbdr pointer to all rxq */ 1095 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1096 rxq->shared_rbdr = nic->rbdr; 1097 1098 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1099 if (ret) { 1100 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1101 nic->vf_id, qidx, ret); 1102 goto config_rq_error; 1103 } 1104 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1105 if (ret) { 1106 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1107 nic->vf_id, qidx, ret); 1108 goto config_cq_error; 1109 } 1110 1111 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1112 RTE_ETH_QUEUE_STATE_STARTED; 1113 return 0; 1114 1115 config_cq_error: 1116 nicvf_qset_cq_reclaim(nic, qidx); 1117 config_rq_error: 1118 nicvf_qset_rq_reclaim(nic, qidx); 1119 return ret; 1120 } 1121 1122 static inline int 1123 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1124 uint16_t qidx) 1125 { 1126 struct nicvf_rxq *rxq; 1127 int ret, other_error; 1128 1129 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1130 RTE_ETH_QUEUE_STATE_STOPPED) 1131 return 0; 1132 1133 ret = nicvf_qset_rq_reclaim(nic, qidx); 1134 if (ret) 1135 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1136 nic->vf_id, qidx, ret); 1137 1138 other_error = ret; 1139 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1140 nicvf_rx_queue_release_mbufs(dev, rxq); 1141 nicvf_rx_queue_reset(rxq); 1142 1143 ret = nicvf_qset_cq_reclaim(nic, qidx); 1144 if (ret) 1145 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1146 nic->vf_id, qidx, ret); 1147 1148 other_error |= ret; 1149 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1150 RTE_ETH_QUEUE_STATE_STOPPED; 1151 return other_error; 1152 } 1153 1154 static void 1155 nicvf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1156 { 1157 PMD_INIT_FUNC_TRACE(); 1158 1159 rte_free(dev->data->rx_queues[qid]); 1160 } 1161 1162 static int 1163 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1164 { 1165 struct nicvf *nic = nicvf_pmd_priv(dev); 1166 int ret; 1167 1168 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1169 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1170 1171 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1172 1173 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1174 if (ret) 1175 return ret; 1176 1177 ret = nicvf_configure_cpi(dev); 1178 if (ret) 1179 return ret; 1180 1181 return nicvf_configure_rss_reta(dev); 1182 } 1183 1184 static int 1185 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1186 { 1187 int ret; 1188 struct nicvf *nic = nicvf_pmd_priv(dev); 1189 1190 if (qidx >= MAX_SND_QUEUES_PER_QS) 1191 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1192 1193 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1194 1195 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1196 ret |= nicvf_configure_cpi(dev); 1197 ret |= nicvf_configure_rss_reta(dev); 1198 return ret; 1199 } 1200 1201 static int 1202 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1203 { 1204 struct nicvf *nic = nicvf_pmd_priv(dev); 1205 1206 if (qidx >= MAX_SND_QUEUES_PER_QS) 1207 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1208 1209 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1210 1211 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1212 } 1213 1214 static int 1215 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1216 { 1217 struct nicvf *nic = nicvf_pmd_priv(dev); 1218 1219 if (qidx >= MAX_SND_QUEUES_PER_QS) 1220 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1221 1222 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1223 1224 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1225 } 1226 1227 static inline void 1228 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1229 { 1230 uintptr_t p; 1231 struct rte_mbuf mb_def; 1232 struct nicvf *nic = rxq->nic; 1233 1234 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1235 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1236 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1237 offsetof(struct rte_mbuf, data_off) != 2); 1238 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1239 offsetof(struct rte_mbuf, data_off) != 4); 1240 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1241 offsetof(struct rte_mbuf, data_off) != 6); 1242 RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) - 1243 offsetof(struct nicvf_rxq, 1244 rxq_fastpath_data_start) > 128); 1245 mb_def.nb_segs = 1; 1246 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1247 mb_def.port = rxq->port_id; 1248 rte_mbuf_refcnt_set(&mb_def, 1); 1249 1250 /* Prevent compiler reordering: rearm_data covers previous fields */ 1251 rte_compiler_barrier(); 1252 p = (uintptr_t)&mb_def.rearm_data; 1253 rxq->mbuf_initializer.value = *(uint64_t *)p; 1254 } 1255 1256 static int 1257 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1258 uint16_t nb_desc, unsigned int socket_id, 1259 const struct rte_eth_rxconf *rx_conf, 1260 struct rte_mempool *mp) 1261 { 1262 uint16_t rx_free_thresh; 1263 struct nicvf_rxq *rxq; 1264 struct nicvf *nic = nicvf_pmd_priv(dev); 1265 uint64_t offloads; 1266 uint32_t buffsz; 1267 struct rte_pktmbuf_pool_private *mbp_priv; 1268 1269 PMD_INIT_FUNC_TRACE(); 1270 1271 /* First skip check */ 1272 mbp_priv = rte_mempool_get_priv(mp); 1273 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1274 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1275 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1276 return -EINVAL; 1277 } 1278 1279 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1280 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1281 1282 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1283 1284 /* Socket id check */ 1285 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1286 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1287 socket_id, nic->node); 1288 1289 /* Mempool memory must be contiguous, so must be one memory segment*/ 1290 if (mp->nb_mem_chunks != 1) { 1291 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1292 return -EINVAL; 1293 } 1294 1295 /* Mempool memory must be physically contiguous */ 1296 if (mp->flags & RTE_MEMPOOL_F_NO_IOVA_CONTIG) { 1297 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1298 return -EINVAL; 1299 } 1300 1301 /* Rx deferred start is not supported */ 1302 if (rx_conf->rx_deferred_start) { 1303 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1304 return -EINVAL; 1305 } 1306 1307 /* Roundup nb_desc to available qsize and validate max number of desc */ 1308 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1309 if (nb_desc == 0) { 1310 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1311 return -EINVAL; 1312 } 1313 1314 1315 /* Check rx_free_thresh upper bound */ 1316 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1317 rx_conf->rx_free_thresh : 1318 NICVF_DEFAULT_RX_FREE_THRESH); 1319 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1320 rx_free_thresh >= nb_desc * .75) { 1321 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1322 rx_free_thresh); 1323 return -EINVAL; 1324 } 1325 1326 /* Free memory prior to re-allocation if needed */ 1327 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1328 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1329 nicvf_netdev_qidx(nic, qidx)); 1330 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1331 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1332 } 1333 1334 /* Allocate rxq memory */ 1335 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1336 RTE_CACHE_LINE_SIZE, nic->node); 1337 if (rxq == NULL) { 1338 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1339 nicvf_netdev_qidx(nic, qidx)); 1340 return -ENOMEM; 1341 } 1342 1343 rxq->nic = nic; 1344 rxq->pool = mp; 1345 rxq->queue_id = qidx; 1346 rxq->port_id = dev->data->port_id; 1347 rxq->rx_free_thresh = rx_free_thresh; 1348 rxq->rx_drop_en = rx_conf->rx_drop_en; 1349 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1350 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1351 rxq->precharge_cnt = 0; 1352 1353 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1354 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1355 else 1356 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1357 1358 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1359 1360 nicvf_rxq_mbuf_setup(rxq); 1361 1362 /* Alloc completion queue */ 1363 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1364 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1365 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1366 return -ENOMEM; 1367 } 1368 1369 nicvf_rx_queue_reset(rxq); 1370 1371 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1372 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1373 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1374 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1375 rte_mempool_avail_count(mp), rxq->phys, offloads); 1376 1377 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1378 RTE_ETH_QUEUE_STATE_STOPPED; 1379 return 0; 1380 } 1381 1382 static int 1383 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1384 { 1385 struct nicvf *nic = nicvf_pmd_priv(dev); 1386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1387 1388 PMD_INIT_FUNC_TRACE(); 1389 1390 /* Autonegotiation may be disabled */ 1391 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 1392 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_100M | 1393 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 1394 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1395 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 1396 1397 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU; 1398 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN; 1399 dev_info->max_rx_queues = 1400 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1401 dev_info->max_tx_queues = 1402 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1403 dev_info->max_mac_addrs = 1; 1404 dev_info->max_vfs = pci_dev->max_vfs; 1405 1406 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1407 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1408 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1409 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1410 1411 dev_info->reta_size = nic->rss_info.rss_size; 1412 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1413 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1414 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1415 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1416 1417 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1418 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1419 .rx_drop_en = 0, 1420 }; 1421 1422 dev_info->default_txconf = (struct rte_eth_txconf) { 1423 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1424 .offloads = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | 1425 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1426 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1427 RTE_ETH_TX_OFFLOAD_TCP_CKSUM, 1428 }; 1429 1430 return 0; 1431 } 1432 1433 static nicvf_iova_addr_t 1434 rbdr_rte_mempool_get(void *dev, void *opaque) 1435 { 1436 uint16_t qidx; 1437 uintptr_t mbuf; 1438 struct nicvf_rxq *rxq; 1439 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1440 struct nicvf *nic = (struct nicvf *)opaque; 1441 uint16_t rx_start, rx_end; 1442 1443 /* Get queue ranges for this VF */ 1444 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1445 1446 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1447 rxq = eth_dev->data->rx_queues[qidx]; 1448 /* Maintain equal buffer count across all pools */ 1449 if (rxq->precharge_cnt >= rxq->qlen_mask) 1450 continue; 1451 rxq->precharge_cnt++; 1452 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1453 if (mbuf) 1454 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1455 } 1456 return 0; 1457 } 1458 1459 static int 1460 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1461 { 1462 int ret; 1463 uint16_t qidx, data_off; 1464 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1465 uint64_t mbuf_phys_off = 0; 1466 struct nicvf_rxq *rxq; 1467 struct rte_mbuf *mbuf; 1468 uint16_t rx_start, rx_end; 1469 uint16_t tx_start, tx_end; 1470 int mask; 1471 1472 PMD_INIT_FUNC_TRACE(); 1473 1474 /* Userspace process exited without proper shutdown in last run */ 1475 if (nicvf_qset_rbdr_active(nic, 0)) 1476 nicvf_vf_stop(dev, nic, false); 1477 1478 /* Get queue ranges for this VF */ 1479 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1480 1481 /* 1482 * Thunderx nicvf PMD can support more than one pool per port only when 1483 * 1) Data payload size is same across all the pools in given port 1484 * AND 1485 * 2) All mbuffs in the pools are from the same hugepage 1486 * AND 1487 * 3) Mbuff metadata size is same across all the pools in given port 1488 * 1489 * This is to support existing application that uses multiple pool/port. 1490 * But, the purpose of using multipool for QoS will not be addressed. 1491 * 1492 */ 1493 1494 /* Validate mempool attributes */ 1495 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1496 rxq = dev->data->rx_queues[qidx]; 1497 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1498 mbuf = rte_pktmbuf_alloc(rxq->pool); 1499 if (mbuf == NULL) { 1500 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1501 "pool=%s", 1502 nic->vf_id, qidx, rxq->pool->name); 1503 return -ENOMEM; 1504 } 1505 data_off = nicvf_mbuff_meta_length(mbuf); 1506 data_off += RTE_PKTMBUF_HEADROOM; 1507 rte_pktmbuf_free(mbuf); 1508 1509 if (data_off % RTE_CACHE_LINE_SIZE) { 1510 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1511 rxq->pool->name, data_off, 1512 data_off % RTE_CACHE_LINE_SIZE); 1513 return -EINVAL; 1514 } 1515 rxq->mbuf_phys_off -= data_off; 1516 rxq->mbuf_phys_off -= nic->skip_bytes; 1517 1518 if (mbuf_phys_off == 0) 1519 mbuf_phys_off = rxq->mbuf_phys_off; 1520 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1521 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1522 PRIx64, rxq->pool->name, nic->vf_id, 1523 mbuf_phys_off); 1524 return -EINVAL; 1525 } 1526 } 1527 1528 /* Check the level of buffers in the pool */ 1529 total_rxq_desc = 0; 1530 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1531 rxq = dev->data->rx_queues[qidx]; 1532 /* Count total numbers of rxq descs */ 1533 total_rxq_desc += rxq->qlen_mask + 1; 1534 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1535 exp_buffs *= dev->data->nb_rx_queues; 1536 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1537 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1538 rxq->pool->name, 1539 rte_mempool_avail_count(rxq->pool), 1540 exp_buffs); 1541 return -ENOENT; 1542 } 1543 } 1544 1545 /* Check RBDR desc overflow */ 1546 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1547 if (ret == 0) { 1548 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1549 "VF%d", nic->vf_id); 1550 return -ENOMEM; 1551 } 1552 1553 /* Enable qset */ 1554 ret = nicvf_qset_config(nic); 1555 if (ret) { 1556 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1557 nic->vf_id); 1558 return ret; 1559 } 1560 1561 /* Allocate RBDR and RBDR ring desc */ 1562 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1563 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1564 if (ret) { 1565 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1566 "VF%d", nic->vf_id); 1567 goto qset_reclaim; 1568 } 1569 1570 /* Enable and configure RBDR registers */ 1571 ret = nicvf_qset_rbdr_config(nic, 0); 1572 if (ret) { 1573 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1574 nic->vf_id); 1575 goto qset_rbdr_free; 1576 } 1577 1578 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1579 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1580 total_rxq_desc); 1581 if (ret) { 1582 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1583 nic->vf_id); 1584 goto qset_rbdr_reclaim; 1585 } 1586 1587 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1588 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1589 1590 /* Configure VLAN Strip */ 1591 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 1592 RTE_ETH_VLAN_EXTEND_MASK; 1593 ret = nicvf_vlan_offload_config(dev, mask); 1594 1595 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1596 * to the 64bit memory address. 1597 * The alignment creates a hole in mbuf(between the end of headroom and 1598 * packet data start). The new revision of the HW provides an option to 1599 * disable the L3 alignment feature and make mbuf layout looks 1600 * more like other NICs. For better application compatibility, disabling 1601 * l3 alignment feature on the hardware revisions it supports 1602 */ 1603 nicvf_apad_config(nic, false); 1604 1605 /* Get queue ranges for this VF */ 1606 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1607 1608 /* Configure TX queues */ 1609 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1610 ret = nicvf_vf_start_tx_queue(dev, nic, 1611 qidx % MAX_SND_QUEUES_PER_QS); 1612 if (ret) 1613 goto start_txq_error; 1614 } 1615 1616 /* Configure RX queues */ 1617 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1618 ret = nicvf_vf_start_rx_queue(dev, nic, 1619 qidx % MAX_RCV_QUEUES_PER_QS); 1620 if (ret) 1621 goto start_rxq_error; 1622 } 1623 1624 if (!nic->sqs_mode) { 1625 /* Configure CPI algorithm */ 1626 ret = nicvf_configure_cpi(dev); 1627 if (ret) 1628 goto start_txq_error; 1629 1630 ret = nicvf_mbox_get_rss_size(nic); 1631 if (ret) { 1632 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1633 goto qset_rss_error; 1634 } 1635 1636 /* Configure RSS */ 1637 ret = nicvf_configure_rss(dev); 1638 if (ret) 1639 goto qset_rss_error; 1640 } 1641 1642 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1643 nicvf_mbox_cfg_done(nic); 1644 return 0; 1645 1646 qset_rss_error: 1647 nicvf_rss_term(nic); 1648 start_rxq_error: 1649 for (qidx = rx_start; qidx <= rx_end; qidx++) 1650 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1651 start_txq_error: 1652 for (qidx = tx_start; qidx <= tx_end; qidx++) 1653 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1654 qset_rbdr_reclaim: 1655 nicvf_qset_rbdr_reclaim(nic, 0); 1656 nicvf_rbdr_release_mbufs(dev, nic); 1657 qset_rbdr_free: 1658 if (nic->rbdr) { 1659 rte_free(nic->rbdr); 1660 nic->rbdr = NULL; 1661 } 1662 qset_reclaim: 1663 nicvf_qset_reclaim(nic); 1664 return ret; 1665 } 1666 1667 static int 1668 nicvf_dev_start(struct rte_eth_dev *dev) 1669 { 1670 uint16_t qidx; 1671 int ret; 1672 size_t i; 1673 struct nicvf *nic = nicvf_pmd_priv(dev); 1674 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1675 uint16_t mtu; 1676 uint32_t buffsz = 0, rbdrsz = 0; 1677 struct rte_pktmbuf_pool_private *mbp_priv; 1678 struct nicvf_rxq *rxq; 1679 1680 PMD_INIT_FUNC_TRACE(); 1681 1682 /* This function must be called for a primary device */ 1683 assert_primary(nic); 1684 1685 /* Validate RBDR buff size */ 1686 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1687 rxq = dev->data->rx_queues[qidx]; 1688 mbp_priv = rte_mempool_get_priv(rxq->pool); 1689 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1690 if (buffsz % 128) { 1691 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1692 return -EINVAL; 1693 } 1694 if (rbdrsz == 0) 1695 rbdrsz = buffsz; 1696 if (rbdrsz != buffsz) { 1697 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1698 qidx, rbdrsz, buffsz); 1699 return -EINVAL; 1700 } 1701 } 1702 1703 /* Configure loopback */ 1704 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1705 if (ret) { 1706 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1707 return ret; 1708 } 1709 1710 /* Reset all statistics counters attached to this port */ 1711 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1712 if (ret) { 1713 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1714 return ret; 1715 } 1716 1717 /* Setup scatter mode if needed by jumbo */ 1718 if (dev->data->mtu + (uint32_t)NIC_HW_L2_OVERHEAD + 2 * VLAN_TAG_SIZE > buffsz) 1719 dev->data->scattered_rx = 1; 1720 if ((rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) != 0) 1721 dev->data->scattered_rx = 1; 1722 1723 /* Setup MTU */ 1724 mtu = dev->data->mtu; 1725 1726 if (nicvf_dev_set_mtu(dev, mtu)) { 1727 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1728 return -EBUSY; 1729 } 1730 1731 ret = nicvf_vf_start(dev, nic, rbdrsz); 1732 if (ret != 0) 1733 return ret; 1734 1735 for (i = 0; i < nic->sqs_count; i++) { 1736 assert(nic->snicvf[i]); 1737 1738 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1739 if (ret != 0) 1740 return ret; 1741 } 1742 1743 /* Configure callbacks based on offloads */ 1744 nicvf_set_tx_function(dev); 1745 nicvf_set_rx_function(dev); 1746 1747 return 0; 1748 } 1749 1750 static void 1751 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1752 { 1753 size_t i; 1754 int ret; 1755 struct nicvf *nic = nicvf_pmd_priv(dev); 1756 1757 PMD_INIT_FUNC_TRACE(); 1758 dev->data->dev_started = 0; 1759 1760 /* Teardown secondary vf first */ 1761 for (i = 0; i < nic->sqs_count; i++) { 1762 if (!nic->snicvf[i]) 1763 continue; 1764 1765 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1766 } 1767 1768 /* Stop the primary VF now */ 1769 nicvf_vf_stop(dev, nic, cleanup); 1770 1771 /* Disable loopback */ 1772 ret = nicvf_loopback_config(nic, 0); 1773 if (ret) 1774 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1775 1776 /* Reclaim CPI configuration */ 1777 ret = nicvf_mbox_config_cpi(nic, 0); 1778 if (ret) 1779 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1780 } 1781 1782 static int 1783 nicvf_dev_stop(struct rte_eth_dev *dev) 1784 { 1785 PMD_INIT_FUNC_TRACE(); 1786 1787 nicvf_dev_stop_cleanup(dev, false); 1788 1789 return 0; 1790 } 1791 1792 static void 1793 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1794 { 1795 int ret; 1796 uint16_t qidx; 1797 uint16_t tx_start, tx_end; 1798 uint16_t rx_start, rx_end; 1799 1800 PMD_INIT_FUNC_TRACE(); 1801 1802 if (cleanup) { 1803 /* Let PF make the BGX's RX and TX switches to OFF position */ 1804 nicvf_mbox_shutdown(nic); 1805 } 1806 1807 /* Disable VLAN Strip */ 1808 nicvf_vlan_hw_strip(nic, 0); 1809 1810 /* Get queue ranges for this VF */ 1811 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1812 1813 for (qidx = tx_start; qidx <= tx_end; qidx++) 1814 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1815 1816 /* Get queue ranges for this VF */ 1817 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1818 1819 /* Reclaim rq */ 1820 for (qidx = rx_start; qidx <= rx_end; qidx++) 1821 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1822 1823 /* Reclaim RBDR */ 1824 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1825 if (ret) 1826 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1827 1828 /* Move all charged buffers in RBDR back to pool */ 1829 if (nic->rbdr != NULL) 1830 nicvf_rbdr_release_mbufs(dev, nic); 1831 1832 /* Disable qset */ 1833 ret = nicvf_qset_reclaim(nic); 1834 if (ret) 1835 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1836 1837 /* Disable all interrupts */ 1838 nicvf_disable_all_interrupts(nic); 1839 1840 /* Free RBDR SW structure */ 1841 if (nic->rbdr) { 1842 rte_free(nic->rbdr); 1843 nic->rbdr = NULL; 1844 } 1845 } 1846 1847 static int 1848 nicvf_dev_close(struct rte_eth_dev *dev) 1849 { 1850 struct nicvf *nic = nicvf_pmd_priv(dev); 1851 1852 PMD_INIT_FUNC_TRACE(); 1853 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1854 return 0; 1855 1856 nicvf_dev_stop_cleanup(dev, true); 1857 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1858 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic); 1859 1860 rte_intr_instance_free(nic->intr_handle); 1861 1862 return 0; 1863 } 1864 1865 static int 1866 nicvf_request_sqs(struct nicvf *nic) 1867 { 1868 size_t i; 1869 1870 assert_primary(nic); 1871 assert(nic->sqs_count > 0); 1872 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1873 1874 /* Set no of Rx/Tx queues in each of the SQsets */ 1875 for (i = 0; i < nic->sqs_count; i++) { 1876 if (nicvf_svf_empty()) 1877 rte_panic("Cannot assign sufficient number of " 1878 "secondary queues to primary VF%" PRIu8 "\n", 1879 nic->vf_id); 1880 1881 nic->snicvf[i] = nicvf_svf_pop(); 1882 nic->snicvf[i]->sqs_id = i; 1883 } 1884 1885 return nicvf_mbox_request_sqs(nic); 1886 } 1887 1888 static int 1889 nicvf_dev_configure(struct rte_eth_dev *dev) 1890 { 1891 struct rte_eth_dev_data *data = dev->data; 1892 struct rte_eth_conf *conf = &data->dev_conf; 1893 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1894 struct rte_eth_txmode *txmode = &conf->txmode; 1895 struct nicvf *nic = nicvf_pmd_priv(dev); 1896 uint8_t cqcount; 1897 1898 PMD_INIT_FUNC_TRACE(); 1899 1900 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1901 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1902 1903 if (!rte_eal_has_hugepages()) { 1904 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1905 return -EINVAL; 1906 } 1907 1908 if (txmode->mq_mode) { 1909 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1910 return -EINVAL; 1911 } 1912 1913 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE && 1914 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) { 1915 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1916 return -EINVAL; 1917 } 1918 1919 if (rxmode->split_hdr_size) { 1920 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1921 return -EINVAL; 1922 } 1923 1924 if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 1925 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1926 return -EINVAL; 1927 } 1928 1929 if (conf->dcb_capability_en) { 1930 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1931 return -EINVAL; 1932 } 1933 1934 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1935 PMD_INIT_LOG(INFO, "Flow director not supported"); 1936 return -EINVAL; 1937 } 1938 1939 assert_primary(nic); 1940 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1941 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1942 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1943 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1944 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1945 } else { 1946 nic->sqs_count = 0; 1947 } 1948 1949 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1950 1951 if (nic->sqs_count > 0) { 1952 if (nicvf_request_sqs(nic)) { 1953 rte_panic("Cannot assign sufficient number of " 1954 "secondary queues to PORT%d VF%" PRIu8 "\n", 1955 dev->data->port_id, nic->vf_id); 1956 } 1957 } 1958 1959 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM) 1960 nic->offload_cksum = 1; 1961 1962 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1963 dev->data->port_id, nicvf_hw_cap(nic)); 1964 1965 return 0; 1966 } 1967 1968 static int 1969 nicvf_dev_set_link_up(struct rte_eth_dev *dev) 1970 { 1971 struct nicvf *nic = nicvf_pmd_priv(dev); 1972 int rc, i; 1973 1974 rc = nicvf_mbox_set_link_up_down(nic, true); 1975 if (rc) 1976 goto done; 1977 1978 /* Start tx queues */ 1979 for (i = 0; i < dev->data->nb_tx_queues; i++) 1980 nicvf_dev_tx_queue_start(dev, i); 1981 1982 done: 1983 return rc; 1984 } 1985 1986 static int 1987 nicvf_dev_set_link_down(struct rte_eth_dev *dev) 1988 { 1989 struct nicvf *nic = nicvf_pmd_priv(dev); 1990 int i; 1991 1992 /* Stop tx queues */ 1993 for (i = 0; i < dev->data->nb_tx_queues; i++) 1994 nicvf_dev_tx_queue_stop(dev, i); 1995 1996 return nicvf_mbox_set_link_up_down(nic, false); 1997 } 1998 1999 /* Initialize and register driver with DPDK Application */ 2000 static const struct eth_dev_ops nicvf_eth_dev_ops = { 2001 .dev_configure = nicvf_dev_configure, 2002 .dev_start = nicvf_dev_start, 2003 .dev_stop = nicvf_dev_stop, 2004 .link_update = nicvf_dev_link_update, 2005 .dev_close = nicvf_dev_close, 2006 .stats_get = nicvf_dev_stats_get, 2007 .stats_reset = nicvf_dev_stats_reset, 2008 .promiscuous_enable = nicvf_dev_promisc_enable, 2009 .dev_infos_get = nicvf_dev_info_get, 2010 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 2011 .mtu_set = nicvf_dev_set_mtu, 2012 .vlan_offload_set = nicvf_vlan_offload_set, 2013 .reta_update = nicvf_dev_reta_update, 2014 .reta_query = nicvf_dev_reta_query, 2015 .rss_hash_update = nicvf_dev_rss_hash_update, 2016 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2017 .rx_queue_start = nicvf_dev_rx_queue_start, 2018 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2019 .tx_queue_start = nicvf_dev_tx_queue_start, 2020 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2021 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2022 .rx_queue_release = nicvf_dev_rx_queue_release, 2023 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2024 .tx_queue_release = nicvf_dev_tx_queue_release, 2025 .dev_set_link_up = nicvf_dev_set_link_up, 2026 .dev_set_link_down = nicvf_dev_set_link_down, 2027 .get_reg = nicvf_dev_get_regs, 2028 }; 2029 2030 static int 2031 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2032 { 2033 struct rte_eth_rxmode *rxmode; 2034 struct nicvf *nic = nicvf_pmd_priv(dev); 2035 rxmode = &dev->data->dev_conf.rxmode; 2036 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2037 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2038 nicvf_vlan_hw_strip(nic, true); 2039 else 2040 nicvf_vlan_hw_strip(nic, false); 2041 } 2042 2043 return 0; 2044 } 2045 2046 static int 2047 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2048 { 2049 nicvf_vlan_offload_config(dev, mask); 2050 2051 return 0; 2052 } 2053 2054 static inline int 2055 nicvf_set_first_skip(struct rte_eth_dev *dev) 2056 { 2057 int bytes_to_skip = 0; 2058 int ret = 0; 2059 unsigned int i; 2060 struct rte_kvargs *kvlist; 2061 static const char *const skip[] = { 2062 SKIP_DATA_BYTES, 2063 NULL}; 2064 struct nicvf *nic = nicvf_pmd_priv(dev); 2065 2066 if (!dev->device->devargs) { 2067 nicvf_first_skip_config(nic, 0); 2068 return ret; 2069 } 2070 2071 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2072 if (!kvlist) 2073 return -EINVAL; 2074 2075 if (kvlist->count == 0) 2076 goto exit; 2077 2078 for (i = 0; i != kvlist->count; ++i) { 2079 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2080 2081 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2082 bytes_to_skip = atoi(pair->value); 2083 } 2084 2085 /*128 bytes amounts to one cache line*/ 2086 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2087 if (!(bytes_to_skip % 8)) { 2088 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2089 nic->skip_bytes = bytes_to_skip; 2090 goto kvlist_free; 2091 } else { 2092 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2093 ret = -EINVAL; 2094 goto exit; 2095 } 2096 } else { 2097 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2098 ret = -EINVAL; 2099 goto exit; 2100 } 2101 exit: 2102 nicvf_first_skip_config(nic, 0); 2103 kvlist_free: 2104 rte_kvargs_free(kvlist); 2105 return ret; 2106 } 2107 static int 2108 nicvf_eth_dev_uninit(struct rte_eth_dev *dev) 2109 { 2110 PMD_INIT_FUNC_TRACE(); 2111 nicvf_dev_close(dev); 2112 return 0; 2113 } 2114 static int 2115 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2116 { 2117 int ret; 2118 struct rte_pci_device *pci_dev; 2119 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2120 2121 PMD_INIT_FUNC_TRACE(); 2122 2123 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2124 eth_dev->rx_queue_count = nicvf_dev_rx_queue_count; 2125 2126 /* For secondary processes, the primary has done all the work */ 2127 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2128 if (nic) { 2129 /* Setup callbacks for secondary process */ 2130 nicvf_set_tx_function(eth_dev); 2131 nicvf_set_rx_function(eth_dev); 2132 return 0; 2133 } else { 2134 /* If nic == NULL than it is secondary function 2135 * so ethdev need to be released by caller */ 2136 return ENOTSUP; 2137 } 2138 } 2139 2140 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2141 rte_eth_copy_pci_info(eth_dev, pci_dev); 2142 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2143 2144 nic->device_id = pci_dev->id.device_id; 2145 nic->vendor_id = pci_dev->id.vendor_id; 2146 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2147 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2148 2149 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2150 pci_dev->id.vendor_id, pci_dev->id.device_id, 2151 pci_dev->addr.domain, pci_dev->addr.bus, 2152 pci_dev->addr.devid, pci_dev->addr.function); 2153 2154 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2155 if (!nic->reg_base) { 2156 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2157 ret = -ENODEV; 2158 goto fail; 2159 } 2160 2161 /* Allocate interrupt instance */ 2162 nic->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2163 if (nic->intr_handle == NULL) { 2164 PMD_INIT_LOG(ERR, "Failed to allocate intr handle"); 2165 ret = -ENODEV; 2166 goto fail; 2167 } 2168 2169 nicvf_disable_all_interrupts(nic); 2170 2171 /* To read mbox messages */ 2172 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2173 if (ret) { 2174 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2175 goto fail; 2176 } 2177 2178 /* To poll link status change*/ 2179 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2180 if (ret) { 2181 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2182 goto fail; 2183 } 2184 2185 ret = nicvf_mbox_check_pf_ready(nic); 2186 if (ret) { 2187 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2188 goto alarm_fail; 2189 } else { 2190 PMD_INIT_LOG(INFO, 2191 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2192 nic->node, nic->vf_id, 2193 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2194 nic->sqs_mode ? "true" : "false", 2195 nic->loopback_supported ? "true" : "false" 2196 ); 2197 } 2198 2199 /* To make sure RX DMAC register is set to default value (0x3) */ 2200 nicvf_mbox_reset_xcast(nic); 2201 2202 ret = nicvf_base_init(nic); 2203 if (ret) { 2204 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2205 goto malloc_fail; 2206 } 2207 2208 if (nic->sqs_mode) { 2209 /* Push nic to stack of secondary vfs */ 2210 nicvf_svf_push(nic); 2211 2212 /* Steal nic pointer from the device for further reuse */ 2213 eth_dev->data->dev_private = NULL; 2214 2215 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2216 2217 /* Detach port by returning positive error number */ 2218 return ENOTSUP; 2219 } 2220 2221 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2222 RTE_ETHER_ADDR_LEN, 0); 2223 if (eth_dev->data->mac_addrs == NULL) { 2224 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2225 ret = -ENOMEM; 2226 goto alarm_fail; 2227 } 2228 if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr)) 2229 rte_eth_random_addr(&nic->mac_addr[0]); 2230 2231 rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr, 2232 ð_dev->data->mac_addrs[0]); 2233 2234 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2235 if (ret) { 2236 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2237 goto malloc_fail; 2238 } 2239 2240 ret = nicvf_set_first_skip(eth_dev); 2241 if (ret) { 2242 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2243 goto malloc_fail; 2244 } 2245 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=" RTE_ETHER_ADDR_PRT_FMT, 2246 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2247 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2248 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2249 2250 return 0; 2251 2252 malloc_fail: 2253 rte_free(eth_dev->data->mac_addrs); 2254 eth_dev->data->mac_addrs = NULL; 2255 alarm_fail: 2256 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2257 fail: 2258 return ret; 2259 } 2260 2261 static const struct rte_pci_id pci_id_nicvf_map[] = { 2262 { 2263 .class_id = RTE_CLASS_ANY_ID, 2264 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2265 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2266 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2267 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2268 }, 2269 { 2270 .class_id = RTE_CLASS_ANY_ID, 2271 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2272 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2273 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2274 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2275 }, 2276 { 2277 .class_id = RTE_CLASS_ANY_ID, 2278 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2279 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2280 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2281 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2282 }, 2283 { 2284 .class_id = RTE_CLASS_ANY_ID, 2285 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2286 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2287 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2288 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2289 }, 2290 { 2291 .vendor_id = 0, 2292 }, 2293 }; 2294 2295 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2296 struct rte_pci_device *pci_dev) 2297 { 2298 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2299 nicvf_eth_dev_init); 2300 } 2301 2302 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2303 { 2304 return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit); 2305 } 2306 2307 static struct rte_pci_driver rte_nicvf_pmd = { 2308 .id_table = pci_id_nicvf_map, 2309 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2310 RTE_PCI_DRV_INTR_LSC, 2311 .probe = nicvf_eth_pci_probe, 2312 .remove = nicvf_eth_pci_remove, 2313 }; 2314 2315 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2316 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2317 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2318 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2319