1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <dev_driver.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <ethdev_driver.h> 27 #include <ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <bus_pci_driver.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 static int nicvf_dev_stop(struct rte_eth_dev *dev); 48 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 49 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 50 bool cleanup); 51 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 52 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 53 54 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_mbox, mbox, NOTICE); 55 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_init, init, NOTICE); 56 RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); 57 58 #define NICVF_QLM_MODE_SGMII 7 59 #define NICVF_QLM_MODE_XFI 12 60 61 enum nicvf_link_speed { 62 NICVF_LINK_SPEED_SGMII, 63 NICVF_LINK_SPEED_XAUI, 64 NICVF_LINK_SPEED_RXAUI, 65 NICVF_LINK_SPEED_10G_R, 66 NICVF_LINK_SPEED_40G_R, 67 NICVF_LINK_SPEED_RESERVE1, 68 NICVF_LINK_SPEED_QSGMII, 69 NICVF_LINK_SPEED_RESERVE2, 70 NICVF_LINK_SPEED_UNKNOWN = 255 71 }; 72 73 static inline uint32_t 74 nicvf_parse_link_speeds(uint32_t link_speeds) 75 { 76 uint32_t link_speed = NICVF_LINK_SPEED_UNKNOWN; 77 78 if (link_speeds & RTE_ETH_LINK_SPEED_40G) 79 link_speed = NICVF_LINK_SPEED_40G_R; 80 81 if (link_speeds & RTE_ETH_LINK_SPEED_10G) { 82 link_speed = NICVF_LINK_SPEED_XAUI; 83 link_speed |= NICVF_LINK_SPEED_RXAUI; 84 link_speed |= NICVF_LINK_SPEED_10G_R; 85 } 86 87 if (link_speeds & RTE_ETH_LINK_SPEED_5G) 88 link_speed = NICVF_LINK_SPEED_QSGMII; 89 90 if (link_speeds & RTE_ETH_LINK_SPEED_1G) 91 link_speed = NICVF_LINK_SPEED_SGMII; 92 93 return link_speed; 94 } 95 96 static inline uint8_t 97 nicvf_parse_eth_link_duplex(uint32_t link_speeds) 98 { 99 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || 100 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) 101 return RTE_ETH_LINK_HALF_DUPLEX; 102 else 103 return RTE_ETH_LINK_FULL_DUPLEX; 104 } 105 106 static int 107 nicvf_apply_link_speed(struct rte_eth_dev *dev) 108 { 109 struct nicvf *nic = nicvf_pmd_priv(dev); 110 struct rte_eth_conf *conf = &dev->data->dev_conf; 111 struct change_link_mode cfg; 112 if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) 113 /* TODO: Handle this case */ 114 return 0; 115 116 cfg.speed = nicvf_parse_link_speeds(conf->link_speeds); 117 cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; 118 cfg.duplex = nicvf_parse_eth_link_duplex(conf->link_speeds); 119 cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? 120 NICVF_QLM_MODE_SGMII : 121 (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? 122 NICVF_QLM_MODE_XFI : 0); 123 124 if (cfg.speed != NICVF_LINK_SPEED_UNKNOWN && 125 (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { 126 nic->speed = cfg.speed; 127 nic->duplex = cfg.duplex; 128 return nicvf_mbox_change_mode(nic, &cfg); 129 } else { 130 return 0; 131 } 132 } 133 134 static void 135 nicvf_link_status_update(struct nicvf *nic, 136 struct rte_eth_link *link) 137 { 138 memset(link, 0, sizeof(*link)); 139 140 link->link_status = nic->link_up ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; 141 142 if (nic->duplex == NICVF_HALF_DUPLEX) 143 link->link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 144 else if (nic->duplex == NICVF_FULL_DUPLEX) 145 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 146 link->link_speed = nic->speed; 147 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 148 } 149 150 /*Poll for link status change by sending NIC_MBOX_MSG_BGX_LINK_CHANGE msg 151 * periodically to PF. 152 */ 153 static void 154 nicvf_interrupt(void *arg) 155 { 156 struct rte_eth_dev *dev = arg; 157 struct nicvf *nic = nicvf_pmd_priv(dev); 158 struct rte_eth_link link; 159 160 rte_eth_linkstatus_get(dev, &link); 161 162 nicvf_mbox_link_change(nic); 163 if (nic->link_up != link.link_status) { 164 if (dev->data->dev_conf.intr_conf.lsc) { 165 nicvf_link_status_update(nic, &link); 166 rte_eth_linkstatus_set(dev, &link); 167 168 rte_eth_dev_callback_process(dev, 169 RTE_ETH_EVENT_INTR_LSC, 170 NULL); 171 } 172 } 173 174 rte_eal_alarm_set(NICVF_INTR_LINK_POLL_INTERVAL_MS * 1000, 175 nicvf_interrupt, dev); 176 } 177 178 static void 179 nicvf_vf_interrupt(void *arg) 180 { 181 struct nicvf *nic = arg; 182 183 nicvf_reg_poll_interrupts(nic); 184 185 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 186 nicvf_vf_interrupt, nic); 187 } 188 189 static int 190 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 191 { 192 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 193 } 194 195 static int 196 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 197 { 198 return rte_eal_alarm_cancel(fn, arg); 199 } 200 201 /* 202 * Return 0 means link status changed, -1 means not changed 203 */ 204 static int 205 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 206 { 207 #define CHECK_INTERVAL 100 /* 100ms */ 208 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 209 struct rte_eth_link link; 210 struct nicvf *nic = nicvf_pmd_priv(dev); 211 int i; 212 213 PMD_INIT_FUNC_TRACE(); 214 215 if (wait_to_complete) { 216 /* rte_eth_link_get() might need to wait up to 9 seconds */ 217 for (i = 0; i < MAX_CHECK_TIME; i++) { 218 nicvf_link_status_update(nic, &link); 219 if (link.link_status == RTE_ETH_LINK_UP) 220 break; 221 rte_delay_ms(CHECK_INTERVAL); 222 } 223 } else { 224 nicvf_link_status_update(nic, &link); 225 } 226 227 return rte_eth_linkstatus_set(dev, &link); 228 } 229 230 static int 231 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 232 { 233 struct nicvf *nic = nicvf_pmd_priv(dev); 234 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 235 size_t i; 236 237 PMD_INIT_FUNC_TRACE(); 238 239 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 240 241 /* 242 * Refuse mtu that requires the support of scattered packets 243 * when this feature has not been enabled before. 244 */ 245 if (dev->data->dev_started && !dev->data->scattered_rx && 246 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 247 return -EINVAL; 248 249 /* check <seg size> * <max_seg> >= max_frame */ 250 if (dev->data->scattered_rx && 251 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 252 return -EINVAL; 253 254 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 255 return -EINVAL; 256 257 nic->mtu = mtu; 258 259 for (i = 0; i < nic->sqs_count; i++) 260 nic->snicvf[i]->mtu = mtu; 261 262 return 0; 263 } 264 265 static int 266 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 267 { 268 uint64_t *data = regs->data; 269 struct nicvf *nic = nicvf_pmd_priv(dev); 270 271 if (data == NULL) { 272 regs->length = nicvf_reg_get_count(); 273 regs->width = THUNDERX_REG_BYTES; 274 return 0; 275 } 276 277 /* Support only full register dump */ 278 if ((regs->length == 0) || 279 (regs->length == (uint32_t)nicvf_reg_get_count())) { 280 regs->version = nic->vendor_id << 16 | nic->device_id; 281 nicvf_reg_dump(nic, data); 282 return 0; 283 } 284 return -ENOTSUP; 285 } 286 287 static int 288 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 289 { 290 uint16_t qidx; 291 struct nicvf_hw_rx_qstats rx_qstats; 292 struct nicvf_hw_tx_qstats tx_qstats; 293 struct nicvf_hw_stats port_stats; 294 struct nicvf *nic = nicvf_pmd_priv(dev); 295 uint16_t rx_start, rx_end; 296 uint16_t tx_start, tx_end; 297 size_t i; 298 299 /* RX queue indices for the first VF */ 300 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 301 302 /* Reading per RX ring stats */ 303 for (qidx = rx_start; qidx <= rx_end; qidx++) { 304 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 305 break; 306 307 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 308 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 309 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 310 } 311 312 /* TX queue indices for the first VF */ 313 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 314 315 /* Reading per TX ring stats */ 316 for (qidx = tx_start; qidx <= tx_end; qidx++) { 317 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 318 break; 319 320 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 321 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 322 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 323 } 324 325 for (i = 0; i < nic->sqs_count; i++) { 326 struct nicvf *snic = nic->snicvf[i]; 327 328 if (snic == NULL) 329 break; 330 331 /* RX queue indices for a secondary VF */ 332 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 333 334 /* Reading per RX ring stats */ 335 for (qidx = rx_start; qidx <= rx_end; qidx++) { 336 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 337 break; 338 339 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 340 qidx % MAX_RCV_QUEUES_PER_QS); 341 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 342 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 343 } 344 345 /* TX queue indices for a secondary VF */ 346 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 347 /* Reading per TX ring stats */ 348 for (qidx = tx_start; qidx <= tx_end; qidx++) { 349 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 350 break; 351 352 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 353 qidx % MAX_SND_QUEUES_PER_QS); 354 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 355 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 356 } 357 } 358 359 nicvf_hw_get_stats(nic, &port_stats); 360 stats->ibytes = port_stats.rx_bytes; 361 stats->ipackets = port_stats.rx_ucast_frames; 362 stats->ipackets += port_stats.rx_bcast_frames; 363 stats->ipackets += port_stats.rx_mcast_frames; 364 stats->ierrors = port_stats.rx_l2_errors; 365 stats->imissed = port_stats.rx_drop_red; 366 stats->imissed += port_stats.rx_drop_overrun; 367 stats->imissed += port_stats.rx_drop_bcast; 368 stats->imissed += port_stats.rx_drop_mcast; 369 stats->imissed += port_stats.rx_drop_l3_bcast; 370 stats->imissed += port_stats.rx_drop_l3_mcast; 371 372 stats->obytes = port_stats.tx_bytes_ok; 373 stats->opackets = port_stats.tx_ucast_frames_ok; 374 stats->opackets += port_stats.tx_bcast_frames_ok; 375 stats->opackets += port_stats.tx_mcast_frames_ok; 376 stats->oerrors = port_stats.tx_drops; 377 378 return 0; 379 } 380 381 static const uint32_t * 382 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 383 { 384 size_t copied; 385 static uint32_t ptypes[32]; 386 struct nicvf *nic = nicvf_pmd_priv(dev); 387 static const uint32_t ptypes_common[] = { 388 RTE_PTYPE_L3_IPV4, 389 RTE_PTYPE_L3_IPV4_EXT, 390 RTE_PTYPE_L3_IPV6, 391 RTE_PTYPE_L3_IPV6_EXT, 392 RTE_PTYPE_L4_TCP, 393 RTE_PTYPE_L4_UDP, 394 RTE_PTYPE_L4_FRAG, 395 }; 396 static const uint32_t ptypes_tunnel[] = { 397 RTE_PTYPE_TUNNEL_GRE, 398 RTE_PTYPE_TUNNEL_GENEVE, 399 RTE_PTYPE_TUNNEL_VXLAN, 400 RTE_PTYPE_TUNNEL_NVGRE, 401 }; 402 403 copied = sizeof(ptypes_common); 404 memcpy(ptypes, ptypes_common, copied); 405 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 406 memcpy((char *)ptypes + copied, ptypes_tunnel, 407 sizeof(ptypes_tunnel)); 408 copied += sizeof(ptypes_tunnel); 409 } 410 411 412 /* All Ptypes are supported in all Rx functions. */ 413 *no_of_elements = copied / sizeof(ptypes[0]); 414 return ptypes; 415 } 416 417 static int 418 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 419 { 420 int i; 421 uint16_t rxqs = 0, txqs = 0; 422 struct nicvf *nic = nicvf_pmd_priv(dev); 423 uint16_t rx_start, rx_end; 424 uint16_t tx_start, tx_end; 425 int ret; 426 427 /* Reset all primary nic counters */ 428 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 429 for (i = rx_start; i <= rx_end; i++) 430 rxqs |= (0x3 << (i * 2)); 431 432 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 433 for (i = tx_start; i <= tx_end; i++) 434 txqs |= (0x3 << (i * 2)); 435 436 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 437 if (ret != 0) 438 return ret; 439 440 /* Reset secondary nic queue counters */ 441 for (i = 0; i < nic->sqs_count; i++) { 442 struct nicvf *snic = nic->snicvf[i]; 443 if (snic == NULL) 444 break; 445 446 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 447 for (i = rx_start; i <= rx_end; i++) 448 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 449 450 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 451 for (i = tx_start; i <= tx_end; i++) 452 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 453 454 ret = nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 455 if (ret != 0) 456 return ret; 457 } 458 459 return 0; 460 } 461 462 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 463 static int 464 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 465 { 466 return 0; 467 } 468 469 static inline uint64_t 470 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 471 { 472 uint64_t nic_rss = 0; 473 474 if (ethdev_rss & RTE_ETH_RSS_IPV4) 475 nic_rss |= RSS_IP_ENA; 476 477 if (ethdev_rss & RTE_ETH_RSS_IPV6) 478 nic_rss |= RSS_IP_ENA; 479 480 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 481 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 482 483 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 484 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 485 486 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 487 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 488 489 if (ethdev_rss & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 490 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 491 492 if (ethdev_rss & RTE_ETH_RSS_PORT) 493 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 494 495 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 496 if (ethdev_rss & RTE_ETH_RSS_VXLAN) 497 nic_rss |= RSS_TUN_VXLAN_ENA; 498 499 if (ethdev_rss & RTE_ETH_RSS_GENEVE) 500 nic_rss |= RSS_TUN_GENEVE_ENA; 501 502 if (ethdev_rss & RTE_ETH_RSS_NVGRE) 503 nic_rss |= RSS_TUN_NVGRE_ENA; 504 } 505 506 return nic_rss; 507 } 508 509 static inline uint64_t 510 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 511 { 512 uint64_t ethdev_rss = 0; 513 514 if (nic_rss & RSS_IP_ENA) 515 ethdev_rss |= (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6); 516 517 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 518 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_TCP | 519 RTE_ETH_RSS_NONFRAG_IPV6_TCP); 520 521 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 522 ethdev_rss |= (RTE_ETH_RSS_NONFRAG_IPV4_UDP | 523 RTE_ETH_RSS_NONFRAG_IPV6_UDP); 524 525 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 526 ethdev_rss |= RTE_ETH_RSS_PORT; 527 528 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 529 if (nic_rss & RSS_TUN_VXLAN_ENA) 530 ethdev_rss |= RTE_ETH_RSS_VXLAN; 531 532 if (nic_rss & RSS_TUN_GENEVE_ENA) 533 ethdev_rss |= RTE_ETH_RSS_GENEVE; 534 535 if (nic_rss & RSS_TUN_NVGRE_ENA) 536 ethdev_rss |= RTE_ETH_RSS_NVGRE; 537 } 538 return ethdev_rss; 539 } 540 541 static int 542 nicvf_dev_reta_query(struct rte_eth_dev *dev, 543 struct rte_eth_rss_reta_entry64 *reta_conf, 544 uint16_t reta_size) 545 { 546 struct nicvf *nic = nicvf_pmd_priv(dev); 547 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 548 int ret, i, j; 549 550 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 551 PMD_DRV_LOG(ERR, 552 "The size of hash lookup table configured " 553 "(%u) doesn't match the number hardware can supported " 554 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 555 return -EINVAL; 556 } 557 558 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 559 if (ret) 560 return ret; 561 562 /* Copy RETA table */ 563 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 564 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 565 if ((reta_conf[i].mask >> j) & 0x01) 566 reta_conf[i].reta[j] = tbl[j]; 567 } 568 569 return 0; 570 } 571 572 static int 573 nicvf_dev_reta_update(struct rte_eth_dev *dev, 574 struct rte_eth_rss_reta_entry64 *reta_conf, 575 uint16_t reta_size) 576 { 577 struct nicvf *nic = nicvf_pmd_priv(dev); 578 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 579 int ret, i, j; 580 581 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 582 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 583 "(%u) doesn't match the number hardware can supported " 584 "(%u)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 585 return -EINVAL; 586 } 587 588 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 589 if (ret) 590 return ret; 591 592 /* Copy RETA table */ 593 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_ETH_RETA_GROUP_SIZE); i++) { 594 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) 595 if ((reta_conf[i].mask >> j) & 0x01) 596 tbl[j] = reta_conf[i].reta[j]; 597 } 598 599 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 600 } 601 602 static int 603 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 604 struct rte_eth_rss_conf *rss_conf) 605 { 606 struct nicvf *nic = nicvf_pmd_priv(dev); 607 608 if (rss_conf->rss_key) 609 nicvf_rss_get_key(nic, rss_conf->rss_key); 610 611 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 612 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 613 return 0; 614 } 615 616 static int 617 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 618 struct rte_eth_rss_conf *rss_conf) 619 { 620 struct nicvf *nic = nicvf_pmd_priv(dev); 621 uint64_t nic_rss; 622 623 if (rss_conf->rss_key && 624 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 625 PMD_DRV_LOG(ERR, "Hash key size mismatch %u", 626 rss_conf->rss_key_len); 627 return -EINVAL; 628 } 629 630 if (rss_conf->rss_key) 631 nicvf_rss_set_key(nic, rss_conf->rss_key); 632 633 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 634 nicvf_rss_set_cfg(nic, nic_rss); 635 return 0; 636 } 637 638 static int 639 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 640 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 641 { 642 const struct rte_memzone *rz; 643 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 644 645 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 646 nicvf_netdev_qidx(nic, qidx), ring_size, 647 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 648 if (rz == NULL) { 649 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 650 return -ENOMEM; 651 } 652 653 memset(rz->addr, 0, ring_size); 654 655 rxq->phys = rz->iova; 656 rxq->desc = rz->addr; 657 rxq->qlen_mask = desc_cnt - 1; 658 659 return 0; 660 } 661 662 static int 663 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 664 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 665 { 666 const struct rte_memzone *rz; 667 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 668 669 rz = rte_eth_dma_zone_reserve(dev, "sq", 670 nicvf_netdev_qidx(nic, qidx), ring_size, 671 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 672 if (rz == NULL) { 673 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 674 return -ENOMEM; 675 } 676 677 memset(rz->addr, 0, ring_size); 678 679 sq->phys = rz->iova; 680 sq->desc = rz->addr; 681 sq->qlen_mask = desc_cnt - 1; 682 683 return 0; 684 } 685 686 static int 687 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 688 uint32_t desc_cnt, uint32_t buffsz) 689 { 690 struct nicvf_rbdr *rbdr; 691 const struct rte_memzone *rz; 692 uint32_t ring_size; 693 694 assert(nic->rbdr == NULL); 695 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 696 RTE_CACHE_LINE_SIZE, nic->node); 697 if (rbdr == NULL) { 698 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 699 return -ENOMEM; 700 } 701 702 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 703 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 704 nicvf_netdev_qidx(nic, 0), ring_size, 705 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 706 if (rz == NULL) { 707 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 708 rte_free(rbdr); 709 return -ENOMEM; 710 } 711 712 memset(rz->addr, 0, ring_size); 713 714 rbdr->phys = rz->iova; 715 rbdr->tail = 0; 716 rbdr->next_tail = 0; 717 rbdr->desc = rz->addr; 718 rbdr->buffsz = buffsz; 719 rbdr->qlen_mask = desc_cnt - 1; 720 rbdr->rbdr_status = 721 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 722 rbdr->rbdr_door = 723 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 724 725 nic->rbdr = rbdr; 726 return 0; 727 } 728 729 static void 730 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 731 nicvf_iova_addr_t phy) 732 { 733 uint16_t qidx; 734 void *obj; 735 struct nicvf_rxq *rxq; 736 uint16_t rx_start, rx_end; 737 738 /* Get queue ranges for this VF */ 739 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 740 741 for (qidx = rx_start; qidx <= rx_end; qidx++) { 742 rxq = dev->data->rx_queues[qidx]; 743 if (rxq->precharge_cnt) { 744 obj = (void *)nicvf_mbuff_phy2virt(phy, 745 rxq->mbuf_phys_off); 746 rte_mempool_put(rxq->pool, obj); 747 rxq->precharge_cnt--; 748 break; 749 } 750 } 751 } 752 753 static inline void 754 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 755 { 756 uint32_t qlen_mask, head; 757 struct rbdr_entry_t *entry; 758 struct nicvf_rbdr *rbdr = nic->rbdr; 759 760 qlen_mask = rbdr->qlen_mask; 761 head = rbdr->head; 762 while (head != rbdr->tail) { 763 entry = rbdr->desc + head; 764 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 765 head++; 766 head = head & qlen_mask; 767 } 768 } 769 770 static inline void 771 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 772 { 773 uint32_t head; 774 775 head = txq->head; 776 while (head != txq->tail) { 777 if (txq->txbuffs[head]) { 778 rte_pktmbuf_free_seg(txq->txbuffs[head]); 779 txq->txbuffs[head] = NULL; 780 } 781 head++; 782 head = head & txq->qlen_mask; 783 } 784 } 785 786 static void 787 nicvf_tx_queue_reset(struct nicvf_txq *txq) 788 { 789 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 790 791 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 792 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 793 txq->tail = 0; 794 txq->head = 0; 795 txq->xmit_bufs = 0; 796 } 797 798 static inline int 799 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 800 uint16_t qidx) 801 { 802 struct nicvf_txq *txq; 803 int ret; 804 805 assert(qidx < MAX_SND_QUEUES_PER_QS); 806 807 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 808 RTE_ETH_QUEUE_STATE_STARTED) 809 return 0; 810 811 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 812 txq->pool = NULL; 813 ret = nicvf_qset_sq_config(nic, qidx, txq); 814 if (ret) { 815 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 816 nic->vf_id, qidx, ret); 817 goto config_sq_error; 818 } 819 820 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 821 RTE_ETH_QUEUE_STATE_STARTED; 822 return ret; 823 824 config_sq_error: 825 nicvf_qset_sq_reclaim(nic, qidx); 826 return ret; 827 } 828 829 static inline int 830 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 831 uint16_t qidx) 832 { 833 struct nicvf_txq *txq; 834 int ret; 835 836 assert(qidx < MAX_SND_QUEUES_PER_QS); 837 838 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 839 RTE_ETH_QUEUE_STATE_STOPPED) 840 return 0; 841 842 ret = nicvf_qset_sq_reclaim(nic, qidx); 843 if (ret) 844 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 845 nic->vf_id, qidx, ret); 846 847 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 848 nicvf_tx_queue_release_mbufs(txq); 849 nicvf_tx_queue_reset(txq); 850 851 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 852 RTE_ETH_QUEUE_STATE_STOPPED; 853 return ret; 854 } 855 856 static inline int 857 nicvf_configure_cpi(struct rte_eth_dev *dev) 858 { 859 struct nicvf *nic = nicvf_pmd_priv(dev); 860 uint16_t qidx, qcnt; 861 int ret; 862 863 /* Count started rx queues */ 864 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 865 if (dev->data->rx_queue_state[qidx] == 866 RTE_ETH_QUEUE_STATE_STARTED) 867 qcnt++; 868 869 nic->cpi_alg = CPI_ALG_NONE; 870 ret = nicvf_mbox_config_cpi(nic, qcnt); 871 if (ret) 872 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 873 874 return ret; 875 } 876 877 static inline int 878 nicvf_configure_rss(struct rte_eth_dev *dev) 879 { 880 struct nicvf *nic = nicvf_pmd_priv(dev); 881 uint64_t rsshf; 882 int ret = -EINVAL; 883 884 rsshf = nicvf_rss_ethdev_to_nic(nic, 885 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 886 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 887 dev->data->dev_conf.rxmode.mq_mode, 888 dev->data->nb_rx_queues, 889 dev->data->dev_conf.lpbk_mode, rsshf); 890 891 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 892 ret = nicvf_rss_term(nic); 893 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 894 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 895 if (ret) 896 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 897 898 return ret; 899 } 900 901 static int 902 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 903 { 904 struct nicvf *nic = nicvf_pmd_priv(dev); 905 unsigned int idx, qmap_size; 906 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 907 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 908 909 if (nic->cpi_alg != CPI_ALG_NONE) 910 return -EINVAL; 911 912 /* Prepare queue map */ 913 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 914 if (dev->data->rx_queue_state[idx] == 915 RTE_ETH_QUEUE_STATE_STARTED) 916 qmap[qmap_size++] = idx; 917 } 918 919 /* Update default RSS RETA */ 920 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 921 default_reta[idx] = qmap[idx % qmap_size]; 922 923 return nicvf_rss_reta_update(nic, default_reta, 924 NIC_MAX_RSS_IDR_TBL_SIZE); 925 } 926 927 static void 928 nicvf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 929 { 930 struct nicvf_txq *txq = dev->data->tx_queues[qid]; 931 932 PMD_INIT_FUNC_TRACE(); 933 934 if (txq) { 935 if (txq->txbuffs != NULL) { 936 nicvf_tx_queue_release_mbufs(txq); 937 rte_free(txq->txbuffs); 938 txq->txbuffs = NULL; 939 } 940 rte_free(txq); 941 dev->data->tx_queues[qid] = NULL; 942 } 943 } 944 945 static void 946 nicvf_set_tx_function(struct rte_eth_dev *dev) 947 { 948 struct nicvf_txq *txq = NULL; 949 size_t i; 950 bool multiseg = false; 951 952 for (i = 0; i < dev->data->nb_tx_queues; i++) { 953 txq = dev->data->tx_queues[i]; 954 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) { 955 multiseg = true; 956 break; 957 } 958 } 959 960 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 961 if (multiseg) { 962 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 963 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 964 } else { 965 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 966 dev->tx_pkt_burst = nicvf_xmit_pkts; 967 } 968 969 if (!txq) 970 return; 971 972 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 973 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 974 else 975 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 976 } 977 978 static void 979 nicvf_set_rx_function(struct rte_eth_dev *dev) 980 { 981 struct nicvf *nic = nicvf_pmd_priv(dev); 982 983 const eth_rx_burst_t rx_burst_func[2][2][2] = { 984 /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */ 985 [0][0][0] = nicvf_recv_pkts_no_offload, 986 [0][0][1] = nicvf_recv_pkts_vlan_strip, 987 [0][1][0] = nicvf_recv_pkts_cksum, 988 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip, 989 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload, 990 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip, 991 [1][1][0] = nicvf_recv_pkts_multiseg_cksum, 992 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip, 993 }; 994 995 dev->rx_pkt_burst = 996 rx_burst_func[dev->data->scattered_rx] 997 [nic->offload_cksum][nic->vlan_strip]; 998 } 999 1000 static int 1001 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1002 uint16_t nb_desc, unsigned int socket_id, 1003 const struct rte_eth_txconf *tx_conf) 1004 { 1005 uint16_t tx_free_thresh; 1006 bool is_single_pool; 1007 struct nicvf_txq *txq; 1008 struct nicvf *nic = nicvf_pmd_priv(dev); 1009 uint64_t offloads; 1010 1011 PMD_INIT_FUNC_TRACE(); 1012 1013 if (qidx >= MAX_SND_QUEUES_PER_QS) 1014 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 1015 1016 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1017 1018 /* Socket id check */ 1019 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1020 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1021 socket_id, nic->node); 1022 1023 /* Tx deferred start is not supported */ 1024 if (tx_conf->tx_deferred_start) { 1025 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 1026 return -EINVAL; 1027 } 1028 1029 /* Roundup nb_desc to available qsize and validate max number of desc */ 1030 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 1031 if (nb_desc == 0) { 1032 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 1033 return -EINVAL; 1034 } 1035 1036 /* Validate tx_free_thresh */ 1037 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 1038 tx_conf->tx_free_thresh : 1039 NICVF_DEFAULT_TX_FREE_THRESH); 1040 1041 if (tx_free_thresh > (nb_desc) || 1042 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 1043 PMD_INIT_LOG(ERR, 1044 "tx_free_thresh must be less than the number of TX " 1045 "descriptors. (tx_free_thresh=%u port=%d " 1046 "queue=%d)", (unsigned int)tx_free_thresh, 1047 (int)dev->data->port_id, (int)qidx); 1048 return -EINVAL; 1049 } 1050 1051 /* Free memory prior to re-allocation if needed. */ 1052 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1053 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1054 nicvf_netdev_qidx(nic, qidx)); 1055 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1056 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1057 } 1058 1059 /* Allocating tx queue data structure */ 1060 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 1061 RTE_CACHE_LINE_SIZE, nic->node); 1062 if (txq == NULL) { 1063 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 1064 nicvf_netdev_qidx(nic, qidx)); 1065 return -ENOMEM; 1066 } 1067 1068 txq->nic = nic; 1069 txq->queue_id = qidx; 1070 txq->tx_free_thresh = tx_free_thresh; 1071 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1072 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1073 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1074 txq->offloads = offloads; 1075 1076 is_single_pool = !!(offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE); 1077 1078 /* Choose optimum free threshold value for multipool case */ 1079 if (!is_single_pool) { 1080 txq->tx_free_thresh = (uint16_t) 1081 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1082 NICVF_TX_FREE_MPOOL_THRESH : 1083 tx_conf->tx_free_thresh); 1084 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1085 } else { 1086 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1087 } 1088 1089 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1090 1091 /* Allocate software ring */ 1092 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1093 nb_desc * sizeof(struct rte_mbuf *), 1094 RTE_CACHE_LINE_SIZE, nic->node); 1095 1096 if (txq->txbuffs == NULL) { 1097 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1098 return -ENOMEM; 1099 } 1100 1101 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1102 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1103 nicvf_dev_tx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1104 return -ENOMEM; 1105 } 1106 1107 nicvf_tx_queue_reset(txq); 1108 1109 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1110 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1111 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1112 txq->phys, txq->offloads); 1113 1114 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1115 RTE_ETH_QUEUE_STATE_STOPPED; 1116 return 0; 1117 } 1118 1119 static inline void 1120 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1121 { 1122 uint32_t rxq_cnt; 1123 uint32_t nb_pkts, released_pkts = 0; 1124 uint32_t refill_cnt = 0; 1125 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1126 1127 if (dev->rx_pkt_burst == NULL) 1128 return; 1129 1130 while ((rxq_cnt = nicvf_dev_rx_queue_count(rxq))) { 1131 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1132 NICVF_MAX_RX_FREE_THRESH); 1133 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1134 while (nb_pkts) { 1135 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1136 released_pkts++; 1137 } 1138 } 1139 1140 1141 refill_cnt += nicvf_dev_rbdr_refill(dev, 1142 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1143 1144 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1145 released_pkts, refill_cnt); 1146 } 1147 1148 static void 1149 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1150 { 1151 rxq->head = 0; 1152 rxq->available_space = 0; 1153 rxq->recv_buffers = 0; 1154 } 1155 1156 static inline int 1157 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1158 uint16_t qidx) 1159 { 1160 struct nicvf_rxq *rxq; 1161 int ret; 1162 1163 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1164 1165 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1166 RTE_ETH_QUEUE_STATE_STARTED) 1167 return 0; 1168 1169 /* Update rbdr pointer to all rxq */ 1170 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1171 rxq->shared_rbdr = nic->rbdr; 1172 1173 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1174 if (ret) { 1175 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1176 nic->vf_id, qidx, ret); 1177 goto config_rq_error; 1178 } 1179 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1180 if (ret) { 1181 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1182 nic->vf_id, qidx, ret); 1183 goto config_cq_error; 1184 } 1185 1186 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1187 RTE_ETH_QUEUE_STATE_STARTED; 1188 return 0; 1189 1190 config_cq_error: 1191 nicvf_qset_cq_reclaim(nic, qidx); 1192 config_rq_error: 1193 nicvf_qset_rq_reclaim(nic, qidx); 1194 return ret; 1195 } 1196 1197 static inline int 1198 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1199 uint16_t qidx) 1200 { 1201 struct nicvf_rxq *rxq; 1202 int ret, other_error; 1203 1204 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1205 RTE_ETH_QUEUE_STATE_STOPPED) 1206 return 0; 1207 1208 ret = nicvf_qset_rq_reclaim(nic, qidx); 1209 if (ret) 1210 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1211 nic->vf_id, qidx, ret); 1212 1213 other_error = ret; 1214 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1215 nicvf_rx_queue_release_mbufs(dev, rxq); 1216 nicvf_rx_queue_reset(rxq); 1217 1218 ret = nicvf_qset_cq_reclaim(nic, qidx); 1219 if (ret) 1220 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1221 nic->vf_id, qidx, ret); 1222 1223 other_error |= ret; 1224 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1225 RTE_ETH_QUEUE_STATE_STOPPED; 1226 return other_error; 1227 } 1228 1229 static void 1230 nicvf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) 1231 { 1232 PMD_INIT_FUNC_TRACE(); 1233 1234 rte_free(dev->data->rx_queues[qid]); 1235 } 1236 1237 static int 1238 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1239 { 1240 struct nicvf *nic = nicvf_pmd_priv(dev); 1241 int ret; 1242 1243 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1244 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1245 1246 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1247 1248 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1249 if (ret) 1250 return ret; 1251 1252 ret = nicvf_configure_cpi(dev); 1253 if (ret) 1254 return ret; 1255 1256 return nicvf_configure_rss_reta(dev); 1257 } 1258 1259 static int 1260 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1261 { 1262 int ret; 1263 struct nicvf *nic = nicvf_pmd_priv(dev); 1264 1265 if (qidx >= MAX_SND_QUEUES_PER_QS) 1266 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1267 1268 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1269 1270 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1271 ret |= nicvf_configure_cpi(dev); 1272 ret |= nicvf_configure_rss_reta(dev); 1273 return ret; 1274 } 1275 1276 static int 1277 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1278 { 1279 struct nicvf *nic = nicvf_pmd_priv(dev); 1280 1281 if (qidx >= MAX_SND_QUEUES_PER_QS) 1282 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1283 1284 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1285 1286 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1287 } 1288 1289 static int 1290 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1291 { 1292 struct nicvf *nic = nicvf_pmd_priv(dev); 1293 1294 if (qidx >= MAX_SND_QUEUES_PER_QS) 1295 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1296 1297 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1298 1299 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1300 } 1301 1302 static inline void 1303 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1304 { 1305 uintptr_t p; 1306 struct rte_mbuf mb_def; 1307 struct nicvf *nic = rxq->nic; 1308 1309 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1310 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1311 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1312 offsetof(struct rte_mbuf, data_off) != 2); 1313 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1314 offsetof(struct rte_mbuf, data_off) != 4); 1315 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1316 offsetof(struct rte_mbuf, data_off) != 6); 1317 RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) - 1318 offsetof(struct nicvf_rxq, 1319 rxq_fastpath_data_start) > 128); 1320 mb_def.nb_segs = 1; 1321 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1322 mb_def.port = rxq->port_id; 1323 rte_mbuf_refcnt_set(&mb_def, 1); 1324 1325 /* Prevent compiler reordering: rearm_data covers previous fields */ 1326 rte_compiler_barrier(); 1327 p = (uintptr_t)&mb_def.rearm_data; 1328 rxq->mbuf_initializer.value = *(uint64_t *)p; 1329 } 1330 1331 static int 1332 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1333 uint16_t nb_desc, unsigned int socket_id, 1334 const struct rte_eth_rxconf *rx_conf, 1335 struct rte_mempool *mp) 1336 { 1337 uint16_t rx_free_thresh; 1338 struct nicvf_rxq *rxq; 1339 struct nicvf *nic = nicvf_pmd_priv(dev); 1340 uint64_t offloads; 1341 uint32_t buffsz; 1342 struct rte_pktmbuf_pool_private *mbp_priv; 1343 1344 PMD_INIT_FUNC_TRACE(); 1345 1346 /* First skip check */ 1347 mbp_priv = rte_mempool_get_priv(mp); 1348 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1349 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1350 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1351 return -EINVAL; 1352 } 1353 1354 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1355 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1356 1357 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1358 1359 /* Socket id check */ 1360 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1361 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1362 socket_id, nic->node); 1363 1364 /* Mempool memory must be contiguous, so must be one memory segment*/ 1365 if (mp->nb_mem_chunks != 1) { 1366 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1367 return -EINVAL; 1368 } 1369 1370 /* Mempool memory must be physically contiguous */ 1371 if (mp->flags & RTE_MEMPOOL_F_NO_IOVA_CONTIG) { 1372 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1373 return -EINVAL; 1374 } 1375 1376 /* Rx deferred start is not supported */ 1377 if (rx_conf->rx_deferred_start) { 1378 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1379 return -EINVAL; 1380 } 1381 1382 /* Roundup nb_desc to available qsize and validate max number of desc */ 1383 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1384 if (nb_desc == 0) { 1385 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1386 return -EINVAL; 1387 } 1388 1389 1390 /* Check rx_free_thresh upper bound */ 1391 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1392 rx_conf->rx_free_thresh : 1393 NICVF_DEFAULT_RX_FREE_THRESH); 1394 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1395 rx_free_thresh >= nb_desc * .75) { 1396 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1397 rx_free_thresh); 1398 return -EINVAL; 1399 } 1400 1401 /* Free memory prior to re-allocation if needed */ 1402 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1403 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1404 nicvf_netdev_qidx(nic, qidx)); 1405 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1406 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1407 } 1408 1409 /* Allocate rxq memory */ 1410 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1411 RTE_CACHE_LINE_SIZE, nic->node); 1412 if (rxq == NULL) { 1413 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1414 nicvf_netdev_qidx(nic, qidx)); 1415 return -ENOMEM; 1416 } 1417 1418 rxq->nic = nic; 1419 rxq->pool = mp; 1420 rxq->queue_id = qidx; 1421 rxq->port_id = dev->data->port_id; 1422 rxq->rx_free_thresh = rx_free_thresh; 1423 rxq->rx_drop_en = rx_conf->rx_drop_en; 1424 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1425 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1426 rxq->precharge_cnt = 0; 1427 1428 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1429 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1430 else 1431 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1432 1433 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1434 1435 nicvf_rxq_mbuf_setup(rxq); 1436 1437 /* Alloc completion queue */ 1438 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1439 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1440 nicvf_dev_rx_queue_release(dev, nicvf_netdev_qidx(nic, qidx)); 1441 return -ENOMEM; 1442 } 1443 1444 nicvf_rx_queue_reset(rxq); 1445 1446 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1447 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1448 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1449 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1450 rte_mempool_avail_count(mp), rxq->phys, offloads); 1451 1452 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1453 RTE_ETH_QUEUE_STATE_STOPPED; 1454 return 0; 1455 } 1456 1457 static int 1458 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1459 { 1460 struct nicvf *nic = nicvf_pmd_priv(dev); 1461 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1462 1463 PMD_INIT_FUNC_TRACE(); 1464 1465 /* Autonegotiation may be disabled */ 1466 dev_info->speed_capa = RTE_ETH_LINK_SPEED_FIXED; 1467 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_10M | RTE_ETH_LINK_SPEED_100M | 1468 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G; 1469 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1470 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_40G; 1471 1472 dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU; 1473 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN; 1474 dev_info->max_rx_queues = 1475 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1476 dev_info->max_tx_queues = 1477 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1478 dev_info->max_mac_addrs = 1; 1479 dev_info->max_vfs = pci_dev->max_vfs; 1480 1481 dev_info->max_mtu = dev_info->max_rx_pktlen - 1482 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 1483 dev_info->min_mtu = dev_info->min_rx_bufsize - NIC_HW_L2_OVERHEAD; 1484 1485 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1486 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1487 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1488 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1489 1490 dev_info->reta_size = nic->rss_info.rss_size; 1491 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1492 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1493 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1494 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1495 1496 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1497 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1498 .rx_drop_en = 0, 1499 }; 1500 1501 dev_info->default_txconf = (struct rte_eth_txconf) { 1502 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1503 .offloads = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | 1504 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1505 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1506 RTE_ETH_TX_OFFLOAD_TCP_CKSUM, 1507 }; 1508 1509 return 0; 1510 } 1511 1512 static nicvf_iova_addr_t 1513 rbdr_rte_mempool_get(void *dev, void *opaque) 1514 { 1515 uint16_t qidx; 1516 uintptr_t mbuf; 1517 struct nicvf_rxq *rxq; 1518 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1519 struct nicvf *nic = (struct nicvf *)opaque; 1520 uint16_t rx_start, rx_end; 1521 1522 /* Get queue ranges for this VF */ 1523 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1524 1525 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1526 rxq = eth_dev->data->rx_queues[qidx]; 1527 /* Maintain equal buffer count across all pools */ 1528 if (rxq->precharge_cnt >= rxq->qlen_mask) 1529 continue; 1530 rxq->precharge_cnt++; 1531 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1532 if (mbuf) 1533 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1534 } 1535 return 0; 1536 } 1537 1538 static int 1539 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1540 { 1541 int ret; 1542 uint16_t qidx, data_off; 1543 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1544 uint64_t mbuf_phys_off = 0; 1545 struct nicvf_rxq *rxq; 1546 struct rte_mbuf *mbuf; 1547 uint16_t rx_start, rx_end; 1548 uint16_t tx_start, tx_end; 1549 int mask; 1550 1551 PMD_INIT_FUNC_TRACE(); 1552 1553 /* Userspace process exited without proper shutdown in last run */ 1554 if (nicvf_qset_rbdr_active(nic, 0)) 1555 nicvf_vf_stop(dev, nic, false); 1556 1557 /* Get queue ranges for this VF */ 1558 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1559 1560 /* 1561 * Thunderx nicvf PMD can support more than one pool per port only when 1562 * 1) Data payload size is same across all the pools in given port 1563 * AND 1564 * 2) All mbuffs in the pools are from the same hugepage 1565 * AND 1566 * 3) Mbuff metadata size is same across all the pools in given port 1567 * 1568 * This is to support existing application that uses multiple pool/port. 1569 * But, the purpose of using multipool for QoS will not be addressed. 1570 * 1571 */ 1572 1573 /* Validate mempool attributes */ 1574 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1575 rxq = dev->data->rx_queues[qidx]; 1576 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1577 mbuf = rte_pktmbuf_alloc(rxq->pool); 1578 if (mbuf == NULL) { 1579 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1580 "pool=%s", 1581 nic->vf_id, qidx, rxq->pool->name); 1582 return -ENOMEM; 1583 } 1584 data_off = nicvf_mbuff_meta_length(mbuf); 1585 data_off += RTE_PKTMBUF_HEADROOM; 1586 rte_pktmbuf_free(mbuf); 1587 1588 if (data_off % RTE_CACHE_LINE_SIZE) { 1589 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1590 rxq->pool->name, data_off, 1591 data_off % RTE_CACHE_LINE_SIZE); 1592 return -EINVAL; 1593 } 1594 rxq->mbuf_phys_off -= data_off; 1595 rxq->mbuf_phys_off -= nic->skip_bytes; 1596 1597 if (mbuf_phys_off == 0) 1598 mbuf_phys_off = rxq->mbuf_phys_off; 1599 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1600 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1601 PRIx64, rxq->pool->name, nic->vf_id, 1602 mbuf_phys_off); 1603 return -EINVAL; 1604 } 1605 } 1606 1607 /* Check the level of buffers in the pool */ 1608 total_rxq_desc = 0; 1609 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1610 rxq = dev->data->rx_queues[qidx]; 1611 /* Count total numbers of rxq descs */ 1612 total_rxq_desc += rxq->qlen_mask + 1; 1613 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1614 exp_buffs *= dev->data->nb_rx_queues; 1615 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1616 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1617 rxq->pool->name, 1618 rte_mempool_avail_count(rxq->pool), 1619 exp_buffs); 1620 return -ENOENT; 1621 } 1622 } 1623 1624 /* Check RBDR desc overflow */ 1625 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1626 if (ret == 0) { 1627 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1628 "VF%d", nic->vf_id); 1629 return -ENOMEM; 1630 } 1631 1632 /* Enable qset */ 1633 ret = nicvf_qset_config(nic); 1634 if (ret) { 1635 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1636 nic->vf_id); 1637 return ret; 1638 } 1639 1640 /* Allocate RBDR and RBDR ring desc */ 1641 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1642 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1643 if (ret) { 1644 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1645 "VF%d", nic->vf_id); 1646 goto qset_reclaim; 1647 } 1648 1649 /* Enable and configure RBDR registers */ 1650 ret = nicvf_qset_rbdr_config(nic, 0); 1651 if (ret) { 1652 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1653 nic->vf_id); 1654 goto qset_rbdr_free; 1655 } 1656 1657 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1658 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1659 total_rxq_desc); 1660 if (ret) { 1661 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1662 nic->vf_id); 1663 goto qset_rbdr_reclaim; 1664 } 1665 1666 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1667 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1668 1669 /* Configure VLAN Strip */ 1670 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | 1671 RTE_ETH_VLAN_EXTEND_MASK; 1672 ret = nicvf_vlan_offload_config(dev, mask); 1673 1674 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1675 * to the 64bit memory address. 1676 * The alignment creates a hole in mbuf(between the end of headroom and 1677 * packet data start). The new revision of the HW provides an option to 1678 * disable the L3 alignment feature and make mbuf layout looks 1679 * more like other NICs. For better application compatibility, disabling 1680 * l3 alignment feature on the hardware revisions it supports 1681 */ 1682 nicvf_apad_config(nic, false); 1683 1684 /* Get queue ranges for this VF */ 1685 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1686 1687 /* Configure TX queues */ 1688 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1689 ret = nicvf_vf_start_tx_queue(dev, nic, 1690 qidx % MAX_SND_QUEUES_PER_QS); 1691 if (ret) 1692 goto start_txq_error; 1693 } 1694 1695 /* Configure RX queues */ 1696 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1697 ret = nicvf_vf_start_rx_queue(dev, nic, 1698 qidx % MAX_RCV_QUEUES_PER_QS); 1699 if (ret) 1700 goto start_rxq_error; 1701 } 1702 1703 if (!nic->sqs_mode) { 1704 /* Configure CPI algorithm */ 1705 ret = nicvf_configure_cpi(dev); 1706 if (ret) 1707 goto start_txq_error; 1708 1709 ret = nicvf_mbox_get_rss_size(nic); 1710 if (ret) { 1711 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1712 goto qset_rss_error; 1713 } 1714 1715 /* Configure RSS */ 1716 ret = nicvf_configure_rss(dev); 1717 if (ret) 1718 goto qset_rss_error; 1719 } 1720 1721 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1722 nicvf_mbox_cfg_done(nic); 1723 return 0; 1724 1725 qset_rss_error: 1726 nicvf_rss_term(nic); 1727 start_rxq_error: 1728 for (qidx = rx_start; qidx <= rx_end; qidx++) 1729 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1730 start_txq_error: 1731 for (qidx = tx_start; qidx <= tx_end; qidx++) 1732 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1733 qset_rbdr_reclaim: 1734 nicvf_qset_rbdr_reclaim(nic, 0); 1735 nicvf_rbdr_release_mbufs(dev, nic); 1736 qset_rbdr_free: 1737 if (nic->rbdr) { 1738 rte_free(nic->rbdr); 1739 nic->rbdr = NULL; 1740 } 1741 qset_reclaim: 1742 nicvf_qset_reclaim(nic); 1743 return ret; 1744 } 1745 1746 static int 1747 nicvf_dev_start(struct rte_eth_dev *dev) 1748 { 1749 uint16_t qidx; 1750 int ret; 1751 size_t i; 1752 struct nicvf *nic = nicvf_pmd_priv(dev); 1753 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1754 uint16_t mtu; 1755 uint32_t buffsz = 0, rbdrsz = 0; 1756 struct rte_pktmbuf_pool_private *mbp_priv; 1757 struct nicvf_rxq *rxq; 1758 1759 PMD_INIT_FUNC_TRACE(); 1760 1761 /* This function must be called for a primary device */ 1762 assert_primary(nic); 1763 1764 /* Validate RBDR buff size */ 1765 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1766 rxq = dev->data->rx_queues[qidx]; 1767 mbp_priv = rte_mempool_get_priv(rxq->pool); 1768 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1769 if (buffsz % 128) { 1770 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1771 return -EINVAL; 1772 } 1773 if (rbdrsz == 0) 1774 rbdrsz = buffsz; 1775 if (rbdrsz != buffsz) { 1776 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1777 qidx, rbdrsz, buffsz); 1778 return -EINVAL; 1779 } 1780 } 1781 1782 /* Configure loopback */ 1783 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1784 if (ret) { 1785 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1786 return ret; 1787 } 1788 1789 /* Reset all statistics counters attached to this port */ 1790 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1791 if (ret) { 1792 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1793 return ret; 1794 } 1795 1796 /* Setup scatter mode if needed by jumbo */ 1797 if (dev->data->mtu + (uint32_t)NIC_HW_L2_OVERHEAD + 2 * VLAN_TAG_SIZE > buffsz) 1798 dev->data->scattered_rx = 1; 1799 if ((rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) != 0) 1800 dev->data->scattered_rx = 1; 1801 1802 /* Setup MTU */ 1803 mtu = dev->data->mtu; 1804 1805 if (nicvf_dev_set_mtu(dev, mtu)) { 1806 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1807 return -EBUSY; 1808 } 1809 1810 /* Apply new link configurations if changed */ 1811 ret = nicvf_apply_link_speed(dev); 1812 if (ret) { 1813 PMD_INIT_LOG(ERR, "Failed to set link configuration\n"); 1814 return ret; 1815 } 1816 1817 ret = nicvf_vf_start(dev, nic, rbdrsz); 1818 if (ret != 0) 1819 return ret; 1820 1821 for (i = 0; i < nic->sqs_count; i++) { 1822 assert(nic->snicvf[i]); 1823 1824 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1825 if (ret != 0) 1826 return ret; 1827 } 1828 1829 /* Configure callbacks based on offloads */ 1830 nicvf_set_tx_function(dev); 1831 nicvf_set_rx_function(dev); 1832 1833 return 0; 1834 } 1835 1836 static void 1837 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1838 { 1839 size_t i; 1840 int ret; 1841 struct nicvf *nic = nicvf_pmd_priv(dev); 1842 1843 PMD_INIT_FUNC_TRACE(); 1844 dev->data->dev_started = 0; 1845 1846 /* Teardown secondary vf first */ 1847 for (i = 0; i < nic->sqs_count; i++) { 1848 if (!nic->snicvf[i]) 1849 continue; 1850 1851 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1852 } 1853 1854 /* Stop the primary VF now */ 1855 nicvf_vf_stop(dev, nic, cleanup); 1856 1857 /* Disable loopback */ 1858 ret = nicvf_loopback_config(nic, 0); 1859 if (ret) 1860 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1861 1862 /* Reclaim CPI configuration */ 1863 ret = nicvf_mbox_config_cpi(nic, 0); 1864 if (ret) 1865 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1866 } 1867 1868 static int 1869 nicvf_dev_stop(struct rte_eth_dev *dev) 1870 { 1871 PMD_INIT_FUNC_TRACE(); 1872 1873 nicvf_dev_stop_cleanup(dev, false); 1874 1875 return 0; 1876 } 1877 1878 static void 1879 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1880 { 1881 int ret; 1882 uint16_t qidx; 1883 uint16_t tx_start, tx_end; 1884 uint16_t rx_start, rx_end; 1885 1886 PMD_INIT_FUNC_TRACE(); 1887 1888 if (cleanup) { 1889 /* Let PF make the BGX's RX and TX switches to OFF position */ 1890 nicvf_mbox_shutdown(nic); 1891 } 1892 1893 /* Disable VLAN Strip */ 1894 nicvf_vlan_hw_strip(nic, 0); 1895 1896 /* Get queue ranges for this VF */ 1897 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1898 1899 for (qidx = tx_start; qidx <= tx_end; qidx++) 1900 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1901 1902 /* Get queue ranges for this VF */ 1903 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1904 1905 /* Reclaim rq */ 1906 for (qidx = rx_start; qidx <= rx_end; qidx++) 1907 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1908 1909 /* Reclaim RBDR */ 1910 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1911 if (ret) 1912 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1913 1914 /* Move all charged buffers in RBDR back to pool */ 1915 if (nic->rbdr != NULL) 1916 nicvf_rbdr_release_mbufs(dev, nic); 1917 1918 /* Disable qset */ 1919 ret = nicvf_qset_reclaim(nic); 1920 if (ret) 1921 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1922 1923 /* Disable all interrupts */ 1924 nicvf_disable_all_interrupts(nic); 1925 1926 /* Free RBDR SW structure */ 1927 if (nic->rbdr) { 1928 rte_free(nic->rbdr); 1929 nic->rbdr = NULL; 1930 } 1931 } 1932 1933 static int 1934 nicvf_dev_close(struct rte_eth_dev *dev) 1935 { 1936 struct nicvf *nic = nicvf_pmd_priv(dev); 1937 1938 PMD_INIT_FUNC_TRACE(); 1939 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1940 return 0; 1941 1942 nicvf_dev_stop_cleanup(dev, true); 1943 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1944 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic); 1945 1946 rte_intr_instance_free(nic->intr_handle); 1947 1948 return 0; 1949 } 1950 1951 static int 1952 nicvf_request_sqs(struct nicvf *nic) 1953 { 1954 size_t i; 1955 1956 assert_primary(nic); 1957 assert(nic->sqs_count > 0); 1958 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1959 1960 /* Set no of Rx/Tx queues in each of the SQsets */ 1961 for (i = 0; i < nic->sqs_count; i++) { 1962 if (nicvf_svf_empty()) 1963 rte_panic("Cannot assign sufficient number of " 1964 "secondary queues to primary VF%" PRIu8 "\n", 1965 nic->vf_id); 1966 1967 nic->snicvf[i] = nicvf_svf_pop(); 1968 nic->snicvf[i]->sqs_id = i; 1969 } 1970 1971 return nicvf_mbox_request_sqs(nic); 1972 } 1973 1974 static int 1975 nicvf_dev_configure(struct rte_eth_dev *dev) 1976 { 1977 struct rte_eth_dev_data *data = dev->data; 1978 struct rte_eth_conf *conf = &data->dev_conf; 1979 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1980 struct rte_eth_txmode *txmode = &conf->txmode; 1981 struct nicvf *nic = nicvf_pmd_priv(dev); 1982 uint8_t cqcount; 1983 1984 PMD_INIT_FUNC_TRACE(); 1985 1986 if (rxmode->mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1987 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1988 1989 if (!rte_eal_has_hugepages()) { 1990 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1991 return -EINVAL; 1992 } 1993 1994 if (txmode->mq_mode) { 1995 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1996 return -EINVAL; 1997 } 1998 1999 if (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE && 2000 rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) { 2001 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 2002 return -EINVAL; 2003 } 2004 2005 if (conf->dcb_capability_en) { 2006 PMD_INIT_LOG(INFO, "DCB enable not supported"); 2007 return -EINVAL; 2008 } 2009 2010 assert_primary(nic); 2011 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 2012 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 2013 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 2014 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 2015 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 2016 } else { 2017 nic->sqs_count = 0; 2018 } 2019 2020 assert(nic->sqs_count <= MAX_SQS_PER_VF); 2021 2022 if (nic->sqs_count > 0) { 2023 if (nicvf_request_sqs(nic)) { 2024 rte_panic("Cannot assign sufficient number of " 2025 "secondary queues to PORT%d VF%" PRIu8 "\n", 2026 dev->data->port_id, nic->vf_id); 2027 } 2028 } 2029 2030 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM) 2031 nic->offload_cksum = 1; 2032 2033 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 2034 dev->data->port_id, nicvf_hw_cap(nic)); 2035 2036 return 0; 2037 } 2038 2039 static int 2040 nicvf_dev_set_link_up(struct rte_eth_dev *dev) 2041 { 2042 struct nicvf *nic = nicvf_pmd_priv(dev); 2043 int rc, i; 2044 2045 rc = nicvf_mbox_set_link_up_down(nic, true); 2046 if (rc) 2047 goto done; 2048 2049 /* Start tx queues */ 2050 for (i = 0; i < dev->data->nb_tx_queues; i++) 2051 nicvf_dev_tx_queue_start(dev, i); 2052 2053 done: 2054 return rc; 2055 } 2056 2057 static int 2058 nicvf_dev_set_link_down(struct rte_eth_dev *dev) 2059 { 2060 struct nicvf *nic = nicvf_pmd_priv(dev); 2061 int i; 2062 2063 /* Stop tx queues */ 2064 for (i = 0; i < dev->data->nb_tx_queues; i++) 2065 nicvf_dev_tx_queue_stop(dev, i); 2066 2067 return nicvf_mbox_set_link_up_down(nic, false); 2068 } 2069 2070 /* Initialize and register driver with DPDK Application */ 2071 static const struct eth_dev_ops nicvf_eth_dev_ops = { 2072 .dev_configure = nicvf_dev_configure, 2073 .dev_start = nicvf_dev_start, 2074 .dev_stop = nicvf_dev_stop, 2075 .link_update = nicvf_dev_link_update, 2076 .dev_close = nicvf_dev_close, 2077 .stats_get = nicvf_dev_stats_get, 2078 .stats_reset = nicvf_dev_stats_reset, 2079 .promiscuous_enable = nicvf_dev_promisc_enable, 2080 .dev_infos_get = nicvf_dev_info_get, 2081 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 2082 .mtu_set = nicvf_dev_set_mtu, 2083 .vlan_offload_set = nicvf_vlan_offload_set, 2084 .reta_update = nicvf_dev_reta_update, 2085 .reta_query = nicvf_dev_reta_query, 2086 .rss_hash_update = nicvf_dev_rss_hash_update, 2087 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2088 .rx_queue_start = nicvf_dev_rx_queue_start, 2089 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2090 .tx_queue_start = nicvf_dev_tx_queue_start, 2091 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2092 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2093 .rx_queue_release = nicvf_dev_rx_queue_release, 2094 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2095 .tx_queue_release = nicvf_dev_tx_queue_release, 2096 .dev_set_link_up = nicvf_dev_set_link_up, 2097 .dev_set_link_down = nicvf_dev_set_link_down, 2098 .get_reg = nicvf_dev_get_regs, 2099 }; 2100 2101 static int 2102 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2103 { 2104 struct rte_eth_rxmode *rxmode; 2105 struct nicvf *nic = nicvf_pmd_priv(dev); 2106 rxmode = &dev->data->dev_conf.rxmode; 2107 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2108 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 2109 nicvf_vlan_hw_strip(nic, true); 2110 else 2111 nicvf_vlan_hw_strip(nic, false); 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int 2118 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2119 { 2120 nicvf_vlan_offload_config(dev, mask); 2121 2122 return 0; 2123 } 2124 2125 static inline int 2126 nicvf_set_first_skip(struct rte_eth_dev *dev) 2127 { 2128 int bytes_to_skip = 0; 2129 int ret = 0; 2130 unsigned int i; 2131 struct rte_kvargs *kvlist; 2132 static const char *const skip[] = { 2133 SKIP_DATA_BYTES, 2134 NULL}; 2135 struct nicvf *nic = nicvf_pmd_priv(dev); 2136 2137 if (!dev->device->devargs) { 2138 nicvf_first_skip_config(nic, 0); 2139 return ret; 2140 } 2141 2142 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2143 if (!kvlist) 2144 return -EINVAL; 2145 2146 if (kvlist->count == 0) 2147 goto exit; 2148 2149 for (i = 0; i != kvlist->count; ++i) { 2150 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2151 2152 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2153 bytes_to_skip = atoi(pair->value); 2154 } 2155 2156 /*128 bytes amounts to one cache line*/ 2157 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2158 if (!(bytes_to_skip % 8)) { 2159 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2160 nic->skip_bytes = bytes_to_skip; 2161 goto kvlist_free; 2162 } else { 2163 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2164 ret = -EINVAL; 2165 goto exit; 2166 } 2167 } else { 2168 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2169 ret = -EINVAL; 2170 goto exit; 2171 } 2172 exit: 2173 nicvf_first_skip_config(nic, 0); 2174 kvlist_free: 2175 rte_kvargs_free(kvlist); 2176 return ret; 2177 } 2178 static int 2179 nicvf_eth_dev_uninit(struct rte_eth_dev *dev) 2180 { 2181 PMD_INIT_FUNC_TRACE(); 2182 nicvf_dev_close(dev); 2183 return 0; 2184 } 2185 static int 2186 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2187 { 2188 int ret; 2189 struct rte_pci_device *pci_dev; 2190 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2191 2192 PMD_INIT_FUNC_TRACE(); 2193 2194 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2195 eth_dev->rx_queue_count = nicvf_dev_rx_queue_count; 2196 2197 /* For secondary processes, the primary has done all the work */ 2198 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2199 if (nic) { 2200 /* Setup callbacks for secondary process */ 2201 nicvf_set_tx_function(eth_dev); 2202 nicvf_set_rx_function(eth_dev); 2203 return 0; 2204 } else { 2205 /* If nic == NULL than it is secondary function 2206 * so ethdev need to be released by caller */ 2207 return ENOTSUP; 2208 } 2209 } 2210 2211 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2212 rte_eth_copy_pci_info(eth_dev, pci_dev); 2213 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2214 2215 nic->device_id = pci_dev->id.device_id; 2216 nic->vendor_id = pci_dev->id.vendor_id; 2217 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2218 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2219 2220 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) " PCI_PRI_FMT, 2221 pci_dev->id.vendor_id, pci_dev->id.device_id, 2222 pci_dev->addr.domain, pci_dev->addr.bus, 2223 pci_dev->addr.devid, pci_dev->addr.function); 2224 2225 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2226 if (!nic->reg_base) { 2227 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2228 ret = -ENODEV; 2229 goto fail; 2230 } 2231 2232 /* Allocate interrupt instance */ 2233 nic->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED); 2234 if (nic->intr_handle == NULL) { 2235 PMD_INIT_LOG(ERR, "Failed to allocate intr handle"); 2236 ret = -ENODEV; 2237 goto fail; 2238 } 2239 2240 nicvf_disable_all_interrupts(nic); 2241 2242 /* To read mbox messages */ 2243 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2244 if (ret) { 2245 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2246 goto fail; 2247 } 2248 2249 /* To poll link status change*/ 2250 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2251 if (ret) { 2252 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2253 goto fail; 2254 } 2255 2256 ret = nicvf_mbox_check_pf_ready(nic); 2257 if (ret) { 2258 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2259 goto alarm_fail; 2260 } else { 2261 PMD_INIT_LOG(INFO, 2262 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2263 nic->node, nic->vf_id, 2264 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2265 nic->sqs_mode ? "true" : "false", 2266 nic->loopback_supported ? "true" : "false" 2267 ); 2268 } 2269 2270 /* To make sure RX DMAC register is set to default value (0x3) */ 2271 nicvf_mbox_reset_xcast(nic); 2272 2273 ret = nicvf_base_init(nic); 2274 if (ret) { 2275 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2276 goto malloc_fail; 2277 } 2278 2279 if (nic->sqs_mode) { 2280 /* Push nic to stack of secondary vfs */ 2281 nicvf_svf_push(nic); 2282 2283 /* Steal nic pointer from the device for further reuse */ 2284 eth_dev->data->dev_private = NULL; 2285 2286 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2287 2288 /* Detach port by returning positive error number */ 2289 return ENOTSUP; 2290 } 2291 2292 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2293 RTE_ETHER_ADDR_LEN, 0); 2294 if (eth_dev->data->mac_addrs == NULL) { 2295 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2296 ret = -ENOMEM; 2297 goto alarm_fail; 2298 } 2299 if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr)) 2300 rte_eth_random_addr(&nic->mac_addr[0]); 2301 2302 rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr, 2303 ð_dev->data->mac_addrs[0]); 2304 2305 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2306 if (ret) { 2307 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2308 goto malloc_fail; 2309 } 2310 2311 ret = nicvf_set_first_skip(eth_dev); 2312 if (ret) { 2313 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2314 goto malloc_fail; 2315 } 2316 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=" RTE_ETHER_ADDR_PRT_FMT, 2317 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2318 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2319 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2320 2321 return 0; 2322 2323 malloc_fail: 2324 rte_free(eth_dev->data->mac_addrs); 2325 eth_dev->data->mac_addrs = NULL; 2326 alarm_fail: 2327 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2328 fail: 2329 return ret; 2330 } 2331 2332 static const struct rte_pci_id pci_id_nicvf_map[] = { 2333 { 2334 .class_id = RTE_CLASS_ANY_ID, 2335 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2336 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2337 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2338 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2339 }, 2340 { 2341 .class_id = RTE_CLASS_ANY_ID, 2342 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2343 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2344 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2345 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2346 }, 2347 { 2348 .class_id = RTE_CLASS_ANY_ID, 2349 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2350 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2351 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2352 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2353 }, 2354 { 2355 .class_id = RTE_CLASS_ANY_ID, 2356 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2357 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2358 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2359 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2360 }, 2361 { 2362 .vendor_id = 0, 2363 }, 2364 }; 2365 2366 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2367 struct rte_pci_device *pci_dev) 2368 { 2369 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2370 nicvf_eth_dev_init); 2371 } 2372 2373 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2374 { 2375 return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit); 2376 } 2377 2378 static struct rte_pci_driver rte_nicvf_pmd = { 2379 .id_table = pci_id_nicvf_map, 2380 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2381 RTE_PCI_DRV_INTR_LSC, 2382 .probe = nicvf_eth_pci_probe, 2383 .remove = nicvf_eth_pci_remove, 2384 }; 2385 2386 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2387 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2388 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2389 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2390