1 /* 2 * BSD LICENSE 3 * 4 * Copyright (C) Cavium networks Ltd. 2016. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Cavium networks nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <assert.h> 34 #include <stdio.h> 35 #include <stdbool.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 #include <sys/queue.h> 44 #include <sys/timerfd.h> 45 46 #include <rte_alarm.h> 47 #include <rte_atomic.h> 48 #include <rte_branch_prediction.h> 49 #include <rte_byteorder.h> 50 #include <rte_common.h> 51 #include <rte_cycles.h> 52 #include <rte_debug.h> 53 #include <rte_dev.h> 54 #include <rte_eal.h> 55 #include <rte_ether.h> 56 #include <rte_ethdev.h> 57 #include <rte_interrupts.h> 58 #include <rte_log.h> 59 #include <rte_memory.h> 60 #include <rte_memzone.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_pci.h> 64 #include <rte_tailq.h> 65 66 #include "base/nicvf_plat.h" 67 68 #include "nicvf_ethdev.h" 69 #include "nicvf_rxtx.h" 70 #include "nicvf_logs.h" 71 72 static void nicvf_dev_stop(struct rte_eth_dev *dev); 73 74 static inline int 75 nicvf_atomic_write_link_status(struct rte_eth_dev *dev, 76 struct rte_eth_link *link) 77 { 78 struct rte_eth_link *dst = &dev->data->dev_link; 79 struct rte_eth_link *src = link; 80 81 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 82 *(uint64_t *)src) == 0) 83 return -1; 84 85 return 0; 86 } 87 88 static inline void 89 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link) 90 { 91 link->link_status = nic->link_up; 92 link->link_duplex = ETH_LINK_AUTONEG; 93 if (nic->duplex == NICVF_HALF_DUPLEX) 94 link->link_duplex = ETH_LINK_HALF_DUPLEX; 95 else if (nic->duplex == NICVF_FULL_DUPLEX) 96 link->link_duplex = ETH_LINK_FULL_DUPLEX; 97 link->link_speed = nic->speed; 98 link->link_autoneg = ETH_LINK_SPEED_AUTONEG; 99 } 100 101 static void 102 nicvf_interrupt(void *arg) 103 { 104 struct rte_eth_dev *dev = arg; 105 struct nicvf *nic = nicvf_pmd_priv(dev); 106 107 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 108 if (dev->data->dev_conf.intr_conf.lsc) 109 nicvf_set_eth_link_status(nic, &dev->data->dev_link); 110 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC); 111 } 112 113 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 114 nicvf_interrupt, dev); 115 } 116 117 static void __rte_unused 118 nicvf_vf_interrupt(void *arg) 119 { 120 struct nicvf *nic = arg; 121 122 nicvf_reg_poll_interrupts(nic); 123 124 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 125 nicvf_vf_interrupt, nic); 126 } 127 128 static int 129 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 130 { 131 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 132 } 133 134 static int 135 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 136 { 137 return rte_eal_alarm_cancel(fn, arg); 138 } 139 140 /* 141 * Return 0 means link status changed, -1 means not changed 142 */ 143 static int 144 nicvf_dev_link_update(struct rte_eth_dev *dev, 145 int wait_to_complete __rte_unused) 146 { 147 struct rte_eth_link link; 148 struct nicvf *nic = nicvf_pmd_priv(dev); 149 150 PMD_INIT_FUNC_TRACE(); 151 152 memset(&link, 0, sizeof(link)); 153 nicvf_set_eth_link_status(nic, &link); 154 return nicvf_atomic_write_link_status(dev, &link); 155 } 156 157 static int 158 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 159 { 160 struct nicvf *nic = nicvf_pmd_priv(dev); 161 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 162 163 PMD_INIT_FUNC_TRACE(); 164 165 if (frame_size > NIC_HW_MAX_FRS) 166 return -EINVAL; 167 168 if (frame_size < NIC_HW_MIN_FRS) 169 return -EINVAL; 170 171 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 172 173 /* 174 * Refuse mtu that requires the support of scattered packets 175 * when this feature has not been enabled before. 176 */ 177 if (!dev->data->scattered_rx && 178 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 179 return -EINVAL; 180 181 /* check <seg size> * <max_seg> >= max_frame */ 182 if (dev->data->scattered_rx && 183 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 184 return -EINVAL; 185 186 if (frame_size > ETHER_MAX_LEN) 187 dev->data->dev_conf.rxmode.jumbo_frame = 1; 188 else 189 dev->data->dev_conf.rxmode.jumbo_frame = 0; 190 191 if (nicvf_mbox_update_hw_max_frs(nic, frame_size)) 192 return -EINVAL; 193 194 /* Update max frame size */ 195 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size; 196 nic->mtu = mtu; 197 return 0; 198 } 199 200 static int 201 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 202 { 203 uint64_t *data = regs->data; 204 struct nicvf *nic = nicvf_pmd_priv(dev); 205 206 if (data == NULL) { 207 regs->length = nicvf_reg_get_count(); 208 regs->width = THUNDERX_REG_BYTES; 209 return 0; 210 } 211 212 /* Support only full register dump */ 213 if ((regs->length == 0) || 214 (regs->length == (uint32_t)nicvf_reg_get_count())) { 215 regs->version = nic->vendor_id << 16 | nic->device_id; 216 nicvf_reg_dump(nic, data); 217 return 0; 218 } 219 return -ENOTSUP; 220 } 221 222 static void 223 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 224 { 225 uint16_t qidx; 226 struct nicvf_hw_rx_qstats rx_qstats; 227 struct nicvf_hw_tx_qstats tx_qstats; 228 struct nicvf_hw_stats port_stats; 229 struct nicvf *nic = nicvf_pmd_priv(dev); 230 231 /* Reading per RX ring stats */ 232 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 233 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS) 234 break; 235 236 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 237 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 238 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 239 } 240 241 /* Reading per TX ring stats */ 242 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) { 243 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS) 244 break; 245 246 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 247 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 248 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 249 } 250 251 nicvf_hw_get_stats(nic, &port_stats); 252 stats->ibytes = port_stats.rx_bytes; 253 stats->ipackets = port_stats.rx_ucast_frames; 254 stats->ipackets += port_stats.rx_bcast_frames; 255 stats->ipackets += port_stats.rx_mcast_frames; 256 stats->ierrors = port_stats.rx_l2_errors; 257 stats->imissed = port_stats.rx_drop_red; 258 stats->imissed += port_stats.rx_drop_overrun; 259 stats->imissed += port_stats.rx_drop_bcast; 260 stats->imissed += port_stats.rx_drop_mcast; 261 stats->imissed += port_stats.rx_drop_l3_bcast; 262 stats->imissed += port_stats.rx_drop_l3_mcast; 263 264 stats->obytes = port_stats.tx_bytes_ok; 265 stats->opackets = port_stats.tx_ucast_frames_ok; 266 stats->opackets += port_stats.tx_bcast_frames_ok; 267 stats->opackets += port_stats.tx_mcast_frames_ok; 268 stats->oerrors = port_stats.tx_drops; 269 } 270 271 static const uint32_t * 272 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 273 { 274 size_t copied; 275 static uint32_t ptypes[32]; 276 struct nicvf *nic = nicvf_pmd_priv(dev); 277 static const uint32_t ptypes_common[] = { 278 RTE_PTYPE_L3_IPV4, 279 RTE_PTYPE_L3_IPV4_EXT, 280 RTE_PTYPE_L3_IPV6, 281 RTE_PTYPE_L3_IPV6_EXT, 282 RTE_PTYPE_L4_TCP, 283 RTE_PTYPE_L4_UDP, 284 RTE_PTYPE_L4_FRAG, 285 }; 286 static const uint32_t ptypes_tunnel[] = { 287 RTE_PTYPE_TUNNEL_GRE, 288 RTE_PTYPE_TUNNEL_GENEVE, 289 RTE_PTYPE_TUNNEL_VXLAN, 290 RTE_PTYPE_TUNNEL_NVGRE, 291 }; 292 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 293 294 copied = sizeof(ptypes_common); 295 memcpy(ptypes, ptypes_common, copied); 296 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 297 memcpy((char *)ptypes + copied, ptypes_tunnel, 298 sizeof(ptypes_tunnel)); 299 copied += sizeof(ptypes_tunnel); 300 } 301 302 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 303 if (dev->rx_pkt_burst == nicvf_recv_pkts || 304 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg) 305 return ptypes; 306 307 return NULL; 308 } 309 310 static void 311 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 312 { 313 int i; 314 uint16_t rxqs = 0, txqs = 0; 315 struct nicvf *nic = nicvf_pmd_priv(dev); 316 317 for (i = 0; i < dev->data->nb_rx_queues; i++) 318 rxqs |= (0x3 << (i * 2)); 319 for (i = 0; i < dev->data->nb_tx_queues; i++) 320 txqs |= (0x3 << (i * 2)); 321 322 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 323 } 324 325 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 326 static void 327 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 328 { 329 } 330 331 static inline uint64_t 332 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 333 { 334 uint64_t nic_rss = 0; 335 336 if (ethdev_rss & ETH_RSS_IPV4) 337 nic_rss |= RSS_IP_ENA; 338 339 if (ethdev_rss & ETH_RSS_IPV6) 340 nic_rss |= RSS_IP_ENA; 341 342 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 343 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 344 345 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 346 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 347 348 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 349 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 350 351 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 352 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 353 354 if (ethdev_rss & ETH_RSS_PORT) 355 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 356 357 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 358 if (ethdev_rss & ETH_RSS_VXLAN) 359 nic_rss |= RSS_TUN_VXLAN_ENA; 360 361 if (ethdev_rss & ETH_RSS_GENEVE) 362 nic_rss |= RSS_TUN_GENEVE_ENA; 363 364 if (ethdev_rss & ETH_RSS_NVGRE) 365 nic_rss |= RSS_TUN_NVGRE_ENA; 366 } 367 368 return nic_rss; 369 } 370 371 static inline uint64_t 372 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 373 { 374 uint64_t ethdev_rss = 0; 375 376 if (nic_rss & RSS_IP_ENA) 377 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 378 379 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 380 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 381 ETH_RSS_NONFRAG_IPV6_TCP); 382 383 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 384 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 385 ETH_RSS_NONFRAG_IPV6_UDP); 386 387 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 388 ethdev_rss |= ETH_RSS_PORT; 389 390 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 391 if (nic_rss & RSS_TUN_VXLAN_ENA) 392 ethdev_rss |= ETH_RSS_VXLAN; 393 394 if (nic_rss & RSS_TUN_GENEVE_ENA) 395 ethdev_rss |= ETH_RSS_GENEVE; 396 397 if (nic_rss & RSS_TUN_NVGRE_ENA) 398 ethdev_rss |= ETH_RSS_NVGRE; 399 } 400 return ethdev_rss; 401 } 402 403 static int 404 nicvf_dev_reta_query(struct rte_eth_dev *dev, 405 struct rte_eth_rss_reta_entry64 *reta_conf, 406 uint16_t reta_size) 407 { 408 struct nicvf *nic = nicvf_pmd_priv(dev); 409 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 410 int ret, i, j; 411 412 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 413 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 414 "(%d) doesn't match the number hardware can supported " 415 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 416 return -EINVAL; 417 } 418 419 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 420 if (ret) 421 return ret; 422 423 /* Copy RETA table */ 424 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 425 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 426 if ((reta_conf[i].mask >> j) & 0x01) 427 reta_conf[i].reta[j] = tbl[j]; 428 } 429 430 return 0; 431 } 432 433 static int 434 nicvf_dev_reta_update(struct rte_eth_dev *dev, 435 struct rte_eth_rss_reta_entry64 *reta_conf, 436 uint16_t reta_size) 437 { 438 struct nicvf *nic = nicvf_pmd_priv(dev); 439 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 440 int ret, i, j; 441 442 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 443 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 444 "(%d) doesn't match the number hardware can supported " 445 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 446 return -EINVAL; 447 } 448 449 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 450 if (ret) 451 return ret; 452 453 /* Copy RETA table */ 454 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 455 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 456 if ((reta_conf[i].mask >> j) & 0x01) 457 tbl[j] = reta_conf[i].reta[j]; 458 } 459 460 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 461 } 462 463 static int 464 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 465 struct rte_eth_rss_conf *rss_conf) 466 { 467 struct nicvf *nic = nicvf_pmd_priv(dev); 468 469 if (rss_conf->rss_key) 470 nicvf_rss_get_key(nic, rss_conf->rss_key); 471 472 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 473 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 474 return 0; 475 } 476 477 static int 478 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 479 struct rte_eth_rss_conf *rss_conf) 480 { 481 struct nicvf *nic = nicvf_pmd_priv(dev); 482 uint64_t nic_rss; 483 484 if (rss_conf->rss_key && 485 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 486 RTE_LOG(ERR, PMD, "Hash key size mismatch %d", 487 rss_conf->rss_key_len); 488 return -EINVAL; 489 } 490 491 if (rss_conf->rss_key) 492 nicvf_rss_set_key(nic, rss_conf->rss_key); 493 494 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 495 nicvf_rss_set_cfg(nic, nic_rss); 496 return 0; 497 } 498 499 static int 500 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 501 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 502 { 503 const struct rte_memzone *rz; 504 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 505 506 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", qidx, ring_size, 507 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 508 if (rz == NULL) { 509 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 510 return -ENOMEM; 511 } 512 513 memset(rz->addr, 0, ring_size); 514 515 rxq->phys = rz->phys_addr; 516 rxq->desc = rz->addr; 517 rxq->qlen_mask = desc_cnt - 1; 518 519 return 0; 520 } 521 522 static int 523 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 524 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 525 { 526 const struct rte_memzone *rz; 527 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 528 529 rz = rte_eth_dma_zone_reserve(dev, "sq", qidx, ring_size, 530 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 531 if (rz == NULL) { 532 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 533 return -ENOMEM; 534 } 535 536 memset(rz->addr, 0, ring_size); 537 538 sq->phys = rz->phys_addr; 539 sq->desc = rz->addr; 540 sq->qlen_mask = desc_cnt - 1; 541 542 return 0; 543 } 544 545 static int 546 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 547 uint32_t desc_cnt, uint32_t buffsz) 548 { 549 struct nicvf_rbdr *rbdr; 550 const struct rte_memzone *rz; 551 uint32_t ring_size; 552 553 assert(nic->rbdr == NULL); 554 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 555 RTE_CACHE_LINE_SIZE, nic->node); 556 if (rbdr == NULL) { 557 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 558 return -ENOMEM; 559 } 560 561 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 562 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 0, ring_size, 563 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 564 if (rz == NULL) { 565 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 566 return -ENOMEM; 567 } 568 569 memset(rz->addr, 0, ring_size); 570 571 rbdr->phys = rz->phys_addr; 572 rbdr->tail = 0; 573 rbdr->next_tail = 0; 574 rbdr->desc = rz->addr; 575 rbdr->buffsz = buffsz; 576 rbdr->qlen_mask = desc_cnt - 1; 577 rbdr->rbdr_status = 578 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 579 rbdr->rbdr_door = 580 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 581 582 nic->rbdr = rbdr; 583 return 0; 584 } 585 586 static void 587 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic __rte_unused, 588 nicvf_phys_addr_t phy) 589 { 590 uint16_t qidx; 591 void *obj; 592 struct nicvf_rxq *rxq; 593 594 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 595 rxq = dev->data->rx_queues[qidx]; 596 if (rxq->precharge_cnt) { 597 obj = (void *)nicvf_mbuff_phy2virt(phy, 598 rxq->mbuf_phys_off); 599 rte_mempool_put(rxq->pool, obj); 600 rxq->precharge_cnt--; 601 break; 602 } 603 } 604 } 605 606 static inline void 607 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 608 { 609 uint32_t qlen_mask, head; 610 struct rbdr_entry_t *entry; 611 struct nicvf_rbdr *rbdr = nic->rbdr; 612 613 qlen_mask = rbdr->qlen_mask; 614 head = rbdr->head; 615 while (head != rbdr->tail) { 616 entry = rbdr->desc + head; 617 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 618 head++; 619 head = head & qlen_mask; 620 } 621 } 622 623 static inline void 624 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 625 { 626 uint32_t head; 627 628 head = txq->head; 629 while (head != txq->tail) { 630 if (txq->txbuffs[head]) { 631 rte_pktmbuf_free_seg(txq->txbuffs[head]); 632 txq->txbuffs[head] = NULL; 633 } 634 head++; 635 head = head & txq->qlen_mask; 636 } 637 } 638 639 static void 640 nicvf_tx_queue_reset(struct nicvf_txq *txq) 641 { 642 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 643 644 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 645 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 646 txq->tail = 0; 647 txq->head = 0; 648 txq->xmit_bufs = 0; 649 } 650 651 static inline int 652 nicvf_start_tx_queue(struct rte_eth_dev *dev, uint16_t qidx) 653 { 654 struct nicvf_txq *txq; 655 int ret; 656 657 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) 658 return 0; 659 660 txq = dev->data->tx_queues[qidx]; 661 txq->pool = NULL; 662 ret = nicvf_qset_sq_config(nicvf_pmd_priv(dev), qidx, txq); 663 if (ret) { 664 PMD_INIT_LOG(ERR, "Failed to configure sq %d %d", qidx, ret); 665 goto config_sq_error; 666 } 667 668 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 669 return ret; 670 671 config_sq_error: 672 nicvf_qset_sq_reclaim(nicvf_pmd_priv(dev), qidx); 673 return ret; 674 } 675 676 static inline int 677 nicvf_stop_tx_queue(struct rte_eth_dev *dev, uint16_t qidx) 678 { 679 struct nicvf_txq *txq; 680 int ret; 681 682 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) 683 return 0; 684 685 ret = nicvf_qset_sq_reclaim(nicvf_pmd_priv(dev), qidx); 686 if (ret) 687 PMD_INIT_LOG(ERR, "Failed to reclaim sq %d %d", qidx, ret); 688 689 txq = dev->data->tx_queues[qidx]; 690 nicvf_tx_queue_release_mbufs(txq); 691 nicvf_tx_queue_reset(txq); 692 693 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 694 return ret; 695 } 696 697 static inline int 698 nicvf_configure_cpi(struct rte_eth_dev *dev) 699 { 700 struct nicvf *nic = nicvf_pmd_priv(dev); 701 uint16_t qidx, qcnt; 702 int ret; 703 704 /* Count started rx queues */ 705 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 706 if (dev->data->rx_queue_state[qidx] == 707 RTE_ETH_QUEUE_STATE_STARTED) 708 qcnt++; 709 710 nic->cpi_alg = CPI_ALG_NONE; 711 ret = nicvf_mbox_config_cpi(nic, qcnt); 712 if (ret) 713 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 714 715 return ret; 716 } 717 718 static inline int 719 nicvf_configure_rss(struct rte_eth_dev *dev) 720 { 721 struct nicvf *nic = nicvf_pmd_priv(dev); 722 uint64_t rsshf; 723 int ret = -EINVAL; 724 725 rsshf = nicvf_rss_ethdev_to_nic(nic, 726 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 727 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 728 dev->data->dev_conf.rxmode.mq_mode, 729 dev->data->nb_rx_queues, 730 dev->data->dev_conf.lpbk_mode, rsshf); 731 732 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 733 ret = nicvf_rss_term(nic); 734 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 735 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 736 if (ret) 737 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 738 739 return ret; 740 } 741 742 static int 743 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 744 { 745 struct nicvf *nic = nicvf_pmd_priv(dev); 746 unsigned int idx, qmap_size; 747 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 748 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 749 750 if (nic->cpi_alg != CPI_ALG_NONE) 751 return -EINVAL; 752 753 /* Prepare queue map */ 754 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 755 if (dev->data->rx_queue_state[idx] == 756 RTE_ETH_QUEUE_STATE_STARTED) 757 qmap[qmap_size++] = idx; 758 } 759 760 /* Update default RSS RETA */ 761 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 762 default_reta[idx] = qmap[idx % qmap_size]; 763 764 return nicvf_rss_reta_update(nic, default_reta, 765 NIC_MAX_RSS_IDR_TBL_SIZE); 766 } 767 768 static void 769 nicvf_dev_tx_queue_release(void *sq) 770 { 771 struct nicvf_txq *txq; 772 773 PMD_INIT_FUNC_TRACE(); 774 775 txq = (struct nicvf_txq *)sq; 776 if (txq) { 777 if (txq->txbuffs != NULL) { 778 nicvf_tx_queue_release_mbufs(txq); 779 rte_free(txq->txbuffs); 780 txq->txbuffs = NULL; 781 } 782 rte_free(txq); 783 } 784 } 785 786 static void 787 nicvf_set_tx_function(struct rte_eth_dev *dev) 788 { 789 struct nicvf_txq *txq; 790 size_t i; 791 bool multiseg = false; 792 793 for (i = 0; i < dev->data->nb_tx_queues; i++) { 794 txq = dev->data->tx_queues[i]; 795 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) { 796 multiseg = true; 797 break; 798 } 799 } 800 801 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 802 if (multiseg) { 803 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 804 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 805 } else { 806 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 807 dev->tx_pkt_burst = nicvf_xmit_pkts; 808 } 809 810 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 811 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 812 else 813 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 814 } 815 816 static void 817 nicvf_set_rx_function(struct rte_eth_dev *dev) 818 { 819 if (dev->data->scattered_rx) { 820 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback"); 821 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg; 822 } else { 823 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback"); 824 dev->rx_pkt_burst = nicvf_recv_pkts; 825 } 826 } 827 828 static int 829 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 830 uint16_t nb_desc, unsigned int socket_id, 831 const struct rte_eth_txconf *tx_conf) 832 { 833 uint16_t tx_free_thresh; 834 uint8_t is_single_pool; 835 struct nicvf_txq *txq; 836 struct nicvf *nic = nicvf_pmd_priv(dev); 837 838 PMD_INIT_FUNC_TRACE(); 839 840 /* Socket id check */ 841 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 842 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 843 socket_id, nic->node); 844 845 /* Tx deferred start is not supported */ 846 if (tx_conf->tx_deferred_start) { 847 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 848 return -EINVAL; 849 } 850 851 /* Roundup nb_desc to available qsize and validate max number of desc */ 852 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 853 if (nb_desc == 0) { 854 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 855 return -EINVAL; 856 } 857 858 /* Validate tx_free_thresh */ 859 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 860 tx_conf->tx_free_thresh : 861 NICVF_DEFAULT_TX_FREE_THRESH); 862 863 if (tx_free_thresh > (nb_desc) || 864 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 865 PMD_INIT_LOG(ERR, 866 "tx_free_thresh must be less than the number of TX " 867 "descriptors. (tx_free_thresh=%u port=%d " 868 "queue=%d)", (unsigned int)tx_free_thresh, 869 (int)dev->data->port_id, (int)qidx); 870 return -EINVAL; 871 } 872 873 /* Free memory prior to re-allocation if needed. */ 874 if (dev->data->tx_queues[qidx] != NULL) { 875 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 876 qidx); 877 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]); 878 dev->data->tx_queues[qidx] = NULL; 879 } 880 881 /* Allocating tx queue data structure */ 882 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 883 RTE_CACHE_LINE_SIZE, nic->node); 884 if (txq == NULL) { 885 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx); 886 return -ENOMEM; 887 } 888 889 txq->nic = nic; 890 txq->queue_id = qidx; 891 txq->tx_free_thresh = tx_free_thresh; 892 txq->txq_flags = tx_conf->txq_flags; 893 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 894 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 895 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT && 896 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP); 897 898 /* Choose optimum free threshold value for multipool case */ 899 if (!is_single_pool) { 900 txq->tx_free_thresh = (uint16_t) 901 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 902 NICVF_TX_FREE_MPOOL_THRESH : 903 tx_conf->tx_free_thresh); 904 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 905 } else { 906 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 907 } 908 909 /* Allocate software ring */ 910 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 911 nb_desc * sizeof(struct rte_mbuf *), 912 RTE_CACHE_LINE_SIZE, nic->node); 913 914 if (txq->txbuffs == NULL) { 915 nicvf_dev_tx_queue_release(txq); 916 return -ENOMEM; 917 } 918 919 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 920 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 921 nicvf_dev_tx_queue_release(txq); 922 return -ENOMEM; 923 } 924 925 nicvf_tx_queue_reset(txq); 926 927 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64, 928 qidx, txq, nb_desc, txq->desc, txq->phys); 929 930 dev->data->tx_queues[qidx] = txq; 931 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 932 return 0; 933 } 934 935 static inline void 936 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 937 { 938 uint32_t rxq_cnt; 939 uint32_t nb_pkts, released_pkts = 0; 940 uint32_t refill_cnt = 0; 941 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 942 943 if (dev->rx_pkt_burst == NULL) 944 return; 945 946 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, rxq->queue_id))) { 947 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 948 NICVF_MAX_RX_FREE_THRESH); 949 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 950 while (nb_pkts) { 951 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 952 released_pkts++; 953 } 954 } 955 956 refill_cnt += nicvf_dev_rbdr_refill(dev, rxq->queue_id); 957 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 958 released_pkts, refill_cnt); 959 } 960 961 static void 962 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 963 { 964 rxq->head = 0; 965 rxq->available_space = 0; 966 rxq->recv_buffers = 0; 967 } 968 969 static inline int 970 nicvf_start_rx_queue(struct rte_eth_dev *dev, uint16_t qidx) 971 { 972 struct nicvf *nic = nicvf_pmd_priv(dev); 973 struct nicvf_rxq *rxq; 974 int ret; 975 976 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) 977 return 0; 978 979 /* Update rbdr pointer to all rxq */ 980 rxq = dev->data->rx_queues[qidx]; 981 rxq->shared_rbdr = nic->rbdr; 982 983 ret = nicvf_qset_rq_config(nic, qidx, rxq); 984 if (ret) { 985 PMD_INIT_LOG(ERR, "Failed to configure rq %d %d", qidx, ret); 986 goto config_rq_error; 987 } 988 ret = nicvf_qset_cq_config(nic, qidx, rxq); 989 if (ret) { 990 PMD_INIT_LOG(ERR, "Failed to configure cq %d %d", qidx, ret); 991 goto config_cq_error; 992 } 993 994 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 995 return 0; 996 997 config_cq_error: 998 nicvf_qset_cq_reclaim(nic, qidx); 999 config_rq_error: 1000 nicvf_qset_rq_reclaim(nic, qidx); 1001 return ret; 1002 } 1003 1004 static inline int 1005 nicvf_stop_rx_queue(struct rte_eth_dev *dev, uint16_t qidx) 1006 { 1007 struct nicvf *nic = nicvf_pmd_priv(dev); 1008 struct nicvf_rxq *rxq; 1009 int ret, other_error; 1010 1011 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) 1012 return 0; 1013 1014 ret = nicvf_qset_rq_reclaim(nic, qidx); 1015 if (ret) 1016 PMD_INIT_LOG(ERR, "Failed to reclaim rq %d %d", qidx, ret); 1017 1018 other_error = ret; 1019 rxq = dev->data->rx_queues[qidx]; 1020 nicvf_rx_queue_release_mbufs(dev, rxq); 1021 nicvf_rx_queue_reset(rxq); 1022 1023 ret = nicvf_qset_cq_reclaim(nic, qidx); 1024 if (ret) 1025 PMD_INIT_LOG(ERR, "Failed to reclaim cq %d %d", qidx, ret); 1026 1027 other_error |= ret; 1028 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1029 return other_error; 1030 } 1031 1032 static void 1033 nicvf_dev_rx_queue_release(void *rx_queue) 1034 { 1035 PMD_INIT_FUNC_TRACE(); 1036 1037 rte_free(rx_queue); 1038 } 1039 1040 static int 1041 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1042 { 1043 int ret; 1044 1045 ret = nicvf_start_rx_queue(dev, qidx); 1046 if (ret) 1047 return ret; 1048 1049 ret = nicvf_configure_cpi(dev); 1050 if (ret) 1051 return ret; 1052 1053 return nicvf_configure_rss_reta(dev); 1054 } 1055 1056 static int 1057 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1058 { 1059 int ret; 1060 1061 ret = nicvf_stop_rx_queue(dev, qidx); 1062 ret |= nicvf_configure_cpi(dev); 1063 ret |= nicvf_configure_rss_reta(dev); 1064 return ret; 1065 } 1066 1067 static int 1068 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1069 { 1070 return nicvf_start_tx_queue(dev, qidx); 1071 } 1072 1073 static int 1074 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1075 { 1076 return nicvf_stop_tx_queue(dev, qidx); 1077 } 1078 1079 1080 static int 1081 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1082 uint16_t nb_desc, unsigned int socket_id, 1083 const struct rte_eth_rxconf *rx_conf, 1084 struct rte_mempool *mp) 1085 { 1086 uint16_t rx_free_thresh; 1087 struct nicvf_rxq *rxq; 1088 struct nicvf *nic = nicvf_pmd_priv(dev); 1089 1090 PMD_INIT_FUNC_TRACE(); 1091 1092 /* Socket id check */ 1093 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1094 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1095 socket_id, nic->node); 1096 1097 /* Mempool memory must be contiguous, so must be one memory segment*/ 1098 if (mp->nb_mem_chunks != 1) { 1099 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1100 return -EINVAL; 1101 } 1102 1103 /* Mempool memory must be physically contiguous */ 1104 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) { 1105 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1106 return -EINVAL; 1107 } 1108 1109 /* Rx deferred start is not supported */ 1110 if (rx_conf->rx_deferred_start) { 1111 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1112 return -EINVAL; 1113 } 1114 1115 /* Roundup nb_desc to available qsize and validate max number of desc */ 1116 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1117 if (nb_desc == 0) { 1118 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1119 return -EINVAL; 1120 } 1121 1122 /* Check rx_free_thresh upper bound */ 1123 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1124 rx_conf->rx_free_thresh : 1125 NICVF_DEFAULT_RX_FREE_THRESH); 1126 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1127 rx_free_thresh >= nb_desc * .75) { 1128 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1129 rx_free_thresh); 1130 return -EINVAL; 1131 } 1132 1133 /* Free memory prior to re-allocation if needed */ 1134 if (dev->data->rx_queues[qidx] != NULL) { 1135 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1136 qidx); 1137 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]); 1138 dev->data->rx_queues[qidx] = NULL; 1139 } 1140 1141 /* Allocate rxq memory */ 1142 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1143 RTE_CACHE_LINE_SIZE, nic->node); 1144 if (rxq == NULL) { 1145 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx); 1146 return -ENOMEM; 1147 } 1148 1149 rxq->nic = nic; 1150 rxq->pool = mp; 1151 rxq->queue_id = qidx; 1152 rxq->port_id = dev->data->port_id; 1153 rxq->rx_free_thresh = rx_free_thresh; 1154 rxq->rx_drop_en = rx_conf->rx_drop_en; 1155 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1156 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1157 rxq->precharge_cnt = 0; 1158 1159 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1160 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1161 else 1162 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1163 1164 1165 /* Alloc completion queue */ 1166 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1167 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1168 nicvf_dev_rx_queue_release(rxq); 1169 return -ENOMEM; 1170 } 1171 1172 nicvf_rx_queue_reset(rxq); 1173 1174 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64, 1175 qidx, rxq, mp->name, nb_desc, 1176 rte_mempool_avail_count(mp), rxq->phys); 1177 1178 dev->data->rx_queues[qidx] = rxq; 1179 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 1180 return 0; 1181 } 1182 1183 static void 1184 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1185 { 1186 struct nicvf *nic = nicvf_pmd_priv(dev); 1187 1188 PMD_INIT_FUNC_TRACE(); 1189 1190 dev_info->min_rx_bufsize = ETHER_MIN_MTU; 1191 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS; 1192 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS; 1193 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS; 1194 dev_info->max_mac_addrs = 1; 1195 dev_info->max_vfs = dev->pci_dev->max_vfs; 1196 1197 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP; 1198 dev_info->tx_offload_capa = 1199 DEV_TX_OFFLOAD_IPV4_CKSUM | 1200 DEV_TX_OFFLOAD_UDP_CKSUM | 1201 DEV_TX_OFFLOAD_TCP_CKSUM | 1202 DEV_TX_OFFLOAD_TCP_TSO | 1203 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 1204 1205 dev_info->reta_size = nic->rss_info.rss_size; 1206 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1207 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1208 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1209 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1210 1211 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1212 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1213 .rx_drop_en = 0, 1214 }; 1215 1216 dev_info->default_txconf = (struct rte_eth_txconf) { 1217 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1218 .txq_flags = 1219 ETH_TXQ_FLAGS_NOMULTSEGS | 1220 ETH_TXQ_FLAGS_NOREFCOUNT | 1221 ETH_TXQ_FLAGS_NOMULTMEMP | 1222 ETH_TXQ_FLAGS_NOVLANOFFL | 1223 ETH_TXQ_FLAGS_NOXSUMSCTP, 1224 }; 1225 } 1226 1227 static nicvf_phys_addr_t 1228 rbdr_rte_mempool_get(void *dev, void *opaque) 1229 { 1230 uint16_t qidx; 1231 uintptr_t mbuf; 1232 struct nicvf_rxq *rxq; 1233 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1234 struct nicvf *nic __rte_unused = (struct nicvf *)opaque; 1235 1236 for (qidx = 0; qidx < eth_dev->data->nb_rx_queues; qidx++) { 1237 rxq = eth_dev->data->rx_queues[qidx]; 1238 /* Maintain equal buffer count across all pools */ 1239 if (rxq->precharge_cnt >= rxq->qlen_mask) 1240 continue; 1241 rxq->precharge_cnt++; 1242 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1243 if (mbuf) 1244 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1245 } 1246 return 0; 1247 } 1248 1249 static int 1250 nicvf_dev_start(struct rte_eth_dev *dev) 1251 { 1252 int ret; 1253 uint16_t qidx; 1254 uint32_t buffsz = 0, rbdrsz = 0; 1255 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1256 uint64_t mbuf_phys_off = 0; 1257 struct nicvf_rxq *rxq; 1258 struct rte_pktmbuf_pool_private *mbp_priv; 1259 struct rte_mbuf *mbuf; 1260 struct nicvf *nic = nicvf_pmd_priv(dev); 1261 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1262 uint16_t mtu; 1263 1264 PMD_INIT_FUNC_TRACE(); 1265 1266 /* Userspace process exited without proper shutdown in last run */ 1267 if (nicvf_qset_rbdr_active(nic, 0)) 1268 nicvf_dev_stop(dev); 1269 1270 /* 1271 * Thunderx nicvf PMD can support more than one pool per port only when 1272 * 1) Data payload size is same across all the pools in given port 1273 * AND 1274 * 2) All mbuffs in the pools are from the same hugepage 1275 * AND 1276 * 3) Mbuff metadata size is same across all the pools in given port 1277 * 1278 * This is to support existing application that uses multiple pool/port. 1279 * But, the purpose of using multipool for QoS will not be addressed. 1280 * 1281 */ 1282 1283 /* Validate RBDR buff size */ 1284 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1285 rxq = dev->data->rx_queues[qidx]; 1286 mbp_priv = rte_mempool_get_priv(rxq->pool); 1287 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1288 if (buffsz % 128) { 1289 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1290 return -EINVAL; 1291 } 1292 if (rbdrsz == 0) 1293 rbdrsz = buffsz; 1294 if (rbdrsz != buffsz) { 1295 PMD_INIT_LOG(ERR, "buffsz not same, qid=%d (%d/%d)", 1296 qidx, rbdrsz, buffsz); 1297 return -EINVAL; 1298 } 1299 } 1300 1301 /* Validate mempool attributes */ 1302 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1303 rxq = dev->data->rx_queues[qidx]; 1304 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1305 mbuf = rte_pktmbuf_alloc(rxq->pool); 1306 if (mbuf == NULL) { 1307 PMD_INIT_LOG(ERR, "Failed allocate mbuf qid=%d pool=%s", 1308 qidx, rxq->pool->name); 1309 return -ENOMEM; 1310 } 1311 rxq->mbuf_phys_off -= nicvf_mbuff_meta_length(mbuf); 1312 rxq->mbuf_phys_off -= RTE_PKTMBUF_HEADROOM; 1313 rte_pktmbuf_free(mbuf); 1314 1315 if (mbuf_phys_off == 0) 1316 mbuf_phys_off = rxq->mbuf_phys_off; 1317 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1318 PMD_INIT_LOG(ERR, "pool params not same,%s %" PRIx64, 1319 rxq->pool->name, mbuf_phys_off); 1320 return -EINVAL; 1321 } 1322 } 1323 1324 /* Check the level of buffers in the pool */ 1325 total_rxq_desc = 0; 1326 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1327 rxq = dev->data->rx_queues[qidx]; 1328 /* Count total numbers of rxq descs */ 1329 total_rxq_desc += rxq->qlen_mask + 1; 1330 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1331 exp_buffs *= dev->data->nb_rx_queues; 1332 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1333 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1334 rxq->pool->name, 1335 rte_mempool_avail_count(rxq->pool), 1336 exp_buffs); 1337 return -ENOENT; 1338 } 1339 } 1340 1341 /* Check RBDR desc overflow */ 1342 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1343 if (ret == 0) { 1344 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc"); 1345 return -ENOMEM; 1346 } 1347 1348 /* Enable qset */ 1349 ret = nicvf_qset_config(nic); 1350 if (ret) { 1351 PMD_INIT_LOG(ERR, "Failed to enable qset %d", ret); 1352 return ret; 1353 } 1354 1355 /* Allocate RBDR and RBDR ring desc */ 1356 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1357 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1358 if (ret) { 1359 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc"); 1360 goto qset_reclaim; 1361 } 1362 1363 /* Enable and configure RBDR registers */ 1364 ret = nicvf_qset_rbdr_config(nic, 0); 1365 if (ret) { 1366 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d", ret); 1367 goto qset_rbdr_free; 1368 } 1369 1370 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1371 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1372 total_rxq_desc); 1373 if (ret) { 1374 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d", ret); 1375 goto qset_rbdr_reclaim; 1376 } 1377 1378 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR", 1379 nic->rbdr->tail, nb_rbdr_desc); 1380 1381 /* Configure RX queues */ 1382 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1383 ret = nicvf_start_rx_queue(dev, qidx); 1384 if (ret) 1385 goto start_rxq_error; 1386 } 1387 1388 /* Configure VLAN Strip */ 1389 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip); 1390 1391 /* Configure TX queues */ 1392 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) { 1393 ret = nicvf_start_tx_queue(dev, qidx); 1394 if (ret) 1395 goto start_txq_error; 1396 } 1397 1398 /* Configure CPI algorithm */ 1399 ret = nicvf_configure_cpi(dev); 1400 if (ret) 1401 goto start_txq_error; 1402 1403 /* Configure RSS */ 1404 ret = nicvf_configure_rss(dev); 1405 if (ret) 1406 goto qset_rss_error; 1407 1408 /* Configure loopback */ 1409 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1410 if (ret) { 1411 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1412 goto qset_rss_error; 1413 } 1414 1415 /* Reset all statistics counters attached to this port */ 1416 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1417 if (ret) { 1418 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1419 goto qset_rss_error; 1420 } 1421 1422 /* Setup scatter mode if needed by jumbo */ 1423 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1424 2 * VLAN_TAG_SIZE > buffsz) 1425 dev->data->scattered_rx = 1; 1426 if (rx_conf->enable_scatter) 1427 dev->data->scattered_rx = 1; 1428 1429 /* Setup MTU based on max_rx_pkt_len or default */ 1430 mtu = dev->data->dev_conf.rxmode.jumbo_frame ? 1431 dev->data->dev_conf.rxmode.max_rx_pkt_len 1432 - ETHER_HDR_LEN - ETHER_CRC_LEN 1433 : ETHER_MTU; 1434 1435 if (nicvf_dev_set_mtu(dev, mtu)) { 1436 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1437 return -EBUSY; 1438 } 1439 1440 /* Configure callbacks based on scatter mode */ 1441 nicvf_set_tx_function(dev); 1442 nicvf_set_rx_function(dev); 1443 1444 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1445 nicvf_mbox_cfg_done(nic); 1446 return 0; 1447 1448 qset_rss_error: 1449 nicvf_rss_term(nic); 1450 start_txq_error: 1451 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) 1452 nicvf_stop_tx_queue(dev, qidx); 1453 start_rxq_error: 1454 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) 1455 nicvf_stop_rx_queue(dev, qidx); 1456 qset_rbdr_reclaim: 1457 nicvf_qset_rbdr_reclaim(nic, 0); 1458 nicvf_rbdr_release_mbufs(dev, nic); 1459 qset_rbdr_free: 1460 if (nic->rbdr) { 1461 rte_free(nic->rbdr); 1462 nic->rbdr = NULL; 1463 } 1464 qset_reclaim: 1465 nicvf_qset_reclaim(nic); 1466 return ret; 1467 } 1468 1469 static void 1470 nicvf_dev_stop(struct rte_eth_dev *dev) 1471 { 1472 int ret; 1473 uint16_t qidx; 1474 struct nicvf *nic = nicvf_pmd_priv(dev); 1475 1476 PMD_INIT_FUNC_TRACE(); 1477 1478 /* Let PF make the BGX's RX and TX switches to OFF position */ 1479 nicvf_mbox_shutdown(nic); 1480 1481 /* Disable loopback */ 1482 ret = nicvf_loopback_config(nic, 0); 1483 if (ret) 1484 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1485 1486 /* Disable VLAN Strip */ 1487 nicvf_vlan_hw_strip(nic, 0); 1488 1489 /* Reclaim sq */ 1490 for (qidx = 0; qidx < dev->data->nb_tx_queues; qidx++) 1491 nicvf_stop_tx_queue(dev, qidx); 1492 1493 /* Reclaim rq */ 1494 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) 1495 nicvf_stop_rx_queue(dev, qidx); 1496 1497 /* Reclaim RBDR */ 1498 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1499 if (ret) 1500 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1501 1502 /* Move all charged buffers in RBDR back to pool */ 1503 if (nic->rbdr != NULL) 1504 nicvf_rbdr_release_mbufs(dev, nic); 1505 1506 /* Reclaim CPI configuration */ 1507 if (!nic->sqs_mode) { 1508 ret = nicvf_mbox_config_cpi(nic, 0); 1509 if (ret) 1510 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config"); 1511 } 1512 1513 /* Disable qset */ 1514 ret = nicvf_qset_config(nic); 1515 if (ret) 1516 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1517 1518 /* Disable all interrupts */ 1519 nicvf_disable_all_interrupts(nic); 1520 1521 /* Free RBDR SW structure */ 1522 if (nic->rbdr) { 1523 rte_free(nic->rbdr); 1524 nic->rbdr = NULL; 1525 } 1526 } 1527 1528 static void 1529 nicvf_dev_close(struct rte_eth_dev *dev) 1530 { 1531 PMD_INIT_FUNC_TRACE(); 1532 1533 nicvf_dev_stop(dev); 1534 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1535 } 1536 1537 static int 1538 nicvf_dev_configure(struct rte_eth_dev *dev) 1539 { 1540 struct rte_eth_conf *conf = &dev->data->dev_conf; 1541 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1542 struct rte_eth_txmode *txmode = &conf->txmode; 1543 struct nicvf *nic = nicvf_pmd_priv(dev); 1544 1545 PMD_INIT_FUNC_TRACE(); 1546 1547 if (!rte_eal_has_hugepages()) { 1548 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1549 return -EINVAL; 1550 } 1551 1552 if (txmode->mq_mode) { 1553 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1554 return -EINVAL; 1555 } 1556 1557 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1558 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1559 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1560 return -EINVAL; 1561 } 1562 1563 if (!rxmode->hw_strip_crc) { 1564 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip"); 1565 rxmode->hw_strip_crc = 1; 1566 } 1567 1568 if (rxmode->hw_ip_checksum) { 1569 PMD_INIT_LOG(NOTICE, "Rxcksum not supported"); 1570 rxmode->hw_ip_checksum = 0; 1571 } 1572 1573 if (rxmode->split_hdr_size) { 1574 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1575 return -EINVAL; 1576 } 1577 1578 if (rxmode->hw_vlan_filter) { 1579 PMD_INIT_LOG(INFO, "VLAN filter not supported"); 1580 return -EINVAL; 1581 } 1582 1583 if (rxmode->hw_vlan_extend) { 1584 PMD_INIT_LOG(INFO, "VLAN extended not supported"); 1585 return -EINVAL; 1586 } 1587 1588 if (rxmode->enable_lro) { 1589 PMD_INIT_LOG(INFO, "LRO not supported"); 1590 return -EINVAL; 1591 } 1592 1593 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1594 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1595 return -EINVAL; 1596 } 1597 1598 if (conf->dcb_capability_en) { 1599 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1600 return -EINVAL; 1601 } 1602 1603 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1604 PMD_INIT_LOG(INFO, "Flow director not supported"); 1605 return -EINVAL; 1606 } 1607 1608 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1609 dev->data->port_id, nicvf_hw_cap(nic)); 1610 1611 return 0; 1612 } 1613 1614 /* Initialize and register driver with DPDK Application */ 1615 static const struct eth_dev_ops nicvf_eth_dev_ops = { 1616 .dev_configure = nicvf_dev_configure, 1617 .dev_start = nicvf_dev_start, 1618 .dev_stop = nicvf_dev_stop, 1619 .link_update = nicvf_dev_link_update, 1620 .dev_close = nicvf_dev_close, 1621 .stats_get = nicvf_dev_stats_get, 1622 .stats_reset = nicvf_dev_stats_reset, 1623 .promiscuous_enable = nicvf_dev_promisc_enable, 1624 .dev_infos_get = nicvf_dev_info_get, 1625 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 1626 .mtu_set = nicvf_dev_set_mtu, 1627 .reta_update = nicvf_dev_reta_update, 1628 .reta_query = nicvf_dev_reta_query, 1629 .rss_hash_update = nicvf_dev_rss_hash_update, 1630 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 1631 .rx_queue_start = nicvf_dev_rx_queue_start, 1632 .rx_queue_stop = nicvf_dev_rx_queue_stop, 1633 .tx_queue_start = nicvf_dev_tx_queue_start, 1634 .tx_queue_stop = nicvf_dev_tx_queue_stop, 1635 .rx_queue_setup = nicvf_dev_rx_queue_setup, 1636 .rx_queue_release = nicvf_dev_rx_queue_release, 1637 .rx_queue_count = nicvf_dev_rx_queue_count, 1638 .tx_queue_setup = nicvf_dev_tx_queue_setup, 1639 .tx_queue_release = nicvf_dev_tx_queue_release, 1640 .get_reg = nicvf_dev_get_regs, 1641 }; 1642 1643 static int 1644 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 1645 { 1646 int ret; 1647 struct rte_pci_device *pci_dev; 1648 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 1649 1650 PMD_INIT_FUNC_TRACE(); 1651 1652 eth_dev->dev_ops = &nicvf_eth_dev_ops; 1653 1654 /* For secondary processes, the primary has done all the work */ 1655 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1656 /* Setup callbacks for secondary process */ 1657 nicvf_set_tx_function(eth_dev); 1658 nicvf_set_rx_function(eth_dev); 1659 return 0; 1660 } 1661 1662 pci_dev = eth_dev->pci_dev; 1663 rte_eth_copy_pci_info(eth_dev, pci_dev); 1664 1665 nic->device_id = pci_dev->id.device_id; 1666 nic->vendor_id = pci_dev->id.vendor_id; 1667 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 1668 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 1669 1670 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 1671 pci_dev->id.vendor_id, pci_dev->id.device_id, 1672 pci_dev->addr.domain, pci_dev->addr.bus, 1673 pci_dev->addr.devid, pci_dev->addr.function); 1674 1675 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 1676 if (!nic->reg_base) { 1677 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 1678 ret = -ENODEV; 1679 goto fail; 1680 } 1681 1682 nicvf_disable_all_interrupts(nic); 1683 1684 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 1685 if (ret) { 1686 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 1687 goto fail; 1688 } 1689 1690 ret = nicvf_mbox_check_pf_ready(nic); 1691 if (ret) { 1692 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 1693 goto alarm_fail; 1694 } else { 1695 PMD_INIT_LOG(INFO, 1696 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 1697 nic->node, nic->vf_id, 1698 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 1699 nic->sqs_mode ? "true" : "false", 1700 nic->loopback_supported ? "true" : "false" 1701 ); 1702 } 1703 1704 if (nic->sqs_mode) { 1705 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching..."); 1706 /* Detach port by returning Positive error number */ 1707 ret = ENOTSUP; 1708 goto alarm_fail; 1709 } 1710 1711 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); 1712 if (eth_dev->data->mac_addrs == NULL) { 1713 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 1714 ret = -ENOMEM; 1715 goto alarm_fail; 1716 } 1717 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr)) 1718 eth_random_addr(&nic->mac_addr[0]); 1719 1720 ether_addr_copy((struct ether_addr *)nic->mac_addr, 1721 ð_dev->data->mac_addrs[0]); 1722 1723 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 1724 if (ret) { 1725 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 1726 goto malloc_fail; 1727 } 1728 1729 ret = nicvf_base_init(nic); 1730 if (ret) { 1731 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 1732 goto malloc_fail; 1733 } 1734 1735 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 1736 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 1737 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 1738 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 1739 1740 return 0; 1741 1742 malloc_fail: 1743 rte_free(eth_dev->data->mac_addrs); 1744 alarm_fail: 1745 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 1746 fail: 1747 return ret; 1748 } 1749 1750 static const struct rte_pci_id pci_id_nicvf_map[] = { 1751 { 1752 .class_id = RTE_CLASS_ANY_ID, 1753 .vendor_id = PCI_VENDOR_ID_CAVIUM, 1754 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 1755 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 1756 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 1757 }, 1758 { 1759 .class_id = RTE_CLASS_ANY_ID, 1760 .vendor_id = PCI_VENDOR_ID_CAVIUM, 1761 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 1762 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 1763 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 1764 }, 1765 { 1766 .class_id = RTE_CLASS_ANY_ID, 1767 .vendor_id = PCI_VENDOR_ID_CAVIUM, 1768 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 1769 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 1770 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 1771 }, 1772 { 1773 .vendor_id = 0, 1774 }, 1775 }; 1776 1777 static struct eth_driver rte_nicvf_pmd = { 1778 .pci_drv = { 1779 .id_table = pci_id_nicvf_map, 1780 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1781 .probe = rte_eth_dev_pci_probe, 1782 .remove = rte_eth_dev_pci_remove, 1783 }, 1784 .eth_dev_init = nicvf_eth_dev_init, 1785 .dev_private_size = sizeof(struct nicvf), 1786 }; 1787 1788 DRIVER_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv); 1789 DRIVER_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 1790