1 /* 2 * BSD LICENSE 3 * 4 * Copyright (C) Cavium, Inc. 2016. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Cavium, Inc nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <assert.h> 34 #include <stdio.h> 35 #include <stdbool.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 #include <sys/queue.h> 44 45 #include <rte_alarm.h> 46 #include <rte_atomic.h> 47 #include <rte_branch_prediction.h> 48 #include <rte_byteorder.h> 49 #include <rte_common.h> 50 #include <rte_cycles.h> 51 #include <rte_debug.h> 52 #include <rte_dev.h> 53 #include <rte_eal.h> 54 #include <rte_ether.h> 55 #include <rte_ethdev.h> 56 #include <rte_ethdev_pci.h> 57 #include <rte_interrupts.h> 58 #include <rte_log.h> 59 #include <rte_memory.h> 60 #include <rte_memzone.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_pci.h> 64 #include <rte_bus_pci.h> 65 #include <rte_tailq.h> 66 67 #include "base/nicvf_plat.h" 68 69 #include "nicvf_ethdev.h" 70 #include "nicvf_rxtx.h" 71 #include "nicvf_svf.h" 72 #include "nicvf_logs.h" 73 74 static void nicvf_dev_stop(struct rte_eth_dev *dev); 75 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 76 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 77 bool cleanup); 78 79 static inline int 80 nicvf_atomic_write_link_status(struct rte_eth_dev *dev, 81 struct rte_eth_link *link) 82 { 83 struct rte_eth_link *dst = &dev->data->dev_link; 84 struct rte_eth_link *src = link; 85 86 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 87 *(uint64_t *)src) == 0) 88 return -1; 89 90 return 0; 91 } 92 93 static inline void 94 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link) 95 { 96 link->link_status = nic->link_up; 97 link->link_duplex = ETH_LINK_AUTONEG; 98 if (nic->duplex == NICVF_HALF_DUPLEX) 99 link->link_duplex = ETH_LINK_HALF_DUPLEX; 100 else if (nic->duplex == NICVF_FULL_DUPLEX) 101 link->link_duplex = ETH_LINK_FULL_DUPLEX; 102 link->link_speed = nic->speed; 103 link->link_autoneg = ETH_LINK_SPEED_AUTONEG; 104 } 105 106 static void 107 nicvf_interrupt(void *arg) 108 { 109 struct rte_eth_dev *dev = arg; 110 struct nicvf *nic = nicvf_pmd_priv(dev); 111 112 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 113 if (dev->data->dev_conf.intr_conf.lsc) 114 nicvf_set_eth_link_status(nic, &dev->data->dev_link); 115 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 116 NULL, NULL); 117 } 118 119 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 120 nicvf_interrupt, dev); 121 } 122 123 static void 124 nicvf_vf_interrupt(void *arg) 125 { 126 struct nicvf *nic = arg; 127 128 nicvf_reg_poll_interrupts(nic); 129 130 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 131 nicvf_vf_interrupt, nic); 132 } 133 134 static int 135 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 136 { 137 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 138 } 139 140 static int 141 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 142 { 143 return rte_eal_alarm_cancel(fn, arg); 144 } 145 146 /* 147 * Return 0 means link status changed, -1 means not changed 148 */ 149 static int 150 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 151 { 152 #define CHECK_INTERVAL 100 /* 100ms */ 153 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 154 struct rte_eth_link link; 155 struct nicvf *nic = nicvf_pmd_priv(dev); 156 int i; 157 158 PMD_INIT_FUNC_TRACE(); 159 160 if (wait_to_complete) { 161 /* rte_eth_link_get() might need to wait up to 9 seconds */ 162 for (i = 0; i < MAX_CHECK_TIME; i++) { 163 memset(&link, 0, sizeof(link)); 164 nicvf_set_eth_link_status(nic, &link); 165 if (link.link_status) 166 break; 167 rte_delay_ms(CHECK_INTERVAL); 168 } 169 } else { 170 memset(&link, 0, sizeof(link)); 171 nicvf_set_eth_link_status(nic, &link); 172 } 173 return nicvf_atomic_write_link_status(dev, &link); 174 } 175 176 static int 177 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 178 { 179 struct nicvf *nic = nicvf_pmd_priv(dev); 180 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 181 size_t i; 182 183 PMD_INIT_FUNC_TRACE(); 184 185 if (frame_size > NIC_HW_MAX_FRS) 186 return -EINVAL; 187 188 if (frame_size < NIC_HW_MIN_FRS) 189 return -EINVAL; 190 191 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 192 193 /* 194 * Refuse mtu that requires the support of scattered packets 195 * when this feature has not been enabled before. 196 */ 197 if (!dev->data->scattered_rx && 198 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 199 return -EINVAL; 200 201 /* check <seg size> * <max_seg> >= max_frame */ 202 if (dev->data->scattered_rx && 203 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 204 return -EINVAL; 205 206 if (frame_size > ETHER_MAX_LEN) 207 dev->data->dev_conf.rxmode.jumbo_frame = 1; 208 else 209 dev->data->dev_conf.rxmode.jumbo_frame = 0; 210 211 if (nicvf_mbox_update_hw_max_frs(nic, frame_size)) 212 return -EINVAL; 213 214 /* Update max frame size */ 215 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size; 216 nic->mtu = mtu; 217 218 for (i = 0; i < nic->sqs_count; i++) 219 nic->snicvf[i]->mtu = mtu; 220 221 return 0; 222 } 223 224 static int 225 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 226 { 227 uint64_t *data = regs->data; 228 struct nicvf *nic = nicvf_pmd_priv(dev); 229 230 if (data == NULL) { 231 regs->length = nicvf_reg_get_count(); 232 regs->width = THUNDERX_REG_BYTES; 233 return 0; 234 } 235 236 /* Support only full register dump */ 237 if ((regs->length == 0) || 238 (regs->length == (uint32_t)nicvf_reg_get_count())) { 239 regs->version = nic->vendor_id << 16 | nic->device_id; 240 nicvf_reg_dump(nic, data); 241 return 0; 242 } 243 return -ENOTSUP; 244 } 245 246 static int 247 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 248 { 249 uint16_t qidx; 250 struct nicvf_hw_rx_qstats rx_qstats; 251 struct nicvf_hw_tx_qstats tx_qstats; 252 struct nicvf_hw_stats port_stats; 253 struct nicvf *nic = nicvf_pmd_priv(dev); 254 uint16_t rx_start, rx_end; 255 uint16_t tx_start, tx_end; 256 size_t i; 257 258 /* RX queue indices for the first VF */ 259 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 260 261 /* Reading per RX ring stats */ 262 for (qidx = rx_start; qidx <= rx_end; qidx++) { 263 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 264 break; 265 266 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 267 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 268 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 269 } 270 271 /* TX queue indices for the first VF */ 272 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 273 274 /* Reading per TX ring stats */ 275 for (qidx = tx_start; qidx <= tx_end; qidx++) { 276 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 277 break; 278 279 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 280 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 281 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 282 } 283 284 for (i = 0; i < nic->sqs_count; i++) { 285 struct nicvf *snic = nic->snicvf[i]; 286 287 if (snic == NULL) 288 break; 289 290 /* RX queue indices for a secondary VF */ 291 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 292 293 /* Reading per RX ring stats */ 294 for (qidx = rx_start; qidx <= rx_end; qidx++) { 295 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 296 break; 297 298 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 299 qidx % MAX_RCV_QUEUES_PER_QS); 300 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 301 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 302 } 303 304 /* TX queue indices for a secondary VF */ 305 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 306 /* Reading per TX ring stats */ 307 for (qidx = tx_start; qidx <= tx_end; qidx++) { 308 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 309 break; 310 311 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 312 qidx % MAX_SND_QUEUES_PER_QS); 313 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 314 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 315 } 316 } 317 318 nicvf_hw_get_stats(nic, &port_stats); 319 stats->ibytes = port_stats.rx_bytes; 320 stats->ipackets = port_stats.rx_ucast_frames; 321 stats->ipackets += port_stats.rx_bcast_frames; 322 stats->ipackets += port_stats.rx_mcast_frames; 323 stats->ierrors = port_stats.rx_l2_errors; 324 stats->imissed = port_stats.rx_drop_red; 325 stats->imissed += port_stats.rx_drop_overrun; 326 stats->imissed += port_stats.rx_drop_bcast; 327 stats->imissed += port_stats.rx_drop_mcast; 328 stats->imissed += port_stats.rx_drop_l3_bcast; 329 stats->imissed += port_stats.rx_drop_l3_mcast; 330 331 stats->obytes = port_stats.tx_bytes_ok; 332 stats->opackets = port_stats.tx_ucast_frames_ok; 333 stats->opackets += port_stats.tx_bcast_frames_ok; 334 stats->opackets += port_stats.tx_mcast_frames_ok; 335 stats->oerrors = port_stats.tx_drops; 336 337 return 0; 338 } 339 340 static const uint32_t * 341 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 342 { 343 size_t copied; 344 static uint32_t ptypes[32]; 345 struct nicvf *nic = nicvf_pmd_priv(dev); 346 static const uint32_t ptypes_common[] = { 347 RTE_PTYPE_L3_IPV4, 348 RTE_PTYPE_L3_IPV4_EXT, 349 RTE_PTYPE_L3_IPV6, 350 RTE_PTYPE_L3_IPV6_EXT, 351 RTE_PTYPE_L4_TCP, 352 RTE_PTYPE_L4_UDP, 353 RTE_PTYPE_L4_FRAG, 354 }; 355 static const uint32_t ptypes_tunnel[] = { 356 RTE_PTYPE_TUNNEL_GRE, 357 RTE_PTYPE_TUNNEL_GENEVE, 358 RTE_PTYPE_TUNNEL_VXLAN, 359 RTE_PTYPE_TUNNEL_NVGRE, 360 }; 361 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 362 363 copied = sizeof(ptypes_common); 364 memcpy(ptypes, ptypes_common, copied); 365 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 366 memcpy((char *)ptypes + copied, ptypes_tunnel, 367 sizeof(ptypes_tunnel)); 368 copied += sizeof(ptypes_tunnel); 369 } 370 371 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 372 if (dev->rx_pkt_burst == nicvf_recv_pkts || 373 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg) 374 return ptypes; 375 376 return NULL; 377 } 378 379 static void 380 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 381 { 382 int i; 383 uint16_t rxqs = 0, txqs = 0; 384 struct nicvf *nic = nicvf_pmd_priv(dev); 385 uint16_t rx_start, rx_end; 386 uint16_t tx_start, tx_end; 387 388 /* Reset all primary nic counters */ 389 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 390 for (i = rx_start; i <= rx_end; i++) 391 rxqs |= (0x3 << (i * 2)); 392 393 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 394 for (i = tx_start; i <= tx_end; i++) 395 txqs |= (0x3 << (i * 2)); 396 397 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 398 399 /* Reset secondary nic queue counters */ 400 for (i = 0; i < nic->sqs_count; i++) { 401 struct nicvf *snic = nic->snicvf[i]; 402 if (snic == NULL) 403 break; 404 405 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 406 for (i = rx_start; i <= rx_end; i++) 407 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 408 409 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 410 for (i = tx_start; i <= tx_end; i++) 411 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 412 413 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 414 } 415 } 416 417 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 418 static void 419 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 420 { 421 } 422 423 static inline uint64_t 424 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 425 { 426 uint64_t nic_rss = 0; 427 428 if (ethdev_rss & ETH_RSS_IPV4) 429 nic_rss |= RSS_IP_ENA; 430 431 if (ethdev_rss & ETH_RSS_IPV6) 432 nic_rss |= RSS_IP_ENA; 433 434 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 435 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 436 437 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 438 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 439 440 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 441 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 442 443 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 444 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 445 446 if (ethdev_rss & ETH_RSS_PORT) 447 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 448 449 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 450 if (ethdev_rss & ETH_RSS_VXLAN) 451 nic_rss |= RSS_TUN_VXLAN_ENA; 452 453 if (ethdev_rss & ETH_RSS_GENEVE) 454 nic_rss |= RSS_TUN_GENEVE_ENA; 455 456 if (ethdev_rss & ETH_RSS_NVGRE) 457 nic_rss |= RSS_TUN_NVGRE_ENA; 458 } 459 460 return nic_rss; 461 } 462 463 static inline uint64_t 464 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 465 { 466 uint64_t ethdev_rss = 0; 467 468 if (nic_rss & RSS_IP_ENA) 469 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 470 471 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 472 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 473 ETH_RSS_NONFRAG_IPV6_TCP); 474 475 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 476 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 477 ETH_RSS_NONFRAG_IPV6_UDP); 478 479 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 480 ethdev_rss |= ETH_RSS_PORT; 481 482 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 483 if (nic_rss & RSS_TUN_VXLAN_ENA) 484 ethdev_rss |= ETH_RSS_VXLAN; 485 486 if (nic_rss & RSS_TUN_GENEVE_ENA) 487 ethdev_rss |= ETH_RSS_GENEVE; 488 489 if (nic_rss & RSS_TUN_NVGRE_ENA) 490 ethdev_rss |= ETH_RSS_NVGRE; 491 } 492 return ethdev_rss; 493 } 494 495 static int 496 nicvf_dev_reta_query(struct rte_eth_dev *dev, 497 struct rte_eth_rss_reta_entry64 *reta_conf, 498 uint16_t reta_size) 499 { 500 struct nicvf *nic = nicvf_pmd_priv(dev); 501 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 502 int ret, i, j; 503 504 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 505 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 506 "(%d) doesn't match the number hardware can supported " 507 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 508 return -EINVAL; 509 } 510 511 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 512 if (ret) 513 return ret; 514 515 /* Copy RETA table */ 516 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 517 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 518 if ((reta_conf[i].mask >> j) & 0x01) 519 reta_conf[i].reta[j] = tbl[j]; 520 } 521 522 return 0; 523 } 524 525 static int 526 nicvf_dev_reta_update(struct rte_eth_dev *dev, 527 struct rte_eth_rss_reta_entry64 *reta_conf, 528 uint16_t reta_size) 529 { 530 struct nicvf *nic = nicvf_pmd_priv(dev); 531 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 532 int ret, i, j; 533 534 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 535 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 536 "(%d) doesn't match the number hardware can supported " 537 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 538 return -EINVAL; 539 } 540 541 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 542 if (ret) 543 return ret; 544 545 /* Copy RETA table */ 546 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 547 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 548 if ((reta_conf[i].mask >> j) & 0x01) 549 tbl[j] = reta_conf[i].reta[j]; 550 } 551 552 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 553 } 554 555 static int 556 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 557 struct rte_eth_rss_conf *rss_conf) 558 { 559 struct nicvf *nic = nicvf_pmd_priv(dev); 560 561 if (rss_conf->rss_key) 562 nicvf_rss_get_key(nic, rss_conf->rss_key); 563 564 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 565 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 566 return 0; 567 } 568 569 static int 570 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 571 struct rte_eth_rss_conf *rss_conf) 572 { 573 struct nicvf *nic = nicvf_pmd_priv(dev); 574 uint64_t nic_rss; 575 576 if (rss_conf->rss_key && 577 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 578 RTE_LOG(ERR, PMD, "Hash key size mismatch %d", 579 rss_conf->rss_key_len); 580 return -EINVAL; 581 } 582 583 if (rss_conf->rss_key) 584 nicvf_rss_set_key(nic, rss_conf->rss_key); 585 586 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 587 nicvf_rss_set_cfg(nic, nic_rss); 588 return 0; 589 } 590 591 static int 592 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 593 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 594 { 595 const struct rte_memzone *rz; 596 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 597 598 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 599 nicvf_netdev_qidx(nic, qidx), ring_size, 600 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 601 if (rz == NULL) { 602 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 603 return -ENOMEM; 604 } 605 606 memset(rz->addr, 0, ring_size); 607 608 rxq->phys = rz->iova; 609 rxq->desc = rz->addr; 610 rxq->qlen_mask = desc_cnt - 1; 611 612 return 0; 613 } 614 615 static int 616 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 617 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 618 { 619 const struct rte_memzone *rz; 620 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 621 622 rz = rte_eth_dma_zone_reserve(dev, "sq", 623 nicvf_netdev_qidx(nic, qidx), ring_size, 624 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 625 if (rz == NULL) { 626 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 627 return -ENOMEM; 628 } 629 630 memset(rz->addr, 0, ring_size); 631 632 sq->phys = rz->iova; 633 sq->desc = rz->addr; 634 sq->qlen_mask = desc_cnt - 1; 635 636 return 0; 637 } 638 639 static int 640 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 641 uint32_t desc_cnt, uint32_t buffsz) 642 { 643 struct nicvf_rbdr *rbdr; 644 const struct rte_memzone *rz; 645 uint32_t ring_size; 646 647 assert(nic->rbdr == NULL); 648 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 649 RTE_CACHE_LINE_SIZE, nic->node); 650 if (rbdr == NULL) { 651 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 652 return -ENOMEM; 653 } 654 655 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 656 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 657 nicvf_netdev_qidx(nic, 0), ring_size, 658 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 659 if (rz == NULL) { 660 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 661 return -ENOMEM; 662 } 663 664 memset(rz->addr, 0, ring_size); 665 666 rbdr->phys = rz->iova; 667 rbdr->tail = 0; 668 rbdr->next_tail = 0; 669 rbdr->desc = rz->addr; 670 rbdr->buffsz = buffsz; 671 rbdr->qlen_mask = desc_cnt - 1; 672 rbdr->rbdr_status = 673 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 674 rbdr->rbdr_door = 675 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 676 677 nic->rbdr = rbdr; 678 return 0; 679 } 680 681 static void 682 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 683 nicvf_iova_addr_t phy) 684 { 685 uint16_t qidx; 686 void *obj; 687 struct nicvf_rxq *rxq; 688 uint16_t rx_start, rx_end; 689 690 /* Get queue ranges for this VF */ 691 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 692 693 for (qidx = rx_start; qidx <= rx_end; qidx++) { 694 rxq = dev->data->rx_queues[qidx]; 695 if (rxq->precharge_cnt) { 696 obj = (void *)nicvf_mbuff_phy2virt(phy, 697 rxq->mbuf_phys_off); 698 rte_mempool_put(rxq->pool, obj); 699 rxq->precharge_cnt--; 700 break; 701 } 702 } 703 } 704 705 static inline void 706 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 707 { 708 uint32_t qlen_mask, head; 709 struct rbdr_entry_t *entry; 710 struct nicvf_rbdr *rbdr = nic->rbdr; 711 712 qlen_mask = rbdr->qlen_mask; 713 head = rbdr->head; 714 while (head != rbdr->tail) { 715 entry = rbdr->desc + head; 716 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 717 head++; 718 head = head & qlen_mask; 719 } 720 } 721 722 static inline void 723 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 724 { 725 uint32_t head; 726 727 head = txq->head; 728 while (head != txq->tail) { 729 if (txq->txbuffs[head]) { 730 rte_pktmbuf_free_seg(txq->txbuffs[head]); 731 txq->txbuffs[head] = NULL; 732 } 733 head++; 734 head = head & txq->qlen_mask; 735 } 736 } 737 738 static void 739 nicvf_tx_queue_reset(struct nicvf_txq *txq) 740 { 741 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 742 743 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 744 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 745 txq->tail = 0; 746 txq->head = 0; 747 txq->xmit_bufs = 0; 748 } 749 750 static inline int 751 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 752 uint16_t qidx) 753 { 754 struct nicvf_txq *txq; 755 int ret; 756 757 assert(qidx < MAX_SND_QUEUES_PER_QS); 758 759 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 760 RTE_ETH_QUEUE_STATE_STARTED) 761 return 0; 762 763 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 764 txq->pool = NULL; 765 ret = nicvf_qset_sq_config(nic, qidx, txq); 766 if (ret) { 767 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 768 nic->vf_id, qidx, ret); 769 goto config_sq_error; 770 } 771 772 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 773 RTE_ETH_QUEUE_STATE_STARTED; 774 return ret; 775 776 config_sq_error: 777 nicvf_qset_sq_reclaim(nic, qidx); 778 return ret; 779 } 780 781 static inline int 782 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 783 uint16_t qidx) 784 { 785 struct nicvf_txq *txq; 786 int ret; 787 788 assert(qidx < MAX_SND_QUEUES_PER_QS); 789 790 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 791 RTE_ETH_QUEUE_STATE_STOPPED) 792 return 0; 793 794 ret = nicvf_qset_sq_reclaim(nic, qidx); 795 if (ret) 796 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 797 nic->vf_id, qidx, ret); 798 799 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 800 nicvf_tx_queue_release_mbufs(txq); 801 nicvf_tx_queue_reset(txq); 802 803 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 804 RTE_ETH_QUEUE_STATE_STOPPED; 805 return ret; 806 } 807 808 static inline int 809 nicvf_configure_cpi(struct rte_eth_dev *dev) 810 { 811 struct nicvf *nic = nicvf_pmd_priv(dev); 812 uint16_t qidx, qcnt; 813 int ret; 814 815 /* Count started rx queues */ 816 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 817 if (dev->data->rx_queue_state[qidx] == 818 RTE_ETH_QUEUE_STATE_STARTED) 819 qcnt++; 820 821 nic->cpi_alg = CPI_ALG_NONE; 822 ret = nicvf_mbox_config_cpi(nic, qcnt); 823 if (ret) 824 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 825 826 return ret; 827 } 828 829 static inline int 830 nicvf_configure_rss(struct rte_eth_dev *dev) 831 { 832 struct nicvf *nic = nicvf_pmd_priv(dev); 833 uint64_t rsshf; 834 int ret = -EINVAL; 835 836 rsshf = nicvf_rss_ethdev_to_nic(nic, 837 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 838 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 839 dev->data->dev_conf.rxmode.mq_mode, 840 dev->data->nb_rx_queues, 841 dev->data->dev_conf.lpbk_mode, rsshf); 842 843 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 844 ret = nicvf_rss_term(nic); 845 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 846 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 847 if (ret) 848 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 849 850 return ret; 851 } 852 853 static int 854 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 855 { 856 struct nicvf *nic = nicvf_pmd_priv(dev); 857 unsigned int idx, qmap_size; 858 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 859 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 860 861 if (nic->cpi_alg != CPI_ALG_NONE) 862 return -EINVAL; 863 864 /* Prepare queue map */ 865 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 866 if (dev->data->rx_queue_state[idx] == 867 RTE_ETH_QUEUE_STATE_STARTED) 868 qmap[qmap_size++] = idx; 869 } 870 871 /* Update default RSS RETA */ 872 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 873 default_reta[idx] = qmap[idx % qmap_size]; 874 875 return nicvf_rss_reta_update(nic, default_reta, 876 NIC_MAX_RSS_IDR_TBL_SIZE); 877 } 878 879 static void 880 nicvf_dev_tx_queue_release(void *sq) 881 { 882 struct nicvf_txq *txq; 883 884 PMD_INIT_FUNC_TRACE(); 885 886 txq = (struct nicvf_txq *)sq; 887 if (txq) { 888 if (txq->txbuffs != NULL) { 889 nicvf_tx_queue_release_mbufs(txq); 890 rte_free(txq->txbuffs); 891 txq->txbuffs = NULL; 892 } 893 rte_free(txq); 894 } 895 } 896 897 static void 898 nicvf_set_tx_function(struct rte_eth_dev *dev) 899 { 900 struct nicvf_txq *txq; 901 size_t i; 902 bool multiseg = false; 903 904 for (i = 0; i < dev->data->nb_tx_queues; i++) { 905 txq = dev->data->tx_queues[i]; 906 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) { 907 multiseg = true; 908 break; 909 } 910 } 911 912 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 913 if (multiseg) { 914 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 915 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 916 } else { 917 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 918 dev->tx_pkt_burst = nicvf_xmit_pkts; 919 } 920 921 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 922 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 923 else 924 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 925 } 926 927 static void 928 nicvf_set_rx_function(struct rte_eth_dev *dev) 929 { 930 if (dev->data->scattered_rx) { 931 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback"); 932 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg; 933 } else { 934 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback"); 935 dev->rx_pkt_burst = nicvf_recv_pkts; 936 } 937 } 938 939 static int 940 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 941 uint16_t nb_desc, unsigned int socket_id, 942 const struct rte_eth_txconf *tx_conf) 943 { 944 uint16_t tx_free_thresh; 945 uint8_t is_single_pool; 946 struct nicvf_txq *txq; 947 struct nicvf *nic = nicvf_pmd_priv(dev); 948 949 PMD_INIT_FUNC_TRACE(); 950 951 if (qidx >= MAX_SND_QUEUES_PER_QS) 952 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 953 954 qidx = qidx % MAX_SND_QUEUES_PER_QS; 955 956 /* Socket id check */ 957 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 958 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 959 socket_id, nic->node); 960 961 /* Tx deferred start is not supported */ 962 if (tx_conf->tx_deferred_start) { 963 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 964 return -EINVAL; 965 } 966 967 /* Roundup nb_desc to available qsize and validate max number of desc */ 968 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 969 if (nb_desc == 0) { 970 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 971 return -EINVAL; 972 } 973 974 /* Validate tx_free_thresh */ 975 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 976 tx_conf->tx_free_thresh : 977 NICVF_DEFAULT_TX_FREE_THRESH); 978 979 if (tx_free_thresh > (nb_desc) || 980 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 981 PMD_INIT_LOG(ERR, 982 "tx_free_thresh must be less than the number of TX " 983 "descriptors. (tx_free_thresh=%u port=%d " 984 "queue=%d)", (unsigned int)tx_free_thresh, 985 (int)dev->data->port_id, (int)qidx); 986 return -EINVAL; 987 } 988 989 /* Free memory prior to re-allocation if needed. */ 990 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 991 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 992 nicvf_netdev_qidx(nic, qidx)); 993 nicvf_dev_tx_queue_release( 994 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]); 995 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 996 } 997 998 /* Allocating tx queue data structure */ 999 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 1000 RTE_CACHE_LINE_SIZE, nic->node); 1001 if (txq == NULL) { 1002 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 1003 nicvf_netdev_qidx(nic, qidx)); 1004 return -ENOMEM; 1005 } 1006 1007 txq->nic = nic; 1008 txq->queue_id = qidx; 1009 txq->tx_free_thresh = tx_free_thresh; 1010 txq->txq_flags = tx_conf->txq_flags; 1011 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1012 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1013 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT && 1014 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP); 1015 1016 /* Choose optimum free threshold value for multipool case */ 1017 if (!is_single_pool) { 1018 txq->tx_free_thresh = (uint16_t) 1019 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1020 NICVF_TX_FREE_MPOOL_THRESH : 1021 tx_conf->tx_free_thresh); 1022 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1023 } else { 1024 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1025 } 1026 1027 /* Allocate software ring */ 1028 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1029 nb_desc * sizeof(struct rte_mbuf *), 1030 RTE_CACHE_LINE_SIZE, nic->node); 1031 1032 if (txq->txbuffs == NULL) { 1033 nicvf_dev_tx_queue_release(txq); 1034 return -ENOMEM; 1035 } 1036 1037 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1038 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1039 nicvf_dev_tx_queue_release(txq); 1040 return -ENOMEM; 1041 } 1042 1043 nicvf_tx_queue_reset(txq); 1044 1045 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64, 1046 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1047 txq->phys); 1048 1049 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1050 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1051 RTE_ETH_QUEUE_STATE_STOPPED; 1052 return 0; 1053 } 1054 1055 static inline void 1056 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1057 { 1058 uint32_t rxq_cnt; 1059 uint32_t nb_pkts, released_pkts = 0; 1060 uint32_t refill_cnt = 0; 1061 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1062 1063 if (dev->rx_pkt_burst == NULL) 1064 return; 1065 1066 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, 1067 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) { 1068 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1069 NICVF_MAX_RX_FREE_THRESH); 1070 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1071 while (nb_pkts) { 1072 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1073 released_pkts++; 1074 } 1075 } 1076 1077 1078 refill_cnt += nicvf_dev_rbdr_refill(dev, 1079 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1080 1081 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1082 released_pkts, refill_cnt); 1083 } 1084 1085 static void 1086 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1087 { 1088 rxq->head = 0; 1089 rxq->available_space = 0; 1090 rxq->recv_buffers = 0; 1091 } 1092 1093 static inline int 1094 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1095 uint16_t qidx) 1096 { 1097 struct nicvf_rxq *rxq; 1098 int ret; 1099 1100 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1101 1102 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1103 RTE_ETH_QUEUE_STATE_STARTED) 1104 return 0; 1105 1106 /* Update rbdr pointer to all rxq */ 1107 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1108 rxq->shared_rbdr = nic->rbdr; 1109 1110 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1111 if (ret) { 1112 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1113 nic->vf_id, qidx, ret); 1114 goto config_rq_error; 1115 } 1116 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1117 if (ret) { 1118 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1119 nic->vf_id, qidx, ret); 1120 goto config_cq_error; 1121 } 1122 1123 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1124 RTE_ETH_QUEUE_STATE_STARTED; 1125 return 0; 1126 1127 config_cq_error: 1128 nicvf_qset_cq_reclaim(nic, qidx); 1129 config_rq_error: 1130 nicvf_qset_rq_reclaim(nic, qidx); 1131 return ret; 1132 } 1133 1134 static inline int 1135 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1136 uint16_t qidx) 1137 { 1138 struct nicvf_rxq *rxq; 1139 int ret, other_error; 1140 1141 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1142 RTE_ETH_QUEUE_STATE_STOPPED) 1143 return 0; 1144 1145 ret = nicvf_qset_rq_reclaim(nic, qidx); 1146 if (ret) 1147 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1148 nic->vf_id, qidx, ret); 1149 1150 other_error = ret; 1151 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1152 nicvf_rx_queue_release_mbufs(dev, rxq); 1153 nicvf_rx_queue_reset(rxq); 1154 1155 ret = nicvf_qset_cq_reclaim(nic, qidx); 1156 if (ret) 1157 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1158 nic->vf_id, qidx, ret); 1159 1160 other_error |= ret; 1161 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1162 RTE_ETH_QUEUE_STATE_STOPPED; 1163 return other_error; 1164 } 1165 1166 static void 1167 nicvf_dev_rx_queue_release(void *rx_queue) 1168 { 1169 PMD_INIT_FUNC_TRACE(); 1170 1171 rte_free(rx_queue); 1172 } 1173 1174 static int 1175 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1176 { 1177 struct nicvf *nic = nicvf_pmd_priv(dev); 1178 int ret; 1179 1180 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1181 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1182 1183 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1184 1185 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1186 if (ret) 1187 return ret; 1188 1189 ret = nicvf_configure_cpi(dev); 1190 if (ret) 1191 return ret; 1192 1193 return nicvf_configure_rss_reta(dev); 1194 } 1195 1196 static int 1197 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1198 { 1199 int ret; 1200 struct nicvf *nic = nicvf_pmd_priv(dev); 1201 1202 if (qidx >= MAX_SND_QUEUES_PER_QS) 1203 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1204 1205 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1206 1207 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1208 ret |= nicvf_configure_cpi(dev); 1209 ret |= nicvf_configure_rss_reta(dev); 1210 return ret; 1211 } 1212 1213 static int 1214 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1215 { 1216 struct nicvf *nic = nicvf_pmd_priv(dev); 1217 1218 if (qidx >= MAX_SND_QUEUES_PER_QS) 1219 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1220 1221 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1222 1223 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1224 } 1225 1226 static int 1227 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1228 { 1229 struct nicvf *nic = nicvf_pmd_priv(dev); 1230 1231 if (qidx >= MAX_SND_QUEUES_PER_QS) 1232 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1233 1234 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1235 1236 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1237 } 1238 1239 static inline void 1240 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1241 { 1242 uintptr_t p; 1243 struct rte_mbuf mb_def; 1244 1245 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1246 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1247 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1248 offsetof(struct rte_mbuf, data_off) != 2); 1249 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1250 offsetof(struct rte_mbuf, data_off) != 4); 1251 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1252 offsetof(struct rte_mbuf, data_off) != 6); 1253 mb_def.nb_segs = 1; 1254 mb_def.data_off = RTE_PKTMBUF_HEADROOM; 1255 mb_def.port = rxq->port_id; 1256 rte_mbuf_refcnt_set(&mb_def, 1); 1257 1258 /* Prevent compiler reordering: rearm_data covers previous fields */ 1259 rte_compiler_barrier(); 1260 p = (uintptr_t)&mb_def.rearm_data; 1261 rxq->mbuf_initializer.value = *(uint64_t *)p; 1262 } 1263 1264 static int 1265 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1266 uint16_t nb_desc, unsigned int socket_id, 1267 const struct rte_eth_rxconf *rx_conf, 1268 struct rte_mempool *mp) 1269 { 1270 uint16_t rx_free_thresh; 1271 struct nicvf_rxq *rxq; 1272 struct nicvf *nic = nicvf_pmd_priv(dev); 1273 1274 PMD_INIT_FUNC_TRACE(); 1275 1276 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1277 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1278 1279 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1280 1281 /* Socket id check */ 1282 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1283 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1284 socket_id, nic->node); 1285 1286 /* Mempool memory must be contiguous, so must be one memory segment*/ 1287 if (mp->nb_mem_chunks != 1) { 1288 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1289 return -EINVAL; 1290 } 1291 1292 /* Mempool memory must be physically contiguous */ 1293 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) { 1294 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1295 return -EINVAL; 1296 } 1297 1298 /* Rx deferred start is not supported */ 1299 if (rx_conf->rx_deferred_start) { 1300 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1301 return -EINVAL; 1302 } 1303 1304 /* Roundup nb_desc to available qsize and validate max number of desc */ 1305 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1306 if (nb_desc == 0) { 1307 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1308 return -EINVAL; 1309 } 1310 1311 /* Check rx_free_thresh upper bound */ 1312 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1313 rx_conf->rx_free_thresh : 1314 NICVF_DEFAULT_RX_FREE_THRESH); 1315 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1316 rx_free_thresh >= nb_desc * .75) { 1317 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1318 rx_free_thresh); 1319 return -EINVAL; 1320 } 1321 1322 /* Free memory prior to re-allocation if needed */ 1323 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1324 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1325 nicvf_netdev_qidx(nic, qidx)); 1326 nicvf_dev_rx_queue_release( 1327 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]); 1328 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1329 } 1330 1331 /* Allocate rxq memory */ 1332 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1333 RTE_CACHE_LINE_SIZE, nic->node); 1334 if (rxq == NULL) { 1335 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1336 nicvf_netdev_qidx(nic, qidx)); 1337 return -ENOMEM; 1338 } 1339 1340 rxq->nic = nic; 1341 rxq->pool = mp; 1342 rxq->queue_id = qidx; 1343 rxq->port_id = dev->data->port_id; 1344 rxq->rx_free_thresh = rx_free_thresh; 1345 rxq->rx_drop_en = rx_conf->rx_drop_en; 1346 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1347 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1348 rxq->precharge_cnt = 0; 1349 1350 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1351 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1352 else 1353 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1354 1355 nicvf_rxq_mbuf_setup(rxq); 1356 1357 /* Alloc completion queue */ 1358 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1359 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1360 nicvf_dev_rx_queue_release(rxq); 1361 return -ENOMEM; 1362 } 1363 1364 nicvf_rx_queue_reset(rxq); 1365 1366 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64, 1367 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1368 rte_mempool_avail_count(mp), rxq->phys); 1369 1370 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1371 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1372 RTE_ETH_QUEUE_STATE_STOPPED; 1373 return 0; 1374 } 1375 1376 static void 1377 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1378 { 1379 struct nicvf *nic = nicvf_pmd_priv(dev); 1380 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1381 1382 PMD_INIT_FUNC_TRACE(); 1383 1384 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1385 1386 /* Autonegotiation may be disabled */ 1387 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 1388 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 1389 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 1390 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1391 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 1392 1393 dev_info->min_rx_bufsize = ETHER_MIN_MTU; 1394 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS; 1395 dev_info->max_rx_queues = 1396 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1397 dev_info->max_tx_queues = 1398 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1399 dev_info->max_mac_addrs = 1; 1400 dev_info->max_vfs = pci_dev->max_vfs; 1401 1402 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP; 1403 dev_info->tx_offload_capa = 1404 DEV_TX_OFFLOAD_IPV4_CKSUM | 1405 DEV_TX_OFFLOAD_UDP_CKSUM | 1406 DEV_TX_OFFLOAD_TCP_CKSUM | 1407 DEV_TX_OFFLOAD_TCP_TSO | 1408 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 1409 1410 dev_info->reta_size = nic->rss_info.rss_size; 1411 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1412 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1413 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1414 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1415 1416 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1417 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1418 .rx_drop_en = 0, 1419 }; 1420 1421 dev_info->default_txconf = (struct rte_eth_txconf) { 1422 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1423 .txq_flags = 1424 ETH_TXQ_FLAGS_NOMULTSEGS | 1425 ETH_TXQ_FLAGS_NOREFCOUNT | 1426 ETH_TXQ_FLAGS_NOMULTMEMP | 1427 ETH_TXQ_FLAGS_NOVLANOFFL | 1428 ETH_TXQ_FLAGS_NOXSUMSCTP, 1429 }; 1430 } 1431 1432 static nicvf_iova_addr_t 1433 rbdr_rte_mempool_get(void *dev, void *opaque) 1434 { 1435 uint16_t qidx; 1436 uintptr_t mbuf; 1437 struct nicvf_rxq *rxq; 1438 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1439 struct nicvf *nic = (struct nicvf *)opaque; 1440 uint16_t rx_start, rx_end; 1441 1442 /* Get queue ranges for this VF */ 1443 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1444 1445 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1446 rxq = eth_dev->data->rx_queues[qidx]; 1447 /* Maintain equal buffer count across all pools */ 1448 if (rxq->precharge_cnt >= rxq->qlen_mask) 1449 continue; 1450 rxq->precharge_cnt++; 1451 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1452 if (mbuf) 1453 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1454 } 1455 return 0; 1456 } 1457 1458 static int 1459 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1460 { 1461 int ret; 1462 uint16_t qidx, data_off; 1463 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1464 uint64_t mbuf_phys_off = 0; 1465 struct nicvf_rxq *rxq; 1466 struct rte_mbuf *mbuf; 1467 uint16_t rx_start, rx_end; 1468 uint16_t tx_start, tx_end; 1469 1470 PMD_INIT_FUNC_TRACE(); 1471 1472 /* Userspace process exited without proper shutdown in last run */ 1473 if (nicvf_qset_rbdr_active(nic, 0)) 1474 nicvf_vf_stop(dev, nic, false); 1475 1476 /* Get queue ranges for this VF */ 1477 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1478 1479 /* 1480 * Thunderx nicvf PMD can support more than one pool per port only when 1481 * 1) Data payload size is same across all the pools in given port 1482 * AND 1483 * 2) All mbuffs in the pools are from the same hugepage 1484 * AND 1485 * 3) Mbuff metadata size is same across all the pools in given port 1486 * 1487 * This is to support existing application that uses multiple pool/port. 1488 * But, the purpose of using multipool for QoS will not be addressed. 1489 * 1490 */ 1491 1492 /* Validate mempool attributes */ 1493 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1494 rxq = dev->data->rx_queues[qidx]; 1495 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1496 mbuf = rte_pktmbuf_alloc(rxq->pool); 1497 if (mbuf == NULL) { 1498 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1499 "pool=%s", 1500 nic->vf_id, qidx, rxq->pool->name); 1501 return -ENOMEM; 1502 } 1503 data_off = nicvf_mbuff_meta_length(mbuf); 1504 data_off += RTE_PKTMBUF_HEADROOM; 1505 rte_pktmbuf_free(mbuf); 1506 1507 if (data_off % RTE_CACHE_LINE_SIZE) { 1508 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1509 rxq->pool->name, data_off, 1510 data_off % RTE_CACHE_LINE_SIZE); 1511 return -EINVAL; 1512 } 1513 rxq->mbuf_phys_off -= data_off; 1514 1515 if (mbuf_phys_off == 0) 1516 mbuf_phys_off = rxq->mbuf_phys_off; 1517 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1518 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1519 PRIx64, rxq->pool->name, nic->vf_id, 1520 mbuf_phys_off); 1521 return -EINVAL; 1522 } 1523 } 1524 1525 /* Check the level of buffers in the pool */ 1526 total_rxq_desc = 0; 1527 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1528 rxq = dev->data->rx_queues[qidx]; 1529 /* Count total numbers of rxq descs */ 1530 total_rxq_desc += rxq->qlen_mask + 1; 1531 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1532 exp_buffs *= dev->data->nb_rx_queues; 1533 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1534 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1535 rxq->pool->name, 1536 rte_mempool_avail_count(rxq->pool), 1537 exp_buffs); 1538 return -ENOENT; 1539 } 1540 } 1541 1542 /* Check RBDR desc overflow */ 1543 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1544 if (ret == 0) { 1545 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1546 "VF%d", nic->vf_id); 1547 return -ENOMEM; 1548 } 1549 1550 /* Enable qset */ 1551 ret = nicvf_qset_config(nic); 1552 if (ret) { 1553 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1554 nic->vf_id); 1555 return ret; 1556 } 1557 1558 /* Allocate RBDR and RBDR ring desc */ 1559 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1560 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1561 if (ret) { 1562 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1563 "VF%d", nic->vf_id); 1564 goto qset_reclaim; 1565 } 1566 1567 /* Enable and configure RBDR registers */ 1568 ret = nicvf_qset_rbdr_config(nic, 0); 1569 if (ret) { 1570 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1571 nic->vf_id); 1572 goto qset_rbdr_free; 1573 } 1574 1575 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1576 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1577 total_rxq_desc); 1578 if (ret) { 1579 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1580 nic->vf_id); 1581 goto qset_rbdr_reclaim; 1582 } 1583 1584 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1585 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1586 1587 /* Configure VLAN Strip */ 1588 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip); 1589 1590 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1591 * to the 64bit memory address. 1592 * The alignment creates a hole in mbuf(between the end of headroom and 1593 * packet data start). The new revision of the HW provides an option to 1594 * disable the L3 alignment feature and make mbuf layout looks 1595 * more like other NICs. For better application compatibility, disabling 1596 * l3 alignment feature on the hardware revisions it supports 1597 */ 1598 nicvf_apad_config(nic, false); 1599 1600 /* Get queue ranges for this VF */ 1601 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1602 1603 /* Configure TX queues */ 1604 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1605 ret = nicvf_vf_start_tx_queue(dev, nic, 1606 qidx % MAX_SND_QUEUES_PER_QS); 1607 if (ret) 1608 goto start_txq_error; 1609 } 1610 1611 /* Configure RX queues */ 1612 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1613 ret = nicvf_vf_start_rx_queue(dev, nic, 1614 qidx % MAX_RCV_QUEUES_PER_QS); 1615 if (ret) 1616 goto start_rxq_error; 1617 } 1618 1619 if (!nic->sqs_mode) { 1620 /* Configure CPI algorithm */ 1621 ret = nicvf_configure_cpi(dev); 1622 if (ret) 1623 goto start_txq_error; 1624 1625 ret = nicvf_mbox_get_rss_size(nic); 1626 if (ret) { 1627 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1628 goto qset_rss_error; 1629 } 1630 1631 /* Configure RSS */ 1632 ret = nicvf_configure_rss(dev); 1633 if (ret) 1634 goto qset_rss_error; 1635 } 1636 1637 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1638 nicvf_mbox_cfg_done(nic); 1639 return 0; 1640 1641 qset_rss_error: 1642 nicvf_rss_term(nic); 1643 start_rxq_error: 1644 for (qidx = rx_start; qidx <= rx_end; qidx++) 1645 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1646 start_txq_error: 1647 for (qidx = tx_start; qidx <= tx_end; qidx++) 1648 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1649 qset_rbdr_reclaim: 1650 nicvf_qset_rbdr_reclaim(nic, 0); 1651 nicvf_rbdr_release_mbufs(dev, nic); 1652 qset_rbdr_free: 1653 if (nic->rbdr) { 1654 rte_free(nic->rbdr); 1655 nic->rbdr = NULL; 1656 } 1657 qset_reclaim: 1658 nicvf_qset_reclaim(nic); 1659 return ret; 1660 } 1661 1662 static int 1663 nicvf_dev_start(struct rte_eth_dev *dev) 1664 { 1665 uint16_t qidx; 1666 int ret; 1667 size_t i; 1668 struct nicvf *nic = nicvf_pmd_priv(dev); 1669 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1670 uint16_t mtu; 1671 uint32_t buffsz = 0, rbdrsz = 0; 1672 struct rte_pktmbuf_pool_private *mbp_priv; 1673 struct nicvf_rxq *rxq; 1674 1675 PMD_INIT_FUNC_TRACE(); 1676 1677 /* This function must be called for a primary device */ 1678 assert_primary(nic); 1679 1680 /* Validate RBDR buff size */ 1681 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1682 rxq = dev->data->rx_queues[qidx]; 1683 mbp_priv = rte_mempool_get_priv(rxq->pool); 1684 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1685 if (buffsz % 128) { 1686 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1687 return -EINVAL; 1688 } 1689 if (rbdrsz == 0) 1690 rbdrsz = buffsz; 1691 if (rbdrsz != buffsz) { 1692 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1693 qidx, rbdrsz, buffsz); 1694 return -EINVAL; 1695 } 1696 } 1697 1698 /* Configure loopback */ 1699 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1700 if (ret) { 1701 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1702 return ret; 1703 } 1704 1705 /* Reset all statistics counters attached to this port */ 1706 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1707 if (ret) { 1708 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1709 return ret; 1710 } 1711 1712 /* Setup scatter mode if needed by jumbo */ 1713 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1714 2 * VLAN_TAG_SIZE > buffsz) 1715 dev->data->scattered_rx = 1; 1716 if (rx_conf->enable_scatter) 1717 dev->data->scattered_rx = 1; 1718 1719 /* Setup MTU based on max_rx_pkt_len or default */ 1720 mtu = dev->data->dev_conf.rxmode.jumbo_frame ? 1721 dev->data->dev_conf.rxmode.max_rx_pkt_len 1722 - ETHER_HDR_LEN - ETHER_CRC_LEN 1723 : ETHER_MTU; 1724 1725 if (nicvf_dev_set_mtu(dev, mtu)) { 1726 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1727 return -EBUSY; 1728 } 1729 1730 ret = nicvf_vf_start(dev, nic, rbdrsz); 1731 if (ret != 0) 1732 return ret; 1733 1734 for (i = 0; i < nic->sqs_count; i++) { 1735 assert(nic->snicvf[i]); 1736 1737 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1738 if (ret != 0) 1739 return ret; 1740 } 1741 1742 /* Configure callbacks based on scatter mode */ 1743 nicvf_set_tx_function(dev); 1744 nicvf_set_rx_function(dev); 1745 1746 return 0; 1747 } 1748 1749 static void 1750 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1751 { 1752 size_t i; 1753 int ret; 1754 struct nicvf *nic = nicvf_pmd_priv(dev); 1755 1756 PMD_INIT_FUNC_TRACE(); 1757 1758 /* Teardown secondary vf first */ 1759 for (i = 0; i < nic->sqs_count; i++) { 1760 if (!nic->snicvf[i]) 1761 continue; 1762 1763 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1764 } 1765 1766 /* Stop the primary VF now */ 1767 nicvf_vf_stop(dev, nic, cleanup); 1768 1769 /* Disable loopback */ 1770 ret = nicvf_loopback_config(nic, 0); 1771 if (ret) 1772 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1773 1774 /* Reclaim CPI configuration */ 1775 ret = nicvf_mbox_config_cpi(nic, 0); 1776 if (ret) 1777 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1778 } 1779 1780 static void 1781 nicvf_dev_stop(struct rte_eth_dev *dev) 1782 { 1783 PMD_INIT_FUNC_TRACE(); 1784 1785 nicvf_dev_stop_cleanup(dev, false); 1786 } 1787 1788 static void 1789 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1790 { 1791 int ret; 1792 uint16_t qidx; 1793 uint16_t tx_start, tx_end; 1794 uint16_t rx_start, rx_end; 1795 1796 PMD_INIT_FUNC_TRACE(); 1797 1798 if (cleanup) { 1799 /* Let PF make the BGX's RX and TX switches to OFF position */ 1800 nicvf_mbox_shutdown(nic); 1801 } 1802 1803 /* Disable VLAN Strip */ 1804 nicvf_vlan_hw_strip(nic, 0); 1805 1806 /* Get queue ranges for this VF */ 1807 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1808 1809 for (qidx = tx_start; qidx <= tx_end; qidx++) 1810 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1811 1812 /* Get queue ranges for this VF */ 1813 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1814 1815 /* Reclaim rq */ 1816 for (qidx = rx_start; qidx <= rx_end; qidx++) 1817 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1818 1819 /* Reclaim RBDR */ 1820 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1821 if (ret) 1822 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1823 1824 /* Move all charged buffers in RBDR back to pool */ 1825 if (nic->rbdr != NULL) 1826 nicvf_rbdr_release_mbufs(dev, nic); 1827 1828 /* Disable qset */ 1829 ret = nicvf_qset_reclaim(nic); 1830 if (ret) 1831 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1832 1833 /* Disable all interrupts */ 1834 nicvf_disable_all_interrupts(nic); 1835 1836 /* Free RBDR SW structure */ 1837 if (nic->rbdr) { 1838 rte_free(nic->rbdr); 1839 nic->rbdr = NULL; 1840 } 1841 } 1842 1843 static void 1844 nicvf_dev_close(struct rte_eth_dev *dev) 1845 { 1846 size_t i; 1847 struct nicvf *nic = nicvf_pmd_priv(dev); 1848 1849 PMD_INIT_FUNC_TRACE(); 1850 1851 nicvf_dev_stop_cleanup(dev, true); 1852 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1853 1854 for (i = 0; i < nic->sqs_count; i++) { 1855 if (!nic->snicvf[i]) 1856 continue; 1857 1858 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); 1859 } 1860 } 1861 1862 static int 1863 nicvf_request_sqs(struct nicvf *nic) 1864 { 1865 size_t i; 1866 1867 assert_primary(nic); 1868 assert(nic->sqs_count > 0); 1869 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1870 1871 /* Set no of Rx/Tx queues in each of the SQsets */ 1872 for (i = 0; i < nic->sqs_count; i++) { 1873 if (nicvf_svf_empty()) 1874 rte_panic("Cannot assign sufficient number of " 1875 "secondary queues to primary VF%" PRIu8 "\n", 1876 nic->vf_id); 1877 1878 nic->snicvf[i] = nicvf_svf_pop(); 1879 nic->snicvf[i]->sqs_id = i; 1880 } 1881 1882 return nicvf_mbox_request_sqs(nic); 1883 } 1884 1885 static int 1886 nicvf_dev_configure(struct rte_eth_dev *dev) 1887 { 1888 struct rte_eth_dev_data *data = dev->data; 1889 struct rte_eth_conf *conf = &data->dev_conf; 1890 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1891 struct rte_eth_txmode *txmode = &conf->txmode; 1892 struct nicvf *nic = nicvf_pmd_priv(dev); 1893 uint8_t cqcount; 1894 1895 PMD_INIT_FUNC_TRACE(); 1896 1897 if (!rte_eal_has_hugepages()) { 1898 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1899 return -EINVAL; 1900 } 1901 1902 if (txmode->mq_mode) { 1903 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1904 return -EINVAL; 1905 } 1906 1907 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1908 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1909 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1910 return -EINVAL; 1911 } 1912 1913 if (!rxmode->hw_strip_crc) { 1914 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip"); 1915 rxmode->hw_strip_crc = 1; 1916 } 1917 1918 if (rxmode->hw_ip_checksum) { 1919 PMD_INIT_LOG(NOTICE, "Rxcksum not supported"); 1920 rxmode->hw_ip_checksum = 0; 1921 } 1922 1923 if (rxmode->split_hdr_size) { 1924 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1925 return -EINVAL; 1926 } 1927 1928 if (rxmode->hw_vlan_filter) { 1929 PMD_INIT_LOG(INFO, "VLAN filter not supported"); 1930 return -EINVAL; 1931 } 1932 1933 if (rxmode->hw_vlan_extend) { 1934 PMD_INIT_LOG(INFO, "VLAN extended not supported"); 1935 return -EINVAL; 1936 } 1937 1938 if (rxmode->enable_lro) { 1939 PMD_INIT_LOG(INFO, "LRO not supported"); 1940 return -EINVAL; 1941 } 1942 1943 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1944 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1945 return -EINVAL; 1946 } 1947 1948 if (conf->dcb_capability_en) { 1949 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1950 return -EINVAL; 1951 } 1952 1953 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1954 PMD_INIT_LOG(INFO, "Flow director not supported"); 1955 return -EINVAL; 1956 } 1957 1958 assert_primary(nic); 1959 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1960 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1961 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1962 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1963 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1964 } else { 1965 nic->sqs_count = 0; 1966 } 1967 1968 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1969 1970 if (nic->sqs_count > 0) { 1971 if (nicvf_request_sqs(nic)) { 1972 rte_panic("Cannot assign sufficient number of " 1973 "secondary queues to PORT%d VF%" PRIu8 "\n", 1974 dev->data->port_id, nic->vf_id); 1975 } 1976 } 1977 1978 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1979 dev->data->port_id, nicvf_hw_cap(nic)); 1980 1981 return 0; 1982 } 1983 1984 /* Initialize and register driver with DPDK Application */ 1985 static const struct eth_dev_ops nicvf_eth_dev_ops = { 1986 .dev_configure = nicvf_dev_configure, 1987 .dev_start = nicvf_dev_start, 1988 .dev_stop = nicvf_dev_stop, 1989 .link_update = nicvf_dev_link_update, 1990 .dev_close = nicvf_dev_close, 1991 .stats_get = nicvf_dev_stats_get, 1992 .stats_reset = nicvf_dev_stats_reset, 1993 .promiscuous_enable = nicvf_dev_promisc_enable, 1994 .dev_infos_get = nicvf_dev_info_get, 1995 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 1996 .mtu_set = nicvf_dev_set_mtu, 1997 .reta_update = nicvf_dev_reta_update, 1998 .reta_query = nicvf_dev_reta_query, 1999 .rss_hash_update = nicvf_dev_rss_hash_update, 2000 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 2001 .rx_queue_start = nicvf_dev_rx_queue_start, 2002 .rx_queue_stop = nicvf_dev_rx_queue_stop, 2003 .tx_queue_start = nicvf_dev_tx_queue_start, 2004 .tx_queue_stop = nicvf_dev_tx_queue_stop, 2005 .rx_queue_setup = nicvf_dev_rx_queue_setup, 2006 .rx_queue_release = nicvf_dev_rx_queue_release, 2007 .rx_queue_count = nicvf_dev_rx_queue_count, 2008 .tx_queue_setup = nicvf_dev_tx_queue_setup, 2009 .tx_queue_release = nicvf_dev_tx_queue_release, 2010 .get_reg = nicvf_dev_get_regs, 2011 }; 2012 2013 static int 2014 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2015 { 2016 int ret; 2017 struct rte_pci_device *pci_dev; 2018 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2019 2020 PMD_INIT_FUNC_TRACE(); 2021 2022 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2023 2024 /* For secondary processes, the primary has done all the work */ 2025 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2026 if (nic) { 2027 /* Setup callbacks for secondary process */ 2028 nicvf_set_tx_function(eth_dev); 2029 nicvf_set_rx_function(eth_dev); 2030 return 0; 2031 } else { 2032 /* If nic == NULL than it is secondary function 2033 * so ethdev need to be released by caller */ 2034 return ENOTSUP; 2035 } 2036 } 2037 2038 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2039 rte_eth_copy_pci_info(eth_dev, pci_dev); 2040 2041 nic->device_id = pci_dev->id.device_id; 2042 nic->vendor_id = pci_dev->id.vendor_id; 2043 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2044 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2045 2046 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2047 pci_dev->id.vendor_id, pci_dev->id.device_id, 2048 pci_dev->addr.domain, pci_dev->addr.bus, 2049 pci_dev->addr.devid, pci_dev->addr.function); 2050 2051 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2052 if (!nic->reg_base) { 2053 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2054 ret = -ENODEV; 2055 goto fail; 2056 } 2057 2058 nicvf_disable_all_interrupts(nic); 2059 2060 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2061 if (ret) { 2062 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2063 goto fail; 2064 } 2065 2066 ret = nicvf_mbox_check_pf_ready(nic); 2067 if (ret) { 2068 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2069 goto alarm_fail; 2070 } else { 2071 PMD_INIT_LOG(INFO, 2072 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2073 nic->node, nic->vf_id, 2074 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2075 nic->sqs_mode ? "true" : "false", 2076 nic->loopback_supported ? "true" : "false" 2077 ); 2078 } 2079 2080 ret = nicvf_base_init(nic); 2081 if (ret) { 2082 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2083 goto malloc_fail; 2084 } 2085 2086 if (nic->sqs_mode) { 2087 /* Push nic to stack of secondary vfs */ 2088 nicvf_svf_push(nic); 2089 2090 /* Steal nic pointer from the device for further reuse */ 2091 eth_dev->data->dev_private = NULL; 2092 2093 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2094 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2095 if (ret) { 2096 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2097 goto fail; 2098 } 2099 2100 /* Detach port by returning positive error number */ 2101 return ENOTSUP; 2102 } 2103 2104 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); 2105 if (eth_dev->data->mac_addrs == NULL) { 2106 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2107 ret = -ENOMEM; 2108 goto alarm_fail; 2109 } 2110 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr)) 2111 eth_random_addr(&nic->mac_addr[0]); 2112 2113 ether_addr_copy((struct ether_addr *)nic->mac_addr, 2114 ð_dev->data->mac_addrs[0]); 2115 2116 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2117 if (ret) { 2118 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2119 goto malloc_fail; 2120 } 2121 2122 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 2123 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2124 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2125 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2126 2127 return 0; 2128 2129 malloc_fail: 2130 rte_free(eth_dev->data->mac_addrs); 2131 alarm_fail: 2132 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2133 fail: 2134 return ret; 2135 } 2136 2137 static const struct rte_pci_id pci_id_nicvf_map[] = { 2138 { 2139 .class_id = RTE_CLASS_ANY_ID, 2140 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2141 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2142 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2143 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2144 }, 2145 { 2146 .class_id = RTE_CLASS_ANY_ID, 2147 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2148 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2149 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2150 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2151 }, 2152 { 2153 .class_id = RTE_CLASS_ANY_ID, 2154 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2155 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2156 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2157 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2158 }, 2159 { 2160 .class_id = RTE_CLASS_ANY_ID, 2161 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2162 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2163 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2164 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2165 }, 2166 { 2167 .vendor_id = 0, 2168 }, 2169 }; 2170 2171 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2172 struct rte_pci_device *pci_dev) 2173 { 2174 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2175 nicvf_eth_dev_init); 2176 } 2177 2178 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2179 { 2180 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 2181 } 2182 2183 static struct rte_pci_driver rte_nicvf_pmd = { 2184 .id_table = pci_id_nicvf_map, 2185 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2186 RTE_PCI_DRV_INTR_LSC, 2187 .probe = nicvf_eth_pci_probe, 2188 .remove = nicvf_eth_pci_remove, 2189 }; 2190 2191 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2192 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2193 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2194