1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016 Cavium, Inc 3 */ 4 5 #include <assert.h> 6 #include <stdio.h> 7 #include <stdbool.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 #include <rte_alarm.h> 18 #include <rte_branch_prediction.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_cycles.h> 22 #include <rte_debug.h> 23 #include <rte_dev.h> 24 #include <rte_eal.h> 25 #include <rte_ether.h> 26 #include <rte_ethdev_driver.h> 27 #include <rte_ethdev_pci.h> 28 #include <rte_interrupts.h> 29 #include <rte_log.h> 30 #include <rte_memory.h> 31 #include <rte_memzone.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_pci.h> 35 #include <rte_bus_pci.h> 36 #include <rte_tailq.h> 37 #include <rte_devargs.h> 38 #include <rte_kvargs.h> 39 40 #include "base/nicvf_plat.h" 41 42 #include "nicvf_ethdev.h" 43 #include "nicvf_rxtx.h" 44 #include "nicvf_svf.h" 45 #include "nicvf_logs.h" 46 47 int nicvf_logtype_mbox; 48 int nicvf_logtype_init; 49 int nicvf_logtype_driver; 50 51 static void nicvf_dev_stop(struct rte_eth_dev *dev); 52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup); 53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, 54 bool cleanup); 55 56 RTE_INIT(nicvf_init_log); 57 static void 58 nicvf_init_log(void) 59 { 60 nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox"); 61 if (nicvf_logtype_mbox >= 0) 62 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE); 63 64 nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init"); 65 if (nicvf_logtype_init >= 0) 66 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE); 67 68 nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver"); 69 if (nicvf_logtype_driver >= 0) 70 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE); 71 } 72 73 static void 74 nicvf_link_status_update(struct nicvf *nic, 75 struct rte_eth_link *link) 76 { 77 memset(link, 0, sizeof(*link)); 78 79 link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN; 80 81 if (nic->duplex == NICVF_HALF_DUPLEX) 82 link->link_duplex = ETH_LINK_HALF_DUPLEX; 83 else if (nic->duplex == NICVF_FULL_DUPLEX) 84 link->link_duplex = ETH_LINK_FULL_DUPLEX; 85 link->link_speed = nic->speed; 86 link->link_autoneg = ETH_LINK_AUTONEG; 87 } 88 89 static void 90 nicvf_interrupt(void *arg) 91 { 92 struct rte_eth_dev *dev = arg; 93 struct nicvf *nic = nicvf_pmd_priv(dev); 94 struct rte_eth_link link; 95 96 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) { 97 if (dev->data->dev_conf.intr_conf.lsc) { 98 nicvf_link_status_update(nic, &link); 99 rte_eth_linkstatus_set(dev, &link); 100 101 _rte_eth_dev_callback_process(dev, 102 RTE_ETH_EVENT_INTR_LSC, 103 NULL); 104 } 105 } 106 107 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 108 nicvf_interrupt, dev); 109 } 110 111 static void 112 nicvf_vf_interrupt(void *arg) 113 { 114 struct nicvf *nic = arg; 115 116 nicvf_reg_poll_interrupts(nic); 117 118 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, 119 nicvf_vf_interrupt, nic); 120 } 121 122 static int 123 nicvf_periodic_alarm_start(void (fn)(void *), void *arg) 124 { 125 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg); 126 } 127 128 static int 129 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg) 130 { 131 return rte_eal_alarm_cancel(fn, arg); 132 } 133 134 /* 135 * Return 0 means link status changed, -1 means not changed 136 */ 137 static int 138 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 139 { 140 #define CHECK_INTERVAL 100 /* 100ms */ 141 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 142 struct rte_eth_link link; 143 struct nicvf *nic = nicvf_pmd_priv(dev); 144 int i; 145 146 PMD_INIT_FUNC_TRACE(); 147 148 if (wait_to_complete) { 149 /* rte_eth_link_get() might need to wait up to 9 seconds */ 150 for (i = 0; i < MAX_CHECK_TIME; i++) { 151 nicvf_link_status_update(nic, &link); 152 if (link.link_status == ETH_LINK_UP) 153 break; 154 rte_delay_ms(CHECK_INTERVAL); 155 } 156 } else { 157 nicvf_link_status_update(nic, &link); 158 } 159 160 return rte_eth_linkstatus_set(dev, &link); 161 } 162 163 static int 164 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 165 { 166 struct nicvf *nic = nicvf_pmd_priv(dev); 167 uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD; 168 size_t i; 169 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 170 171 PMD_INIT_FUNC_TRACE(); 172 173 if (frame_size > NIC_HW_MAX_FRS) 174 return -EINVAL; 175 176 if (frame_size < NIC_HW_MIN_FRS) 177 return -EINVAL; 178 179 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 180 181 /* 182 * Refuse mtu that requires the support of scattered packets 183 * when this feature has not been enabled before. 184 */ 185 if (dev->data->dev_started && !dev->data->scattered_rx && 186 (frame_size + 2 * VLAN_TAG_SIZE > buffsz)) 187 return -EINVAL; 188 189 /* check <seg size> * <max_seg> >= max_frame */ 190 if (dev->data->scattered_rx && 191 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS)) 192 return -EINVAL; 193 194 if (frame_size > ETHER_MAX_LEN) 195 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 196 else 197 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 198 199 if (nicvf_mbox_update_hw_max_frs(nic, mtu)) 200 return -EINVAL; 201 202 /* Update max_rx_pkt_len */ 203 rxmode->max_rx_pkt_len = mtu + ETHER_HDR_LEN; 204 nic->mtu = mtu; 205 206 for (i = 0; i < nic->sqs_count; i++) 207 nic->snicvf[i]->mtu = mtu; 208 209 return 0; 210 } 211 212 static int 213 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 214 { 215 uint64_t *data = regs->data; 216 struct nicvf *nic = nicvf_pmd_priv(dev); 217 218 if (data == NULL) { 219 regs->length = nicvf_reg_get_count(); 220 regs->width = THUNDERX_REG_BYTES; 221 return 0; 222 } 223 224 /* Support only full register dump */ 225 if ((regs->length == 0) || 226 (regs->length == (uint32_t)nicvf_reg_get_count())) { 227 regs->version = nic->vendor_id << 16 | nic->device_id; 228 nicvf_reg_dump(nic, data); 229 return 0; 230 } 231 return -ENOTSUP; 232 } 233 234 static int 235 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 236 { 237 uint16_t qidx; 238 struct nicvf_hw_rx_qstats rx_qstats; 239 struct nicvf_hw_tx_qstats tx_qstats; 240 struct nicvf_hw_stats port_stats; 241 struct nicvf *nic = nicvf_pmd_priv(dev); 242 uint16_t rx_start, rx_end; 243 uint16_t tx_start, tx_end; 244 size_t i; 245 246 /* RX queue indices for the first VF */ 247 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 248 249 /* Reading per RX ring stats */ 250 for (qidx = rx_start; qidx <= rx_end; qidx++) { 251 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 252 break; 253 254 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx); 255 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 256 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 257 } 258 259 /* TX queue indices for the first VF */ 260 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 261 262 /* Reading per TX ring stats */ 263 for (qidx = tx_start; qidx <= tx_end; qidx++) { 264 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 265 break; 266 267 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx); 268 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 269 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 270 } 271 272 for (i = 0; i < nic->sqs_count; i++) { 273 struct nicvf *snic = nic->snicvf[i]; 274 275 if (snic == NULL) 276 break; 277 278 /* RX queue indices for a secondary VF */ 279 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 280 281 /* Reading per RX ring stats */ 282 for (qidx = rx_start; qidx <= rx_end; qidx++) { 283 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 284 break; 285 286 nicvf_hw_get_rx_qstats(snic, &rx_qstats, 287 qidx % MAX_RCV_QUEUES_PER_QS); 288 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes; 289 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets; 290 } 291 292 /* TX queue indices for a secondary VF */ 293 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 294 /* Reading per TX ring stats */ 295 for (qidx = tx_start; qidx <= tx_end; qidx++) { 296 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 297 break; 298 299 nicvf_hw_get_tx_qstats(snic, &tx_qstats, 300 qidx % MAX_SND_QUEUES_PER_QS); 301 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes; 302 stats->q_opackets[qidx] = tx_qstats.q_tx_packets; 303 } 304 } 305 306 nicvf_hw_get_stats(nic, &port_stats); 307 stats->ibytes = port_stats.rx_bytes; 308 stats->ipackets = port_stats.rx_ucast_frames; 309 stats->ipackets += port_stats.rx_bcast_frames; 310 stats->ipackets += port_stats.rx_mcast_frames; 311 stats->ierrors = port_stats.rx_l2_errors; 312 stats->imissed = port_stats.rx_drop_red; 313 stats->imissed += port_stats.rx_drop_overrun; 314 stats->imissed += port_stats.rx_drop_bcast; 315 stats->imissed += port_stats.rx_drop_mcast; 316 stats->imissed += port_stats.rx_drop_l3_bcast; 317 stats->imissed += port_stats.rx_drop_l3_mcast; 318 319 stats->obytes = port_stats.tx_bytes_ok; 320 stats->opackets = port_stats.tx_ucast_frames_ok; 321 stats->opackets += port_stats.tx_bcast_frames_ok; 322 stats->opackets += port_stats.tx_mcast_frames_ok; 323 stats->oerrors = port_stats.tx_drops; 324 325 return 0; 326 } 327 328 static const uint32_t * 329 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev) 330 { 331 size_t copied; 332 static uint32_t ptypes[32]; 333 struct nicvf *nic = nicvf_pmd_priv(dev); 334 static const uint32_t ptypes_common[] = { 335 RTE_PTYPE_L3_IPV4, 336 RTE_PTYPE_L3_IPV4_EXT, 337 RTE_PTYPE_L3_IPV6, 338 RTE_PTYPE_L3_IPV6_EXT, 339 RTE_PTYPE_L4_TCP, 340 RTE_PTYPE_L4_UDP, 341 RTE_PTYPE_L4_FRAG, 342 }; 343 static const uint32_t ptypes_tunnel[] = { 344 RTE_PTYPE_TUNNEL_GRE, 345 RTE_PTYPE_TUNNEL_GENEVE, 346 RTE_PTYPE_TUNNEL_VXLAN, 347 RTE_PTYPE_TUNNEL_NVGRE, 348 }; 349 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN; 350 351 copied = sizeof(ptypes_common); 352 memcpy(ptypes, ptypes_common, copied); 353 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 354 memcpy((char *)ptypes + copied, ptypes_tunnel, 355 sizeof(ptypes_tunnel)); 356 copied += sizeof(ptypes_tunnel); 357 } 358 359 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end)); 360 if (dev->rx_pkt_burst == nicvf_recv_pkts || 361 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg) 362 return ptypes; 363 364 return NULL; 365 } 366 367 static void 368 nicvf_dev_stats_reset(struct rte_eth_dev *dev) 369 { 370 int i; 371 uint16_t rxqs = 0, txqs = 0; 372 struct nicvf *nic = nicvf_pmd_priv(dev); 373 uint16_t rx_start, rx_end; 374 uint16_t tx_start, tx_end; 375 376 /* Reset all primary nic counters */ 377 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 378 for (i = rx_start; i <= rx_end; i++) 379 rxqs |= (0x3 << (i * 2)); 380 381 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 382 for (i = tx_start; i <= tx_end; i++) 383 txqs |= (0x3 << (i * 2)); 384 385 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs); 386 387 /* Reset secondary nic queue counters */ 388 for (i = 0; i < nic->sqs_count; i++) { 389 struct nicvf *snic = nic->snicvf[i]; 390 if (snic == NULL) 391 break; 392 393 nicvf_rx_range(dev, snic, &rx_start, &rx_end); 394 for (i = rx_start; i <= rx_end; i++) 395 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2)); 396 397 nicvf_tx_range(dev, snic, &tx_start, &tx_end); 398 for (i = tx_start; i <= tx_end; i++) 399 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2)); 400 401 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs); 402 } 403 } 404 405 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */ 406 static void 407 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused) 408 { 409 } 410 411 static inline uint64_t 412 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss) 413 { 414 uint64_t nic_rss = 0; 415 416 if (ethdev_rss & ETH_RSS_IPV4) 417 nic_rss |= RSS_IP_ENA; 418 419 if (ethdev_rss & ETH_RSS_IPV6) 420 nic_rss |= RSS_IP_ENA; 421 422 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP) 423 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 424 425 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP) 426 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 427 428 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP) 429 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA); 430 431 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP) 432 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA); 433 434 if (ethdev_rss & ETH_RSS_PORT) 435 nic_rss |= RSS_L2_EXTENDED_HASH_ENA; 436 437 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 438 if (ethdev_rss & ETH_RSS_VXLAN) 439 nic_rss |= RSS_TUN_VXLAN_ENA; 440 441 if (ethdev_rss & ETH_RSS_GENEVE) 442 nic_rss |= RSS_TUN_GENEVE_ENA; 443 444 if (ethdev_rss & ETH_RSS_NVGRE) 445 nic_rss |= RSS_TUN_NVGRE_ENA; 446 } 447 448 return nic_rss; 449 } 450 451 static inline uint64_t 452 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss) 453 { 454 uint64_t ethdev_rss = 0; 455 456 if (nic_rss & RSS_IP_ENA) 457 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6); 458 459 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA)) 460 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP | 461 ETH_RSS_NONFRAG_IPV6_TCP); 462 463 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA)) 464 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP | 465 ETH_RSS_NONFRAG_IPV6_UDP); 466 467 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA) 468 ethdev_rss |= ETH_RSS_PORT; 469 470 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) { 471 if (nic_rss & RSS_TUN_VXLAN_ENA) 472 ethdev_rss |= ETH_RSS_VXLAN; 473 474 if (nic_rss & RSS_TUN_GENEVE_ENA) 475 ethdev_rss |= ETH_RSS_GENEVE; 476 477 if (nic_rss & RSS_TUN_NVGRE_ENA) 478 ethdev_rss |= ETH_RSS_NVGRE; 479 } 480 return ethdev_rss; 481 } 482 483 static int 484 nicvf_dev_reta_query(struct rte_eth_dev *dev, 485 struct rte_eth_rss_reta_entry64 *reta_conf, 486 uint16_t reta_size) 487 { 488 struct nicvf *nic = nicvf_pmd_priv(dev); 489 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 490 int ret, i, j; 491 492 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 493 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 494 "(%d) doesn't match the number hardware can supported " 495 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 496 return -EINVAL; 497 } 498 499 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 500 if (ret) 501 return ret; 502 503 /* Copy RETA table */ 504 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 505 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 506 if ((reta_conf[i].mask >> j) & 0x01) 507 reta_conf[i].reta[j] = tbl[j]; 508 } 509 510 return 0; 511 } 512 513 static int 514 nicvf_dev_reta_update(struct rte_eth_dev *dev, 515 struct rte_eth_rss_reta_entry64 *reta_conf, 516 uint16_t reta_size) 517 { 518 struct nicvf *nic = nicvf_pmd_priv(dev); 519 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 520 int ret, i, j; 521 522 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) { 523 RTE_LOG(ERR, PMD, "The size of hash lookup table configured " 524 "(%d) doesn't match the number hardware can supported " 525 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE); 526 return -EINVAL; 527 } 528 529 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 530 if (ret) 531 return ret; 532 533 /* Copy RETA table */ 534 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) { 535 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) 536 if ((reta_conf[i].mask >> j) & 0x01) 537 tbl[j] = reta_conf[i].reta[j]; 538 } 539 540 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE); 541 } 542 543 static int 544 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 545 struct rte_eth_rss_conf *rss_conf) 546 { 547 struct nicvf *nic = nicvf_pmd_priv(dev); 548 549 if (rss_conf->rss_key) 550 nicvf_rss_get_key(nic, rss_conf->rss_key); 551 552 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE; 553 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic)); 554 return 0; 555 } 556 557 static int 558 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev, 559 struct rte_eth_rss_conf *rss_conf) 560 { 561 struct nicvf *nic = nicvf_pmd_priv(dev); 562 uint64_t nic_rss; 563 564 if (rss_conf->rss_key && 565 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) { 566 RTE_LOG(ERR, PMD, "Hash key size mismatch %d", 567 rss_conf->rss_key_len); 568 return -EINVAL; 569 } 570 571 if (rss_conf->rss_key) 572 nicvf_rss_set_key(nic, rss_conf->rss_key); 573 574 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf); 575 nicvf_rss_set_cfg(nic, nic_rss); 576 return 0; 577 } 578 579 static int 580 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 581 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt) 582 { 583 const struct rte_memzone *rz; 584 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t); 585 586 rz = rte_eth_dma_zone_reserve(dev, "cq_ring", 587 nicvf_netdev_qidx(nic, qidx), ring_size, 588 NICVF_CQ_BASE_ALIGN_BYTES, nic->node); 589 if (rz == NULL) { 590 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring"); 591 return -ENOMEM; 592 } 593 594 memset(rz->addr, 0, ring_size); 595 596 rxq->phys = rz->iova; 597 rxq->desc = rz->addr; 598 rxq->qlen_mask = desc_cnt - 1; 599 600 return 0; 601 } 602 603 static int 604 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 605 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt) 606 { 607 const struct rte_memzone *rz; 608 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t); 609 610 rz = rte_eth_dma_zone_reserve(dev, "sq", 611 nicvf_netdev_qidx(nic, qidx), ring_size, 612 NICVF_SQ_BASE_ALIGN_BYTES, nic->node); 613 if (rz == NULL) { 614 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring"); 615 return -ENOMEM; 616 } 617 618 memset(rz->addr, 0, ring_size); 619 620 sq->phys = rz->iova; 621 sq->desc = rz->addr; 622 sq->qlen_mask = desc_cnt - 1; 623 624 return 0; 625 } 626 627 static int 628 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic, 629 uint32_t desc_cnt, uint32_t buffsz) 630 { 631 struct nicvf_rbdr *rbdr; 632 const struct rte_memzone *rz; 633 uint32_t ring_size; 634 635 assert(nic->rbdr == NULL); 636 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr), 637 RTE_CACHE_LINE_SIZE, nic->node); 638 if (rbdr == NULL) { 639 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr"); 640 return -ENOMEM; 641 } 642 643 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX; 644 rz = rte_eth_dma_zone_reserve(dev, "rbdr", 645 nicvf_netdev_qidx(nic, 0), ring_size, 646 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node); 647 if (rz == NULL) { 648 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring"); 649 return -ENOMEM; 650 } 651 652 memset(rz->addr, 0, ring_size); 653 654 rbdr->phys = rz->iova; 655 rbdr->tail = 0; 656 rbdr->next_tail = 0; 657 rbdr->desc = rz->addr; 658 rbdr->buffsz = buffsz; 659 rbdr->qlen_mask = desc_cnt - 1; 660 rbdr->rbdr_status = 661 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0; 662 rbdr->rbdr_door = 663 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR; 664 665 nic->rbdr = rbdr; 666 return 0; 667 } 668 669 static void 670 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic, 671 nicvf_iova_addr_t phy) 672 { 673 uint16_t qidx; 674 void *obj; 675 struct nicvf_rxq *rxq; 676 uint16_t rx_start, rx_end; 677 678 /* Get queue ranges for this VF */ 679 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 680 681 for (qidx = rx_start; qidx <= rx_end; qidx++) { 682 rxq = dev->data->rx_queues[qidx]; 683 if (rxq->precharge_cnt) { 684 obj = (void *)nicvf_mbuff_phy2virt(phy, 685 rxq->mbuf_phys_off); 686 rte_mempool_put(rxq->pool, obj); 687 rxq->precharge_cnt--; 688 break; 689 } 690 } 691 } 692 693 static inline void 694 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic) 695 { 696 uint32_t qlen_mask, head; 697 struct rbdr_entry_t *entry; 698 struct nicvf_rbdr *rbdr = nic->rbdr; 699 700 qlen_mask = rbdr->qlen_mask; 701 head = rbdr->head; 702 while (head != rbdr->tail) { 703 entry = rbdr->desc + head; 704 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr); 705 head++; 706 head = head & qlen_mask; 707 } 708 } 709 710 static inline void 711 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq) 712 { 713 uint32_t head; 714 715 head = txq->head; 716 while (head != txq->tail) { 717 if (txq->txbuffs[head]) { 718 rte_pktmbuf_free_seg(txq->txbuffs[head]); 719 txq->txbuffs[head] = NULL; 720 } 721 head++; 722 head = head & txq->qlen_mask; 723 } 724 } 725 726 static void 727 nicvf_tx_queue_reset(struct nicvf_txq *txq) 728 { 729 uint32_t txq_desc_cnt = txq->qlen_mask + 1; 730 731 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt); 732 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt); 733 txq->tail = 0; 734 txq->head = 0; 735 txq->xmit_bufs = 0; 736 } 737 738 static inline int 739 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 740 uint16_t qidx) 741 { 742 struct nicvf_txq *txq; 743 int ret; 744 745 assert(qidx < MAX_SND_QUEUES_PER_QS); 746 747 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 748 RTE_ETH_QUEUE_STATE_STARTED) 749 return 0; 750 751 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 752 txq->pool = NULL; 753 ret = nicvf_qset_sq_config(nic, qidx, txq); 754 if (ret) { 755 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d", 756 nic->vf_id, qidx, ret); 757 goto config_sq_error; 758 } 759 760 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 761 RTE_ETH_QUEUE_STATE_STARTED; 762 return ret; 763 764 config_sq_error: 765 nicvf_qset_sq_reclaim(nic, qidx); 766 return ret; 767 } 768 769 static inline int 770 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 771 uint16_t qidx) 772 { 773 struct nicvf_txq *txq; 774 int ret; 775 776 assert(qidx < MAX_SND_QUEUES_PER_QS); 777 778 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 779 RTE_ETH_QUEUE_STATE_STOPPED) 780 return 0; 781 782 ret = nicvf_qset_sq_reclaim(nic, qidx); 783 if (ret) 784 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d", 785 nic->vf_id, qidx, ret); 786 787 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]; 788 nicvf_tx_queue_release_mbufs(txq); 789 nicvf_tx_queue_reset(txq); 790 791 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 792 RTE_ETH_QUEUE_STATE_STOPPED; 793 return ret; 794 } 795 796 static inline int 797 nicvf_configure_cpi(struct rte_eth_dev *dev) 798 { 799 struct nicvf *nic = nicvf_pmd_priv(dev); 800 uint16_t qidx, qcnt; 801 int ret; 802 803 /* Count started rx queues */ 804 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++) 805 if (dev->data->rx_queue_state[qidx] == 806 RTE_ETH_QUEUE_STATE_STARTED) 807 qcnt++; 808 809 nic->cpi_alg = CPI_ALG_NONE; 810 ret = nicvf_mbox_config_cpi(nic, qcnt); 811 if (ret) 812 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret); 813 814 return ret; 815 } 816 817 static inline int 818 nicvf_configure_rss(struct rte_eth_dev *dev) 819 { 820 struct nicvf *nic = nicvf_pmd_priv(dev); 821 uint64_t rsshf; 822 int ret = -EINVAL; 823 824 rsshf = nicvf_rss_ethdev_to_nic(nic, 825 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf); 826 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64, 827 dev->data->dev_conf.rxmode.mq_mode, 828 dev->data->nb_rx_queues, 829 dev->data->dev_conf.lpbk_mode, rsshf); 830 831 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 832 ret = nicvf_rss_term(nic); 833 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 834 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf); 835 if (ret) 836 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret); 837 838 return ret; 839 } 840 841 static int 842 nicvf_configure_rss_reta(struct rte_eth_dev *dev) 843 { 844 struct nicvf *nic = nicvf_pmd_priv(dev); 845 unsigned int idx, qmap_size; 846 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT]; 847 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE]; 848 849 if (nic->cpi_alg != CPI_ALG_NONE) 850 return -EINVAL; 851 852 /* Prepare queue map */ 853 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) { 854 if (dev->data->rx_queue_state[idx] == 855 RTE_ETH_QUEUE_STATE_STARTED) 856 qmap[qmap_size++] = idx; 857 } 858 859 /* Update default RSS RETA */ 860 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++) 861 default_reta[idx] = qmap[idx % qmap_size]; 862 863 return nicvf_rss_reta_update(nic, default_reta, 864 NIC_MAX_RSS_IDR_TBL_SIZE); 865 } 866 867 static void 868 nicvf_dev_tx_queue_release(void *sq) 869 { 870 struct nicvf_txq *txq; 871 872 PMD_INIT_FUNC_TRACE(); 873 874 txq = (struct nicvf_txq *)sq; 875 if (txq) { 876 if (txq->txbuffs != NULL) { 877 nicvf_tx_queue_release_mbufs(txq); 878 rte_free(txq->txbuffs); 879 txq->txbuffs = NULL; 880 } 881 rte_free(txq); 882 } 883 } 884 885 static void 886 nicvf_set_tx_function(struct rte_eth_dev *dev) 887 { 888 struct nicvf_txq *txq = NULL; 889 size_t i; 890 bool multiseg = false; 891 892 for (i = 0; i < dev->data->nb_tx_queues; i++) { 893 txq = dev->data->tx_queues[i]; 894 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) { 895 multiseg = true; 896 break; 897 } 898 } 899 900 /* Use a simple Tx queue (no offloads, no multi segs) if possible */ 901 if (multiseg) { 902 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback"); 903 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg; 904 } else { 905 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback"); 906 dev->tx_pkt_burst = nicvf_xmit_pkts; 907 } 908 909 if (!txq) 910 return; 911 912 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers) 913 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method"); 914 else 915 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method"); 916 } 917 918 static void 919 nicvf_set_rx_function(struct rte_eth_dev *dev) 920 { 921 if (dev->data->scattered_rx) { 922 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback"); 923 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg; 924 } else { 925 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback"); 926 dev->rx_pkt_burst = nicvf_recv_pkts; 927 } 928 } 929 930 static int 931 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 932 uint16_t nb_desc, unsigned int socket_id, 933 const struct rte_eth_txconf *tx_conf) 934 { 935 uint16_t tx_free_thresh; 936 bool is_single_pool; 937 struct nicvf_txq *txq; 938 struct nicvf *nic = nicvf_pmd_priv(dev); 939 uint64_t offloads; 940 941 PMD_INIT_FUNC_TRACE(); 942 943 if (qidx >= MAX_SND_QUEUES_PER_QS) 944 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1]; 945 946 qidx = qidx % MAX_SND_QUEUES_PER_QS; 947 948 /* Socket id check */ 949 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 950 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 951 socket_id, nic->node); 952 953 /* Tx deferred start is not supported */ 954 if (tx_conf->tx_deferred_start) { 955 PMD_INIT_LOG(ERR, "Tx deferred start not supported"); 956 return -EINVAL; 957 } 958 959 /* Roundup nb_desc to available qsize and validate max number of desc */ 960 nb_desc = nicvf_qsize_sq_roundup(nb_desc); 961 if (nb_desc == 0) { 962 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize"); 963 return -EINVAL; 964 } 965 966 /* Validate tx_free_thresh */ 967 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ? 968 tx_conf->tx_free_thresh : 969 NICVF_DEFAULT_TX_FREE_THRESH); 970 971 if (tx_free_thresh > (nb_desc) || 972 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) { 973 PMD_INIT_LOG(ERR, 974 "tx_free_thresh must be less than the number of TX " 975 "descriptors. (tx_free_thresh=%u port=%d " 976 "queue=%d)", (unsigned int)tx_free_thresh, 977 (int)dev->data->port_id, (int)qidx); 978 return -EINVAL; 979 } 980 981 /* Free memory prior to re-allocation if needed. */ 982 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 983 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 984 nicvf_netdev_qidx(nic, qidx)); 985 nicvf_dev_tx_queue_release( 986 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]); 987 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 988 } 989 990 /* Allocating tx queue data structure */ 991 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq), 992 RTE_CACHE_LINE_SIZE, nic->node); 993 if (txq == NULL) { 994 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", 995 nicvf_netdev_qidx(nic, qidx)); 996 return -ENOMEM; 997 } 998 999 txq->nic = nic; 1000 txq->queue_id = qidx; 1001 txq->tx_free_thresh = tx_free_thresh; 1002 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD; 1003 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR; 1004 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1005 txq->offloads = offloads; 1006 1007 is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); 1008 1009 /* Choose optimum free threshold value for multipool case */ 1010 if (!is_single_pool) { 1011 txq->tx_free_thresh = (uint16_t) 1012 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ? 1013 NICVF_TX_FREE_MPOOL_THRESH : 1014 tx_conf->tx_free_thresh); 1015 txq->pool_free = nicvf_multi_pool_free_xmited_buffers; 1016 } else { 1017 txq->pool_free = nicvf_single_pool_free_xmited_buffers; 1018 } 1019 1020 /* Allocate software ring */ 1021 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs", 1022 nb_desc * sizeof(struct rte_mbuf *), 1023 RTE_CACHE_LINE_SIZE, nic->node); 1024 1025 if (txq->txbuffs == NULL) { 1026 nicvf_dev_tx_queue_release(txq); 1027 return -ENOMEM; 1028 } 1029 1030 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) { 1031 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx); 1032 nicvf_dev_tx_queue_release(txq); 1033 return -ENOMEM; 1034 } 1035 1036 nicvf_tx_queue_reset(txq); 1037 1038 PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p" 1039 " phys=0x%" PRIx64 " offloads=0x%" PRIx64, 1040 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc, 1041 txq->phys, txq->offloads); 1042 1043 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq; 1044 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1045 RTE_ETH_QUEUE_STATE_STOPPED; 1046 return 0; 1047 } 1048 1049 static inline void 1050 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq) 1051 { 1052 uint32_t rxq_cnt; 1053 uint32_t nb_pkts, released_pkts = 0; 1054 uint32_t refill_cnt = 0; 1055 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH]; 1056 1057 if (dev->rx_pkt_burst == NULL) 1058 return; 1059 1060 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev, 1061 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) { 1062 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts, 1063 NICVF_MAX_RX_FREE_THRESH); 1064 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt); 1065 while (nb_pkts) { 1066 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]); 1067 released_pkts++; 1068 } 1069 } 1070 1071 1072 refill_cnt += nicvf_dev_rbdr_refill(dev, 1073 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)); 1074 1075 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d", 1076 released_pkts, refill_cnt); 1077 } 1078 1079 static void 1080 nicvf_rx_queue_reset(struct nicvf_rxq *rxq) 1081 { 1082 rxq->head = 0; 1083 rxq->available_space = 0; 1084 rxq->recv_buffers = 0; 1085 } 1086 1087 static inline int 1088 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1089 uint16_t qidx) 1090 { 1091 struct nicvf_rxq *rxq; 1092 int ret; 1093 1094 assert(qidx < MAX_RCV_QUEUES_PER_QS); 1095 1096 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1097 RTE_ETH_QUEUE_STATE_STARTED) 1098 return 0; 1099 1100 /* Update rbdr pointer to all rxq */ 1101 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1102 rxq->shared_rbdr = nic->rbdr; 1103 1104 ret = nicvf_qset_rq_config(nic, qidx, rxq); 1105 if (ret) { 1106 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d", 1107 nic->vf_id, qidx, ret); 1108 goto config_rq_error; 1109 } 1110 ret = nicvf_qset_cq_config(nic, qidx, rxq); 1111 if (ret) { 1112 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d", 1113 nic->vf_id, qidx, ret); 1114 goto config_cq_error; 1115 } 1116 1117 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1118 RTE_ETH_QUEUE_STATE_STARTED; 1119 return 0; 1120 1121 config_cq_error: 1122 nicvf_qset_cq_reclaim(nic, qidx); 1123 config_rq_error: 1124 nicvf_qset_rq_reclaim(nic, qidx); 1125 return ret; 1126 } 1127 1128 static inline int 1129 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic, 1130 uint16_t qidx) 1131 { 1132 struct nicvf_rxq *rxq; 1133 int ret, other_error; 1134 1135 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] == 1136 RTE_ETH_QUEUE_STATE_STOPPED) 1137 return 0; 1138 1139 ret = nicvf_qset_rq_reclaim(nic, qidx); 1140 if (ret) 1141 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d", 1142 nic->vf_id, qidx, ret); 1143 1144 other_error = ret; 1145 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]; 1146 nicvf_rx_queue_release_mbufs(dev, rxq); 1147 nicvf_rx_queue_reset(rxq); 1148 1149 ret = nicvf_qset_cq_reclaim(nic, qidx); 1150 if (ret) 1151 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d", 1152 nic->vf_id, qidx, ret); 1153 1154 other_error |= ret; 1155 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1156 RTE_ETH_QUEUE_STATE_STOPPED; 1157 return other_error; 1158 } 1159 1160 static void 1161 nicvf_dev_rx_queue_release(void *rx_queue) 1162 { 1163 PMD_INIT_FUNC_TRACE(); 1164 1165 rte_free(rx_queue); 1166 } 1167 1168 static int 1169 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1170 { 1171 struct nicvf *nic = nicvf_pmd_priv(dev); 1172 int ret; 1173 1174 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1175 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)]; 1176 1177 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1178 1179 ret = nicvf_vf_start_rx_queue(dev, nic, qidx); 1180 if (ret) 1181 return ret; 1182 1183 ret = nicvf_configure_cpi(dev); 1184 if (ret) 1185 return ret; 1186 1187 return nicvf_configure_rss_reta(dev); 1188 } 1189 1190 static int 1191 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1192 { 1193 int ret; 1194 struct nicvf *nic = nicvf_pmd_priv(dev); 1195 1196 if (qidx >= MAX_SND_QUEUES_PER_QS) 1197 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1198 1199 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1200 1201 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx); 1202 ret |= nicvf_configure_cpi(dev); 1203 ret |= nicvf_configure_rss_reta(dev); 1204 return ret; 1205 } 1206 1207 static int 1208 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 1209 { 1210 struct nicvf *nic = nicvf_pmd_priv(dev); 1211 1212 if (qidx >= MAX_SND_QUEUES_PER_QS) 1213 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1214 1215 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1216 1217 return nicvf_vf_start_tx_queue(dev, nic, qidx); 1218 } 1219 1220 static int 1221 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 1222 { 1223 struct nicvf *nic = nicvf_pmd_priv(dev); 1224 1225 if (qidx >= MAX_SND_QUEUES_PER_QS) 1226 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)]; 1227 1228 qidx = qidx % MAX_SND_QUEUES_PER_QS; 1229 1230 return nicvf_vf_stop_tx_queue(dev, nic, qidx); 1231 } 1232 1233 static inline void 1234 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq) 1235 { 1236 uintptr_t p; 1237 struct rte_mbuf mb_def; 1238 struct nicvf *nic = rxq->nic; 1239 1240 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8); 1241 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0); 1242 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) - 1243 offsetof(struct rte_mbuf, data_off) != 2); 1244 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) - 1245 offsetof(struct rte_mbuf, data_off) != 4); 1246 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) - 1247 offsetof(struct rte_mbuf, data_off) != 6); 1248 mb_def.nb_segs = 1; 1249 mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes); 1250 mb_def.port = rxq->port_id; 1251 rte_mbuf_refcnt_set(&mb_def, 1); 1252 1253 /* Prevent compiler reordering: rearm_data covers previous fields */ 1254 rte_compiler_barrier(); 1255 p = (uintptr_t)&mb_def.rearm_data; 1256 rxq->mbuf_initializer.value = *(uint64_t *)p; 1257 } 1258 1259 static int 1260 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx, 1261 uint16_t nb_desc, unsigned int socket_id, 1262 const struct rte_eth_rxconf *rx_conf, 1263 struct rte_mempool *mp) 1264 { 1265 uint16_t rx_free_thresh; 1266 struct nicvf_rxq *rxq; 1267 struct nicvf *nic = nicvf_pmd_priv(dev); 1268 uint64_t offloads; 1269 uint32_t buffsz; 1270 struct rte_pktmbuf_pool_private *mbp_priv; 1271 1272 PMD_INIT_FUNC_TRACE(); 1273 1274 /* First skip check */ 1275 mbp_priv = rte_mempool_get_priv(mp); 1276 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1277 if (buffsz < (uint32_t)(nic->skip_bytes)) { 1278 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size"); 1279 return -EINVAL; 1280 } 1281 1282 if (qidx >= MAX_RCV_QUEUES_PER_QS) 1283 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1]; 1284 1285 qidx = qidx % MAX_RCV_QUEUES_PER_QS; 1286 1287 /* Socket id check */ 1288 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node) 1289 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d", 1290 socket_id, nic->node); 1291 1292 /* Mempool memory must be contiguous, so must be one memory segment*/ 1293 if (mp->nb_mem_chunks != 1) { 1294 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages"); 1295 return -EINVAL; 1296 } 1297 1298 /* Mempool memory must be physically contiguous */ 1299 if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) { 1300 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous"); 1301 return -EINVAL; 1302 } 1303 1304 /* Rx deferred start is not supported */ 1305 if (rx_conf->rx_deferred_start) { 1306 PMD_INIT_LOG(ERR, "Rx deferred start not supported"); 1307 return -EINVAL; 1308 } 1309 1310 /* Roundup nb_desc to available qsize and validate max number of desc */ 1311 nb_desc = nicvf_qsize_cq_roundup(nb_desc); 1312 if (nb_desc == 0) { 1313 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize"); 1314 return -EINVAL; 1315 } 1316 1317 1318 /* Check rx_free_thresh upper bound */ 1319 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ? 1320 rx_conf->rx_free_thresh : 1321 NICVF_DEFAULT_RX_FREE_THRESH); 1322 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH || 1323 rx_free_thresh >= nb_desc * .75) { 1324 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d", 1325 rx_free_thresh); 1326 return -EINVAL; 1327 } 1328 1329 /* Free memory prior to re-allocation if needed */ 1330 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) { 1331 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d", 1332 nicvf_netdev_qidx(nic, qidx)); 1333 nicvf_dev_rx_queue_release( 1334 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]); 1335 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL; 1336 } 1337 1338 /* Allocate rxq memory */ 1339 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq), 1340 RTE_CACHE_LINE_SIZE, nic->node); 1341 if (rxq == NULL) { 1342 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", 1343 nicvf_netdev_qidx(nic, qidx)); 1344 return -ENOMEM; 1345 } 1346 1347 rxq->nic = nic; 1348 rxq->pool = mp; 1349 rxq->queue_id = qidx; 1350 rxq->port_id = dev->data->port_id; 1351 rxq->rx_free_thresh = rx_free_thresh; 1352 rxq->rx_drop_en = rx_conf->rx_drop_en; 1353 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS; 1354 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR; 1355 rxq->precharge_cnt = 0; 1356 1357 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2) 1358 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD; 1359 else 1360 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD; 1361 1362 nicvf_rxq_mbuf_setup(rxq); 1363 1364 /* Alloc completion queue */ 1365 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) { 1366 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id); 1367 nicvf_dev_rx_queue_release(rxq); 1368 return -ENOMEM; 1369 } 1370 1371 nicvf_rx_queue_reset(rxq); 1372 1373 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads; 1374 PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)" 1375 " phy=0x%" PRIx64 " offloads=0x%" PRIx64, 1376 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc, 1377 rte_mempool_avail_count(mp), rxq->phys, offloads); 1378 1379 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq; 1380 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] = 1381 RTE_ETH_QUEUE_STATE_STOPPED; 1382 return 0; 1383 } 1384 1385 static void 1386 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1387 { 1388 struct nicvf *nic = nicvf_pmd_priv(dev); 1389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1390 1391 PMD_INIT_FUNC_TRACE(); 1392 1393 /* Autonegotiation may be disabled */ 1394 dev_info->speed_capa = ETH_LINK_SPEED_FIXED; 1395 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M | 1396 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 1397 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF) 1398 dev_info->speed_capa |= ETH_LINK_SPEED_40G; 1399 1400 dev_info->min_rx_bufsize = ETHER_MIN_MTU; 1401 dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN; 1402 dev_info->max_rx_queues = 1403 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1404 dev_info->max_tx_queues = 1405 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1); 1406 dev_info->max_mac_addrs = 1; 1407 dev_info->max_vfs = pci_dev->max_vfs; 1408 1409 dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1410 dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1411 dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA; 1412 dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA; 1413 1414 dev_info->reta_size = nic->rss_info.rss_size; 1415 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE; 1416 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1; 1417 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) 1418 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL; 1419 1420 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1421 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH, 1422 .rx_drop_en = 0, 1423 .offloads = DEV_RX_OFFLOAD_CRC_STRIP, 1424 }; 1425 1426 dev_info->default_txconf = (struct rte_eth_txconf) { 1427 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH, 1428 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE | 1429 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1430 DEV_TX_OFFLOAD_UDP_CKSUM | 1431 DEV_TX_OFFLOAD_TCP_CKSUM, 1432 }; 1433 } 1434 1435 static nicvf_iova_addr_t 1436 rbdr_rte_mempool_get(void *dev, void *opaque) 1437 { 1438 uint16_t qidx; 1439 uintptr_t mbuf; 1440 struct nicvf_rxq *rxq; 1441 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev; 1442 struct nicvf *nic = (struct nicvf *)opaque; 1443 uint16_t rx_start, rx_end; 1444 1445 /* Get queue ranges for this VF */ 1446 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end); 1447 1448 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1449 rxq = eth_dev->data->rx_queues[qidx]; 1450 /* Maintain equal buffer count across all pools */ 1451 if (rxq->precharge_cnt >= rxq->qlen_mask) 1452 continue; 1453 rxq->precharge_cnt++; 1454 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool); 1455 if (mbuf) 1456 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off); 1457 } 1458 return 0; 1459 } 1460 1461 static int 1462 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz) 1463 { 1464 int ret; 1465 uint16_t qidx, data_off; 1466 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs; 1467 uint64_t mbuf_phys_off = 0; 1468 struct nicvf_rxq *rxq; 1469 struct rte_mbuf *mbuf; 1470 uint16_t rx_start, rx_end; 1471 uint16_t tx_start, tx_end; 1472 bool vlan_strip; 1473 1474 PMD_INIT_FUNC_TRACE(); 1475 1476 /* Userspace process exited without proper shutdown in last run */ 1477 if (nicvf_qset_rbdr_active(nic, 0)) 1478 nicvf_vf_stop(dev, nic, false); 1479 1480 /* Get queue ranges for this VF */ 1481 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1482 1483 /* 1484 * Thunderx nicvf PMD can support more than one pool per port only when 1485 * 1) Data payload size is same across all the pools in given port 1486 * AND 1487 * 2) All mbuffs in the pools are from the same hugepage 1488 * AND 1489 * 3) Mbuff metadata size is same across all the pools in given port 1490 * 1491 * This is to support existing application that uses multiple pool/port. 1492 * But, the purpose of using multipool for QoS will not be addressed. 1493 * 1494 */ 1495 1496 /* Validate mempool attributes */ 1497 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1498 rxq = dev->data->rx_queues[qidx]; 1499 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool); 1500 mbuf = rte_pktmbuf_alloc(rxq->pool); 1501 if (mbuf == NULL) { 1502 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d " 1503 "pool=%s", 1504 nic->vf_id, qidx, rxq->pool->name); 1505 return -ENOMEM; 1506 } 1507 data_off = nicvf_mbuff_meta_length(mbuf); 1508 data_off += RTE_PKTMBUF_HEADROOM; 1509 rte_pktmbuf_free(mbuf); 1510 1511 if (data_off % RTE_CACHE_LINE_SIZE) { 1512 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d", 1513 rxq->pool->name, data_off, 1514 data_off % RTE_CACHE_LINE_SIZE); 1515 return -EINVAL; 1516 } 1517 rxq->mbuf_phys_off -= data_off; 1518 rxq->mbuf_phys_off -= nic->skip_bytes; 1519 1520 if (mbuf_phys_off == 0) 1521 mbuf_phys_off = rxq->mbuf_phys_off; 1522 if (mbuf_phys_off != rxq->mbuf_phys_off) { 1523 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %" 1524 PRIx64, rxq->pool->name, nic->vf_id, 1525 mbuf_phys_off); 1526 return -EINVAL; 1527 } 1528 } 1529 1530 /* Check the level of buffers in the pool */ 1531 total_rxq_desc = 0; 1532 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1533 rxq = dev->data->rx_queues[qidx]; 1534 /* Count total numbers of rxq descs */ 1535 total_rxq_desc += rxq->qlen_mask + 1; 1536 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh; 1537 exp_buffs *= dev->data->nb_rx_queues; 1538 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) { 1539 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)", 1540 rxq->pool->name, 1541 rte_mempool_avail_count(rxq->pool), 1542 exp_buffs); 1543 return -ENOENT; 1544 } 1545 } 1546 1547 /* Check RBDR desc overflow */ 1548 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1549 if (ret == 0) { 1550 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc " 1551 "VF%d", nic->vf_id); 1552 return -ENOMEM; 1553 } 1554 1555 /* Enable qset */ 1556 ret = nicvf_qset_config(nic); 1557 if (ret) { 1558 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret, 1559 nic->vf_id); 1560 return ret; 1561 } 1562 1563 /* Allocate RBDR and RBDR ring desc */ 1564 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc); 1565 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz); 1566 if (ret) { 1567 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc " 1568 "VF%d", nic->vf_id); 1569 goto qset_reclaim; 1570 } 1571 1572 /* Enable and configure RBDR registers */ 1573 ret = nicvf_qset_rbdr_config(nic, 0); 1574 if (ret) { 1575 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret, 1576 nic->vf_id); 1577 goto qset_rbdr_free; 1578 } 1579 1580 /* Fill rte_mempool buffers in RBDR pool and precharge it */ 1581 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get, 1582 total_rxq_desc); 1583 if (ret) { 1584 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret, 1585 nic->vf_id); 1586 goto qset_rbdr_reclaim; 1587 } 1588 1589 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d", 1590 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id); 1591 1592 /* Configure VLAN Strip */ 1593 vlan_strip = !!(dev->data->dev_conf.rxmode.offloads & 1594 DEV_RX_OFFLOAD_VLAN_STRIP); 1595 nicvf_vlan_hw_strip(nic, vlan_strip); 1596 1597 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data 1598 * to the 64bit memory address. 1599 * The alignment creates a hole in mbuf(between the end of headroom and 1600 * packet data start). The new revision of the HW provides an option to 1601 * disable the L3 alignment feature and make mbuf layout looks 1602 * more like other NICs. For better application compatibility, disabling 1603 * l3 alignment feature on the hardware revisions it supports 1604 */ 1605 nicvf_apad_config(nic, false); 1606 1607 /* Get queue ranges for this VF */ 1608 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1609 1610 /* Configure TX queues */ 1611 for (qidx = tx_start; qidx <= tx_end; qidx++) { 1612 ret = nicvf_vf_start_tx_queue(dev, nic, 1613 qidx % MAX_SND_QUEUES_PER_QS); 1614 if (ret) 1615 goto start_txq_error; 1616 } 1617 1618 /* Configure RX queues */ 1619 for (qidx = rx_start; qidx <= rx_end; qidx++) { 1620 ret = nicvf_vf_start_rx_queue(dev, nic, 1621 qidx % MAX_RCV_QUEUES_PER_QS); 1622 if (ret) 1623 goto start_rxq_error; 1624 } 1625 1626 if (!nic->sqs_mode) { 1627 /* Configure CPI algorithm */ 1628 ret = nicvf_configure_cpi(dev); 1629 if (ret) 1630 goto start_txq_error; 1631 1632 ret = nicvf_mbox_get_rss_size(nic); 1633 if (ret) { 1634 PMD_INIT_LOG(ERR, "Failed to get rss table size"); 1635 goto qset_rss_error; 1636 } 1637 1638 /* Configure RSS */ 1639 ret = nicvf_configure_rss(dev); 1640 if (ret) 1641 goto qset_rss_error; 1642 } 1643 1644 /* Done; Let PF make the BGX's RX and TX switches to ON position */ 1645 nicvf_mbox_cfg_done(nic); 1646 return 0; 1647 1648 qset_rss_error: 1649 nicvf_rss_term(nic); 1650 start_rxq_error: 1651 for (qidx = rx_start; qidx <= rx_end; qidx++) 1652 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1653 start_txq_error: 1654 for (qidx = tx_start; qidx <= tx_end; qidx++) 1655 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1656 qset_rbdr_reclaim: 1657 nicvf_qset_rbdr_reclaim(nic, 0); 1658 nicvf_rbdr_release_mbufs(dev, nic); 1659 qset_rbdr_free: 1660 if (nic->rbdr) { 1661 rte_free(nic->rbdr); 1662 nic->rbdr = NULL; 1663 } 1664 qset_reclaim: 1665 nicvf_qset_reclaim(nic); 1666 return ret; 1667 } 1668 1669 static int 1670 nicvf_dev_start(struct rte_eth_dev *dev) 1671 { 1672 uint16_t qidx; 1673 int ret; 1674 size_t i; 1675 struct nicvf *nic = nicvf_pmd_priv(dev); 1676 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 1677 uint16_t mtu; 1678 uint32_t buffsz = 0, rbdrsz = 0; 1679 struct rte_pktmbuf_pool_private *mbp_priv; 1680 struct nicvf_rxq *rxq; 1681 1682 PMD_INIT_FUNC_TRACE(); 1683 1684 /* This function must be called for a primary device */ 1685 assert_primary(nic); 1686 1687 /* Validate RBDR buff size */ 1688 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) { 1689 rxq = dev->data->rx_queues[qidx]; 1690 mbp_priv = rte_mempool_get_priv(rxq->pool); 1691 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; 1692 if (buffsz % 128) { 1693 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128"); 1694 return -EINVAL; 1695 } 1696 if (rbdrsz == 0) 1697 rbdrsz = buffsz; 1698 if (rbdrsz != buffsz) { 1699 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)", 1700 qidx, rbdrsz, buffsz); 1701 return -EINVAL; 1702 } 1703 } 1704 1705 /* Configure loopback */ 1706 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode); 1707 if (ret) { 1708 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret); 1709 return ret; 1710 } 1711 1712 /* Reset all statistics counters attached to this port */ 1713 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF); 1714 if (ret) { 1715 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret); 1716 return ret; 1717 } 1718 1719 /* Setup scatter mode if needed by jumbo */ 1720 if (dev->data->dev_conf.rxmode.max_rx_pkt_len + 1721 2 * VLAN_TAG_SIZE > buffsz) 1722 dev->data->scattered_rx = 1; 1723 if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0) 1724 dev->data->scattered_rx = 1; 1725 1726 /* Setup MTU based on max_rx_pkt_len or default */ 1727 mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ? 1728 dev->data->dev_conf.rxmode.max_rx_pkt_len 1729 - ETHER_HDR_LEN : ETHER_MTU; 1730 1731 if (nicvf_dev_set_mtu(dev, mtu)) { 1732 PMD_INIT_LOG(ERR, "Failed to set default mtu size"); 1733 return -EBUSY; 1734 } 1735 1736 ret = nicvf_vf_start(dev, nic, rbdrsz); 1737 if (ret != 0) 1738 return ret; 1739 1740 for (i = 0; i < nic->sqs_count; i++) { 1741 assert(nic->snicvf[i]); 1742 1743 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz); 1744 if (ret != 0) 1745 return ret; 1746 } 1747 1748 /* Configure callbacks based on scatter mode */ 1749 nicvf_set_tx_function(dev); 1750 nicvf_set_rx_function(dev); 1751 1752 return 0; 1753 } 1754 1755 static void 1756 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup) 1757 { 1758 size_t i; 1759 int ret; 1760 struct nicvf *nic = nicvf_pmd_priv(dev); 1761 1762 PMD_INIT_FUNC_TRACE(); 1763 1764 /* Teardown secondary vf first */ 1765 for (i = 0; i < nic->sqs_count; i++) { 1766 if (!nic->snicvf[i]) 1767 continue; 1768 1769 nicvf_vf_stop(dev, nic->snicvf[i], cleanup); 1770 } 1771 1772 /* Stop the primary VF now */ 1773 nicvf_vf_stop(dev, nic, cleanup); 1774 1775 /* Disable loopback */ 1776 ret = nicvf_loopback_config(nic, 0); 1777 if (ret) 1778 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret); 1779 1780 /* Reclaim CPI configuration */ 1781 ret = nicvf_mbox_config_cpi(nic, 0); 1782 if (ret) 1783 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret); 1784 } 1785 1786 static void 1787 nicvf_dev_stop(struct rte_eth_dev *dev) 1788 { 1789 PMD_INIT_FUNC_TRACE(); 1790 1791 nicvf_dev_stop_cleanup(dev, false); 1792 } 1793 1794 static void 1795 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup) 1796 { 1797 int ret; 1798 uint16_t qidx; 1799 uint16_t tx_start, tx_end; 1800 uint16_t rx_start, rx_end; 1801 1802 PMD_INIT_FUNC_TRACE(); 1803 1804 if (cleanup) { 1805 /* Let PF make the BGX's RX and TX switches to OFF position */ 1806 nicvf_mbox_shutdown(nic); 1807 } 1808 1809 /* Disable VLAN Strip */ 1810 nicvf_vlan_hw_strip(nic, 0); 1811 1812 /* Get queue ranges for this VF */ 1813 nicvf_tx_range(dev, nic, &tx_start, &tx_end); 1814 1815 for (qidx = tx_start; qidx <= tx_end; qidx++) 1816 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS); 1817 1818 /* Get queue ranges for this VF */ 1819 nicvf_rx_range(dev, nic, &rx_start, &rx_end); 1820 1821 /* Reclaim rq */ 1822 for (qidx = rx_start; qidx <= rx_end; qidx++) 1823 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS); 1824 1825 /* Reclaim RBDR */ 1826 ret = nicvf_qset_rbdr_reclaim(nic, 0); 1827 if (ret) 1828 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret); 1829 1830 /* Move all charged buffers in RBDR back to pool */ 1831 if (nic->rbdr != NULL) 1832 nicvf_rbdr_release_mbufs(dev, nic); 1833 1834 /* Disable qset */ 1835 ret = nicvf_qset_reclaim(nic); 1836 if (ret) 1837 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret); 1838 1839 /* Disable all interrupts */ 1840 nicvf_disable_all_interrupts(nic); 1841 1842 /* Free RBDR SW structure */ 1843 if (nic->rbdr) { 1844 rte_free(nic->rbdr); 1845 nic->rbdr = NULL; 1846 } 1847 } 1848 1849 static void 1850 nicvf_dev_close(struct rte_eth_dev *dev) 1851 { 1852 size_t i; 1853 struct nicvf *nic = nicvf_pmd_priv(dev); 1854 1855 PMD_INIT_FUNC_TRACE(); 1856 1857 nicvf_dev_stop_cleanup(dev, true); 1858 nicvf_periodic_alarm_stop(nicvf_interrupt, dev); 1859 1860 for (i = 0; i < nic->sqs_count; i++) { 1861 if (!nic->snicvf[i]) 1862 continue; 1863 1864 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]); 1865 } 1866 } 1867 1868 static int 1869 nicvf_request_sqs(struct nicvf *nic) 1870 { 1871 size_t i; 1872 1873 assert_primary(nic); 1874 assert(nic->sqs_count > 0); 1875 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1876 1877 /* Set no of Rx/Tx queues in each of the SQsets */ 1878 for (i = 0; i < nic->sqs_count; i++) { 1879 if (nicvf_svf_empty()) 1880 rte_panic("Cannot assign sufficient number of " 1881 "secondary queues to primary VF%" PRIu8 "\n", 1882 nic->vf_id); 1883 1884 nic->snicvf[i] = nicvf_svf_pop(); 1885 nic->snicvf[i]->sqs_id = i; 1886 } 1887 1888 return nicvf_mbox_request_sqs(nic); 1889 } 1890 1891 static int 1892 nicvf_dev_configure(struct rte_eth_dev *dev) 1893 { 1894 struct rte_eth_dev_data *data = dev->data; 1895 struct rte_eth_conf *conf = &data->dev_conf; 1896 struct rte_eth_rxmode *rxmode = &conf->rxmode; 1897 struct rte_eth_txmode *txmode = &conf->txmode; 1898 struct nicvf *nic = nicvf_pmd_priv(dev); 1899 uint8_t cqcount; 1900 1901 PMD_INIT_FUNC_TRACE(); 1902 1903 if (!rte_eal_has_hugepages()) { 1904 PMD_INIT_LOG(INFO, "Huge page is not configured"); 1905 return -EINVAL; 1906 } 1907 1908 /* KEEP_CRC offload flag is not supported by PMD 1909 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed 1910 */ 1911 if (rte_eth_dev_must_keep_crc(rxmode->offloads)) { 1912 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip"); 1913 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP; 1914 } 1915 1916 if (txmode->mq_mode) { 1917 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported"); 1918 return -EINVAL; 1919 } 1920 1921 if (rxmode->mq_mode != ETH_MQ_RX_NONE && 1922 rxmode->mq_mode != ETH_MQ_RX_RSS) { 1923 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode); 1924 return -EINVAL; 1925 } 1926 1927 if (rxmode->split_hdr_size) { 1928 PMD_INIT_LOG(INFO, "Rxmode does not support split header"); 1929 return -EINVAL; 1930 } 1931 1932 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 1933 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported"); 1934 return -EINVAL; 1935 } 1936 1937 if (conf->dcb_capability_en) { 1938 PMD_INIT_LOG(INFO, "DCB enable not supported"); 1939 return -EINVAL; 1940 } 1941 1942 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { 1943 PMD_INIT_LOG(INFO, "Flow director not supported"); 1944 return -EINVAL; 1945 } 1946 1947 assert_primary(nic); 1948 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS); 1949 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues); 1950 if (cqcount > MAX_RCV_QUEUES_PER_QS) { 1951 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS); 1952 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1; 1953 } else { 1954 nic->sqs_count = 0; 1955 } 1956 1957 assert(nic->sqs_count <= MAX_SQS_PER_VF); 1958 1959 if (nic->sqs_count > 0) { 1960 if (nicvf_request_sqs(nic)) { 1961 rte_panic("Cannot assign sufficient number of " 1962 "secondary queues to PORT%d VF%" PRIu8 "\n", 1963 dev->data->port_id, nic->vf_id); 1964 } 1965 } 1966 1967 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64, 1968 dev->data->port_id, nicvf_hw_cap(nic)); 1969 1970 return 0; 1971 } 1972 1973 /* Initialize and register driver with DPDK Application */ 1974 static const struct eth_dev_ops nicvf_eth_dev_ops = { 1975 .dev_configure = nicvf_dev_configure, 1976 .dev_start = nicvf_dev_start, 1977 .dev_stop = nicvf_dev_stop, 1978 .link_update = nicvf_dev_link_update, 1979 .dev_close = nicvf_dev_close, 1980 .stats_get = nicvf_dev_stats_get, 1981 .stats_reset = nicvf_dev_stats_reset, 1982 .promiscuous_enable = nicvf_dev_promisc_enable, 1983 .dev_infos_get = nicvf_dev_info_get, 1984 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get, 1985 .mtu_set = nicvf_dev_set_mtu, 1986 .reta_update = nicvf_dev_reta_update, 1987 .reta_query = nicvf_dev_reta_query, 1988 .rss_hash_update = nicvf_dev_rss_hash_update, 1989 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get, 1990 .rx_queue_start = nicvf_dev_rx_queue_start, 1991 .rx_queue_stop = nicvf_dev_rx_queue_stop, 1992 .tx_queue_start = nicvf_dev_tx_queue_start, 1993 .tx_queue_stop = nicvf_dev_tx_queue_stop, 1994 .rx_queue_setup = nicvf_dev_rx_queue_setup, 1995 .rx_queue_release = nicvf_dev_rx_queue_release, 1996 .rx_queue_count = nicvf_dev_rx_queue_count, 1997 .tx_queue_setup = nicvf_dev_tx_queue_setup, 1998 .tx_queue_release = nicvf_dev_tx_queue_release, 1999 .get_reg = nicvf_dev_get_regs, 2000 }; 2001 2002 static inline int 2003 nicvf_set_first_skip(struct rte_eth_dev *dev) 2004 { 2005 int bytes_to_skip = 0; 2006 int ret = 0; 2007 unsigned int i; 2008 struct rte_kvargs *kvlist; 2009 static const char *const skip[] = { 2010 SKIP_DATA_BYTES, 2011 NULL}; 2012 struct nicvf *nic = nicvf_pmd_priv(dev); 2013 2014 if (!dev->device->devargs) { 2015 nicvf_first_skip_config(nic, 0); 2016 return ret; 2017 } 2018 2019 kvlist = rte_kvargs_parse(dev->device->devargs->args, skip); 2020 if (!kvlist) 2021 return -EINVAL; 2022 2023 if (kvlist->count == 0) 2024 goto exit; 2025 2026 for (i = 0; i != kvlist->count; ++i) { 2027 const struct rte_kvargs_pair *pair = &kvlist->pairs[i]; 2028 2029 if (!strcmp(pair->key, SKIP_DATA_BYTES)) 2030 bytes_to_skip = atoi(pair->value); 2031 } 2032 2033 /*128 bytes amounts to one cache line*/ 2034 if (bytes_to_skip >= 0 && bytes_to_skip < 128) { 2035 if (!(bytes_to_skip % 8)) { 2036 nicvf_first_skip_config(nic, (bytes_to_skip / 8)); 2037 nic->skip_bytes = bytes_to_skip; 2038 goto kvlist_free; 2039 } else { 2040 PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8"); 2041 ret = -EINVAL; 2042 goto exit; 2043 } 2044 } else { 2045 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128"); 2046 ret = -EINVAL; 2047 goto exit; 2048 } 2049 exit: 2050 nicvf_first_skip_config(nic, 0); 2051 kvlist_free: 2052 rte_kvargs_free(kvlist); 2053 return ret; 2054 } 2055 static int 2056 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) 2057 { 2058 int ret; 2059 struct rte_pci_device *pci_dev; 2060 struct nicvf *nic = nicvf_pmd_priv(eth_dev); 2061 2062 PMD_INIT_FUNC_TRACE(); 2063 2064 eth_dev->dev_ops = &nicvf_eth_dev_ops; 2065 2066 /* For secondary processes, the primary has done all the work */ 2067 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2068 if (nic) { 2069 /* Setup callbacks for secondary process */ 2070 nicvf_set_tx_function(eth_dev); 2071 nicvf_set_rx_function(eth_dev); 2072 return 0; 2073 } else { 2074 /* If nic == NULL than it is secondary function 2075 * so ethdev need to be released by caller */ 2076 return ENOTSUP; 2077 } 2078 } 2079 2080 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2081 rte_eth_copy_pci_info(eth_dev, pci_dev); 2082 2083 nic->device_id = pci_dev->id.device_id; 2084 nic->vendor_id = pci_dev->id.vendor_id; 2085 nic->subsystem_device_id = pci_dev->id.subsystem_device_id; 2086 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id; 2087 2088 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u", 2089 pci_dev->id.vendor_id, pci_dev->id.device_id, 2090 pci_dev->addr.domain, pci_dev->addr.bus, 2091 pci_dev->addr.devid, pci_dev->addr.function); 2092 2093 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr; 2094 if (!nic->reg_base) { 2095 PMD_INIT_LOG(ERR, "Failed to map BAR0"); 2096 ret = -ENODEV; 2097 goto fail; 2098 } 2099 2100 nicvf_disable_all_interrupts(nic); 2101 2102 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev); 2103 if (ret) { 2104 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2105 goto fail; 2106 } 2107 2108 ret = nicvf_mbox_check_pf_ready(nic); 2109 if (ret) { 2110 PMD_INIT_LOG(ERR, "Failed to get ready message from PF"); 2111 goto alarm_fail; 2112 } else { 2113 PMD_INIT_LOG(INFO, 2114 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s", 2115 nic->node, nic->vf_id, 2116 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass", 2117 nic->sqs_mode ? "true" : "false", 2118 nic->loopback_supported ? "true" : "false" 2119 ); 2120 } 2121 2122 ret = nicvf_base_init(nic); 2123 if (ret) { 2124 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init"); 2125 goto malloc_fail; 2126 } 2127 2128 if (nic->sqs_mode) { 2129 /* Push nic to stack of secondary vfs */ 2130 nicvf_svf_push(nic); 2131 2132 /* Steal nic pointer from the device for further reuse */ 2133 eth_dev->data->dev_private = NULL; 2134 2135 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2136 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic); 2137 if (ret) { 2138 PMD_INIT_LOG(ERR, "Failed to start period alarm"); 2139 goto fail; 2140 } 2141 2142 /* Detach port by returning positive error number */ 2143 return ENOTSUP; 2144 } 2145 2146 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0); 2147 if (eth_dev->data->mac_addrs == NULL) { 2148 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr"); 2149 ret = -ENOMEM; 2150 goto alarm_fail; 2151 } 2152 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr)) 2153 eth_random_addr(&nic->mac_addr[0]); 2154 2155 ether_addr_copy((struct ether_addr *)nic->mac_addr, 2156 ð_dev->data->mac_addrs[0]); 2157 2158 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr); 2159 if (ret) { 2160 PMD_INIT_LOG(ERR, "Failed to set mac addr"); 2161 goto malloc_fail; 2162 } 2163 2164 ret = nicvf_set_first_skip(eth_dev); 2165 if (ret) { 2166 PMD_INIT_LOG(ERR, "Failed to configure first skip"); 2167 goto malloc_fail; 2168 } 2169 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x", 2170 eth_dev->data->port_id, nic->vendor_id, nic->device_id, 2171 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2], 2172 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]); 2173 2174 return 0; 2175 2176 malloc_fail: 2177 rte_free(eth_dev->data->mac_addrs); 2178 alarm_fail: 2179 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev); 2180 fail: 2181 return ret; 2182 } 2183 2184 static const struct rte_pci_id pci_id_nicvf_map[] = { 2185 { 2186 .class_id = RTE_CLASS_ANY_ID, 2187 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2188 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF, 2189 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2190 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF, 2191 }, 2192 { 2193 .class_id = RTE_CLASS_ANY_ID, 2194 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2195 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2196 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2197 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF, 2198 }, 2199 { 2200 .class_id = RTE_CLASS_ANY_ID, 2201 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2202 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2203 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2204 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF, 2205 }, 2206 { 2207 .class_id = RTE_CLASS_ANY_ID, 2208 .vendor_id = PCI_VENDOR_ID_CAVIUM, 2209 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF, 2210 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM, 2211 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF, 2212 }, 2213 { 2214 .vendor_id = 0, 2215 }, 2216 }; 2217 2218 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2219 struct rte_pci_device *pci_dev) 2220 { 2221 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf), 2222 nicvf_eth_dev_init); 2223 } 2224 2225 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev) 2226 { 2227 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 2228 } 2229 2230 static struct rte_pci_driver rte_nicvf_pmd = { 2231 .id_table = pci_id_nicvf_map, 2232 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES | 2233 RTE_PCI_DRV_INTR_LSC, 2234 .probe = nicvf_eth_pci_probe, 2235 .remove = nicvf_eth_pci_remove, 2236 }; 2237 2238 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd); 2239 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map); 2240 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci"); 2241 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>"); 2242