1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include "sfc.h" 11 #include "sfc_debug.h" 12 #include "sfc_log.h" 13 #include "sfc_ev.h" 14 #include "sfc_tx.h" 15 #include "sfc_tweak.h" 16 #include "sfc_kvargs.h" 17 18 /* 19 * Maximum number of TX queue flush attempts in case of 20 * failure or flush timeout 21 */ 22 #define SFC_TX_QFLUSH_ATTEMPTS (3) 23 24 /* 25 * Time to wait between event queue polling attempts when waiting for TX 26 * queue flush done or flush failed events 27 */ 28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1) 29 30 /* 31 * Maximum number of event queue polling attempts when waiting for TX queue 32 * flush done or flush failed events; it defines TX queue flush attempt timeout 33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS 34 */ 35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000) 36 37 struct sfc_txq_info * 38 sfc_txq_info_by_ethdev_qid(struct sfc_adapter_shared *sas, 39 sfc_ethdev_qid_t ethdev_qid) 40 { 41 sfc_sw_index_t sw_index; 42 43 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_txq_count); 44 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 45 46 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 47 return &sas->txq_info[sw_index]; 48 } 49 50 static uint64_t 51 sfc_tx_get_offload_mask(struct sfc_adapter *sa) 52 { 53 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 54 uint64_t no_caps = 0; 55 56 if (!encp->enc_hw_tx_insert_vlan_enabled) 57 no_caps |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT; 58 59 if (!encp->enc_tunnel_encapsulations_supported) 60 no_caps |= RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM; 61 62 if (!sa->tso) 63 no_caps |= RTE_ETH_TX_OFFLOAD_TCP_TSO; 64 65 if (!sa->tso_encap || 66 (encp->enc_tunnel_encapsulations_supported & 67 (1u << EFX_TUNNEL_PROTOCOL_VXLAN)) == 0) 68 no_caps |= RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO; 69 70 if (!sa->tso_encap || 71 (encp->enc_tunnel_encapsulations_supported & 72 (1u << EFX_TUNNEL_PROTOCOL_GENEVE)) == 0) 73 no_caps |= RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO; 74 75 return ~no_caps; 76 } 77 78 uint64_t 79 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa) 80 { 81 return sa->priv.dp_tx->dev_offload_capa & sfc_tx_get_offload_mask(sa); 82 } 83 84 uint64_t 85 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa) 86 { 87 return sa->priv.dp_tx->queue_offload_capa & sfc_tx_get_offload_mask(sa); 88 } 89 90 static int 91 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level, 92 const struct rte_eth_txconf *tx_conf, 93 uint64_t offloads) 94 { 95 int rc = 0; 96 97 if (tx_conf->tx_rs_thresh != 0) { 98 sfc_err(sa, "RS bit in transmit descriptor is not supported"); 99 rc = EINVAL; 100 } 101 102 if (tx_conf->tx_free_thresh > txq_max_fill_level) { 103 sfc_err(sa, 104 "TxQ free threshold too large: %u vs maximum %u", 105 tx_conf->tx_free_thresh, txq_max_fill_level); 106 rc = EINVAL; 107 } 108 109 if (tx_conf->tx_thresh.pthresh != 0 || 110 tx_conf->tx_thresh.hthresh != 0 || 111 tx_conf->tx_thresh.wthresh != 0) { 112 sfc_warn(sa, 113 "prefetch/host/writeback thresholds are not supported"); 114 } 115 116 /* We either perform both TCP and UDP offload, or no offload at all */ 117 if (((offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) == 0) != 118 ((offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) == 0)) { 119 sfc_err(sa, "TCP and UDP offloads can't be set independently"); 120 rc = EINVAL; 121 } 122 123 return rc; 124 } 125 126 void 127 sfc_tx_qflush_done(struct sfc_txq_info *txq_info) 128 { 129 txq_info->state |= SFC_TXQ_FLUSHED; 130 txq_info->state &= ~SFC_TXQ_FLUSHING; 131 } 132 133 int 134 sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 135 uint16_t nb_tx_desc, unsigned int socket_id, 136 const struct rte_eth_txconf *tx_conf) 137 { 138 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 139 sfc_ethdev_qid_t ethdev_qid; 140 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 141 unsigned int txq_entries; 142 unsigned int evq_entries; 143 unsigned int txq_max_fill_level; 144 struct sfc_txq_info *txq_info; 145 struct sfc_evq *evq; 146 struct sfc_txq *txq; 147 int rc = 0; 148 struct sfc_dp_tx_qcreate_info info; 149 uint64_t offloads; 150 struct sfc_dp_tx_hw_limits hw_limits; 151 152 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 153 154 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 155 156 memset(&hw_limits, 0, sizeof(hw_limits)); 157 hw_limits.txq_max_entries = sa->txq_max_entries; 158 hw_limits.txq_min_entries = sa->txq_min_entries; 159 160 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits, 161 &txq_entries, &evq_entries, 162 &txq_max_fill_level); 163 if (rc != 0) 164 goto fail_size_up_rings; 165 SFC_ASSERT(txq_entries >= sa->txq_min_entries); 166 SFC_ASSERT(txq_entries <= sa->txq_max_entries); 167 SFC_ASSERT(txq_entries >= nb_tx_desc); 168 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc); 169 170 offloads = tx_conf->offloads; 171 /* Add device level Tx offloads if the queue is an ethdev Tx queue */ 172 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 173 offloads |= sa->eth_dev->data->dev_conf.txmode.offloads; 174 175 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads); 176 if (rc != 0) 177 goto fail_bad_conf; 178 179 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 180 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 181 182 txq_info->entries = txq_entries; 183 184 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index, 185 evq_entries, socket_id, &evq); 186 if (rc != 0) 187 goto fail_ev_qinit; 188 189 txq = &sa->txq_ctrl[sw_index]; 190 txq->hw_index = sw_index; 191 txq->evq = evq; 192 txq_info->free_thresh = 193 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh : 194 SFC_TX_DEFAULT_FREE_THRESH; 195 txq_info->offloads = offloads; 196 197 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_NIC_DMA_ADDR_TX_RING, 198 efx_txq_size(sa->nic, txq_info->entries), 199 socket_id, &txq->mem); 200 if (rc != 0) 201 goto fail_dma_alloc; 202 203 memset(&info, 0, sizeof(info)); 204 info.max_fill_level = txq_max_fill_level; 205 info.free_thresh = txq_info->free_thresh; 206 info.offloads = offloads; 207 info.txq_entries = txq_info->entries; 208 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max; 209 info.txq_hw_ring = txq->mem.esm_base; 210 info.evq_entries = evq_entries; 211 info.evq_hw_ring = evq->mem.esm_base; 212 info.hw_index = txq->hw_index; 213 info.mem_bar = sa->mem_bar.esb_base; 214 info.vi_window_shift = encp->enc_vi_window_shift; 215 info.tso_tcp_header_offset_limit = 216 encp->enc_tx_tso_tcp_header_offset_limit; 217 info.tso_max_nb_header_descs = 218 RTE_MIN(encp->enc_tx_tso_max_header_ndescs, 219 (uint32_t)UINT16_MAX); 220 info.tso_max_header_len = 221 RTE_MIN(encp->enc_tx_tso_max_header_length, 222 (uint32_t)UINT16_MAX); 223 info.tso_max_nb_payload_descs = 224 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs, 225 (uint32_t)UINT16_MAX); 226 info.tso_max_payload_len = encp->enc_tx_tso_max_payload_length; 227 info.tso_max_nb_outgoing_frames = encp->enc_tx_tso_max_nframes; 228 229 info.nic_dma_info = &sas->nic_dma_info; 230 231 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index, 232 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 233 socket_id, &info, &txq_info->dp); 234 if (rc != 0) 235 goto fail_dp_tx_qinit; 236 237 evq->dp_txq = txq_info->dp; 238 239 txq_info->state = SFC_TXQ_INITIALIZED; 240 241 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0); 242 243 return 0; 244 245 fail_dp_tx_qinit: 246 sfc_dma_free(sa, &txq->mem); 247 248 fail_dma_alloc: 249 sfc_ev_qfini(evq); 250 251 fail_ev_qinit: 252 txq_info->entries = 0; 253 254 fail_bad_conf: 255 fail_size_up_rings: 256 sfc_log_init(sa, "failed (TxQ = %d (internal %u), rc = %d)", ethdev_qid, 257 sw_index, rc); 258 return rc; 259 } 260 261 void 262 sfc_tx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 263 { 264 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 265 sfc_ethdev_qid_t ethdev_qid; 266 struct sfc_txq_info *txq_info; 267 struct sfc_txq *txq; 268 269 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 270 271 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 272 273 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 274 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 275 sa->eth_dev->data->tx_queues[ethdev_qid] = NULL; 276 277 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 278 279 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 280 281 sa->priv.dp_tx->qdestroy(txq_info->dp); 282 txq_info->dp = NULL; 283 284 txq_info->state &= ~SFC_TXQ_INITIALIZED; 285 txq_info->entries = 0; 286 287 txq = &sa->txq_ctrl[sw_index]; 288 289 sfc_dma_free(sa, &txq->mem); 290 291 sfc_ev_qfini(txq->evq); 292 txq->evq = NULL; 293 } 294 295 int 296 sfc_tx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 297 { 298 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 299 sfc_ethdev_qid_t ethdev_qid; 300 301 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 302 303 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 304 305 return 0; 306 } 307 308 static int 309 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode) 310 { 311 int rc = 0; 312 313 switch (txmode->mq_mode) { 314 case RTE_ETH_MQ_TX_NONE: 315 break; 316 default: 317 sfc_err(sa, "Tx multi-queue mode %u not supported", 318 txmode->mq_mode); 319 rc = EINVAL; 320 } 321 322 /* 323 * These features are claimed to be i40e-specific, 324 * but it does make sense to double-check their absence 325 */ 326 if (txmode->hw_vlan_reject_tagged) { 327 sfc_err(sa, "Rejecting tagged packets not supported"); 328 rc = EINVAL; 329 } 330 331 if (txmode->hw_vlan_reject_untagged) { 332 sfc_err(sa, "Rejecting untagged packets not supported"); 333 rc = EINVAL; 334 } 335 336 if (txmode->hw_vlan_insert_pvid) { 337 sfc_err(sa, "Port-based VLAN insertion not supported"); 338 rc = EINVAL; 339 } 340 341 return rc; 342 } 343 344 /** 345 * Destroy excess queues that are no longer needed after reconfiguration 346 * or complete close. 347 */ 348 static void 349 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues) 350 { 351 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 352 sfc_sw_index_t sw_index; 353 sfc_ethdev_qid_t ethdev_qid; 354 355 SFC_ASSERT(nb_tx_queues <= sas->ethdev_txq_count); 356 357 /* 358 * Finalize only ethdev queues since other ones are finalized only 359 * on device close and they may require additional deinitializaton. 360 */ 361 ethdev_qid = sas->ethdev_txq_count; 362 while (--ethdev_qid >= (int)nb_tx_queues) { 363 struct sfc_txq_info *txq_info; 364 365 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 366 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 367 if (txq_info->state & SFC_TXQ_INITIALIZED) 368 sfc_tx_qfini(sa, sw_index); 369 } 370 371 sas->ethdev_txq_count = nb_tx_queues; 372 } 373 374 int 375 sfc_tx_configure(struct sfc_adapter *sa) 376 { 377 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 378 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 379 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 380 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues; 381 const unsigned int nb_rsvd_tx_queues = sfc_nb_txq_reserved(sas); 382 const unsigned int nb_txq_total = nb_tx_queues + nb_rsvd_tx_queues; 383 bool reconfigure; 384 int rc = 0; 385 386 sfc_log_init(sa, "nb_tx_queues=%u (old %u)", 387 nb_tx_queues, sas->ethdev_txq_count); 388 389 /* 390 * The datapath implementation assumes absence of boundary 391 * limits on Tx DMA descriptors. Addition of these checks on 392 * datapath would simply make the datapath slower. 393 */ 394 if (encp->enc_tx_dma_desc_boundary != 0) { 395 rc = ENOTSUP; 396 goto fail_tx_dma_desc_boundary; 397 } 398 399 rc = sfc_tx_check_mode(sa, &dev_conf->txmode); 400 if (rc != 0) 401 goto fail_check_mode; 402 403 if (nb_txq_total == sas->txq_count) 404 goto done; 405 406 if (sas->txq_info == NULL) { 407 reconfigure = false; 408 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_txq_total, 409 sizeof(sas->txq_info[0]), 0, 410 sa->socket_id); 411 if (sas->txq_info == NULL) 412 goto fail_txqs_alloc; 413 414 /* 415 * Allocate primary process only TxQ control from heap 416 * since it should not be shared. 417 */ 418 rc = ENOMEM; 419 sa->txq_ctrl = calloc(nb_txq_total, sizeof(sa->txq_ctrl[0])); 420 if (sa->txq_ctrl == NULL) 421 goto fail_txqs_ctrl_alloc; 422 } else { 423 struct sfc_txq_info *new_txq_info; 424 struct sfc_txq *new_txq_ctrl; 425 426 reconfigure = true; 427 428 if (nb_tx_queues < sas->ethdev_txq_count) 429 sfc_tx_fini_queues(sa, nb_tx_queues); 430 431 new_txq_info = 432 rte_realloc(sas->txq_info, 433 nb_txq_total * sizeof(sas->txq_info[0]), 0); 434 if (new_txq_info == NULL && nb_txq_total > 0) 435 goto fail_txqs_realloc; 436 437 new_txq_ctrl = realloc(sa->txq_ctrl, 438 nb_txq_total * sizeof(sa->txq_ctrl[0])); 439 if (new_txq_ctrl == NULL && nb_txq_total > 0) 440 goto fail_txqs_ctrl_realloc; 441 442 sas->txq_info = new_txq_info; 443 sa->txq_ctrl = new_txq_ctrl; 444 if (nb_txq_total > sas->txq_count) { 445 memset(&sas->txq_info[sas->txq_count], 0, 446 (nb_txq_total - sas->txq_count) * 447 sizeof(sas->txq_info[0])); 448 memset(&sa->txq_ctrl[sas->txq_count], 0, 449 (nb_txq_total - sas->txq_count) * 450 sizeof(sa->txq_ctrl[0])); 451 } 452 } 453 454 while (sas->ethdev_txq_count < nb_tx_queues) { 455 sfc_sw_index_t sw_index; 456 457 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, 458 sas->ethdev_txq_count); 459 rc = sfc_tx_qinit_info(sa, sw_index); 460 if (rc != 0) 461 goto fail_tx_qinit_info; 462 463 sas->ethdev_txq_count++; 464 } 465 466 sas->txq_count = sas->ethdev_txq_count + nb_rsvd_tx_queues; 467 468 if (!reconfigure) { 469 rc = sfc_repr_proxy_txq_init(sa); 470 if (rc != 0) 471 goto fail_repr_proxy_txq_init; 472 } 473 474 done: 475 return 0; 476 477 fail_repr_proxy_txq_init: 478 fail_tx_qinit_info: 479 fail_txqs_ctrl_realloc: 480 fail_txqs_realloc: 481 fail_txqs_ctrl_alloc: 482 fail_txqs_alloc: 483 sfc_tx_close(sa); 484 485 fail_check_mode: 486 fail_tx_dma_desc_boundary: 487 sfc_log_init(sa, "failed (rc = %d)", rc); 488 return rc; 489 } 490 491 void 492 sfc_tx_close(struct sfc_adapter *sa) 493 { 494 sfc_tx_fini_queues(sa, 0); 495 sfc_repr_proxy_txq_fini(sa); 496 497 free(sa->txq_ctrl); 498 sa->txq_ctrl = NULL; 499 500 rte_free(sfc_sa2shared(sa)->txq_info); 501 sfc_sa2shared(sa)->txq_info = NULL; 502 } 503 504 int 505 sfc_tx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 506 { 507 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 508 sfc_ethdev_qid_t ethdev_qid; 509 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) | 510 sfc_tx_get_queue_offload_caps(sa); 511 struct sfc_txq_info *txq_info; 512 struct sfc_txq *txq; 513 struct sfc_evq *evq; 514 uint16_t flags = 0; 515 unsigned int desc_index; 516 int rc = 0; 517 518 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 519 520 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 521 522 SFC_ASSERT(sw_index < sas->txq_count); 523 txq_info = &sas->txq_info[sw_index]; 524 525 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 526 527 txq = &sa->txq_ctrl[sw_index]; 528 evq = txq->evq; 529 530 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_txq_sw_index(sa, sw_index)); 531 if (rc != 0) 532 goto fail_ev_qstart; 533 534 if (txq_info->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) 535 flags |= EFX_TXQ_CKSUM_IPV4; 536 537 if (txq_info->offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM) 538 flags |= EFX_TXQ_CKSUM_INNER_IPV4; 539 540 if ((txq_info->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) || 541 (txq_info->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM)) { 542 flags |= EFX_TXQ_CKSUM_TCPUDP; 543 544 if (offloads_supported & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM) 545 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP; 546 } 547 548 if (txq_info->offloads & (RTE_ETH_TX_OFFLOAD_TCP_TSO | 549 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | 550 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO)) 551 flags |= EFX_TXQ_FATSOV2; 552 553 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem, 554 txq_info->entries, 0 /* not used on EF10 */, 555 flags, evq->common, 556 &txq->common, &desc_index); 557 if (rc != 0) { 558 if (sa->tso && (rc == ENOSPC)) 559 sfc_err(sa, "ran out of TSO contexts"); 560 561 goto fail_tx_qcreate; 562 } 563 564 efx_tx_qenable(txq->common); 565 566 txq_info->state |= SFC_TXQ_STARTED; 567 568 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index); 569 if (rc != 0) 570 goto fail_dp_qstart; 571 572 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) { 573 struct rte_eth_dev_data *dev_data; 574 575 /* 576 * It sems to be used by DPDK for debug purposes only 577 * ('rte_ether'). 578 */ 579 dev_data = sa->eth_dev->data; 580 dev_data->tx_queue_state[ethdev_qid] = 581 RTE_ETH_QUEUE_STATE_STARTED; 582 } 583 584 return 0; 585 586 fail_dp_qstart: 587 txq_info->state = SFC_TXQ_INITIALIZED; 588 efx_tx_qdestroy(txq->common); 589 590 fail_tx_qcreate: 591 sfc_ev_qstop(evq); 592 593 fail_ev_qstart: 594 return rc; 595 } 596 597 void 598 sfc_tx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 599 { 600 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 601 sfc_ethdev_qid_t ethdev_qid; 602 struct sfc_txq_info *txq_info; 603 struct sfc_txq *txq; 604 unsigned int retry_count; 605 unsigned int wait_count; 606 int rc; 607 608 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 609 610 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 611 612 SFC_ASSERT(sw_index < sas->txq_count); 613 txq_info = &sas->txq_info[sw_index]; 614 615 if (txq_info->state == SFC_TXQ_INITIALIZED) 616 return; 617 618 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED); 619 620 txq = &sa->txq_ctrl[sw_index]; 621 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr); 622 623 /* 624 * Retry TX queue flushing in case of flush failed or 625 * timeout; in the worst case it can delay for 6 seconds 626 */ 627 for (retry_count = 0; 628 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) && 629 (retry_count < SFC_TX_QFLUSH_ATTEMPTS); 630 ++retry_count) { 631 rc = efx_tx_qflush(txq->common); 632 if (rc != 0) { 633 txq_info->state |= (rc == EALREADY) ? 634 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED; 635 break; 636 } 637 638 /* 639 * Wait for TX queue flush done or flush failed event at least 640 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more 641 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied 642 * by SFC_TX_QFLUSH_POLL_ATTEMPTS) 643 */ 644 wait_count = 0; 645 do { 646 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS); 647 sfc_ev_qpoll(txq->evq); 648 } while ((txq_info->state & SFC_TXQ_FLUSHING) && 649 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS); 650 651 if (txq_info->state & SFC_TXQ_FLUSHING) 652 sfc_err(sa, "TxQ %d (internal %u) flush timed out", 653 ethdev_qid, sw_index); 654 655 if (txq_info->state & SFC_TXQ_FLUSHED) 656 sfc_notice(sa, "TxQ %d (internal %u) flushed", 657 ethdev_qid, sw_index); 658 } 659 660 sa->priv.dp_tx->qreap(txq_info->dp); 661 662 txq_info->state = SFC_TXQ_INITIALIZED; 663 664 efx_tx_qdestroy(txq->common); 665 666 sfc_ev_qstop(txq->evq); 667 668 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) { 669 struct rte_eth_dev_data *dev_data; 670 671 /* 672 * It seems to be used by DPDK for debug purposes only 673 * ('rte_ether') 674 */ 675 dev_data = sa->eth_dev->data; 676 dev_data->tx_queue_state[ethdev_qid] = 677 RTE_ETH_QUEUE_STATE_STOPPED; 678 } 679 } 680 681 int 682 sfc_tx_start(struct sfc_adapter *sa) 683 { 684 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 685 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 686 sfc_sw_index_t sw_index; 687 int rc = 0; 688 689 sfc_log_init(sa, "txq_count = %u (internal %u)", 690 sas->ethdev_txq_count, sas->txq_count); 691 692 if (sa->tso) { 693 if (!encp->enc_fw_assisted_tso_v2_enabled && 694 !encp->enc_tso_v3_enabled) { 695 sfc_warn(sa, "TSO support was unable to be restored"); 696 sa->tso = B_FALSE; 697 sa->tso_encap = B_FALSE; 698 } 699 } 700 701 if (sa->tso_encap && !encp->enc_fw_assisted_tso_v2_encap_enabled && 702 !encp->enc_tso_v3_enabled) { 703 sfc_warn(sa, "Encapsulated TSO support was unable to be restored"); 704 sa->tso_encap = B_FALSE; 705 } 706 707 rc = efx_tx_init(sa->nic); 708 if (rc != 0) 709 goto fail_efx_tx_init; 710 711 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) { 712 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED && 713 (!(sas->txq_info[sw_index].deferred_start) || 714 sas->txq_info[sw_index].deferred_started)) { 715 rc = sfc_tx_qstart(sa, sw_index); 716 if (rc != 0) 717 goto fail_tx_qstart; 718 } 719 } 720 721 return 0; 722 723 fail_tx_qstart: 724 while (sw_index-- > 0) 725 sfc_tx_qstop(sa, sw_index); 726 727 efx_tx_fini(sa->nic); 728 729 fail_efx_tx_init: 730 sfc_log_init(sa, "failed (rc = %d)", rc); 731 return rc; 732 } 733 734 void 735 sfc_tx_stop(struct sfc_adapter *sa) 736 { 737 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 738 sfc_sw_index_t sw_index; 739 740 sfc_log_init(sa, "txq_count = %u (internal %u)", 741 sas->ethdev_txq_count, sas->txq_count); 742 743 sw_index = sas->txq_count; 744 while (sw_index-- > 0) { 745 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED) 746 sfc_tx_qstop(sa, sw_index); 747 } 748 749 efx_tx_fini(sa->nic); 750 } 751 752 static void 753 sfc_efx_tx_reap(struct sfc_efx_txq *txq) 754 { 755 unsigned int completed; 756 757 sfc_ev_qpoll(txq->evq); 758 759 for (completed = txq->completed; 760 completed != txq->pending; completed++) { 761 struct sfc_efx_tx_sw_desc *txd; 762 763 txd = &txq->sw_ring[completed & txq->ptr_mask]; 764 765 if (txd->mbuf != NULL) { 766 rte_pktmbuf_free(txd->mbuf); 767 txd->mbuf = NULL; 768 } 769 } 770 771 txq->completed = completed; 772 } 773 774 /* 775 * The function is used to insert or update VLAN tag; 776 * the firmware has state of the firmware tag to insert per TxQ 777 * (controlled by option descriptors), hence, if the tag of the 778 * packet to be sent is different from one remembered by the firmware, 779 * the function will update it 780 */ 781 static unsigned int 782 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m, 783 efx_desc_t **pend) 784 { 785 uint16_t this_tag = ((m->ol_flags & RTE_MBUF_F_TX_VLAN) ? 786 m->vlan_tci : 0); 787 788 if (this_tag == txq->hw_vlan_tci) 789 return 0; 790 791 /* 792 * The expression inside SFC_ASSERT() is not desired to be checked in 793 * a non-debug build because it might be too expensive on the data path 794 */ 795 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled); 796 797 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag), 798 *pend); 799 (*pend)++; 800 txq->hw_vlan_tci = this_tag; 801 802 return 1; 803 } 804 805 static uint16_t 806 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 807 uint16_t nb_pkts) 808 { 809 struct sfc_dp_txq *dp_txq = tx_queue; 810 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 811 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic); 812 uint16_t i; 813 814 for (i = 0; i < nb_pkts; i++) { 815 int ret; 816 817 /* 818 * EFX Tx datapath may require extra VLAN descriptor if VLAN 819 * insertion offload is requested regardless the offload 820 * requested/supported. 821 */ 822 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i], 0, SFC_TSOH_STD_LEN, 823 encp->enc_tx_tso_tcp_header_offset_limit, 824 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS, 825 1); 826 if (unlikely(ret != 0)) { 827 rte_errno = ret; 828 break; 829 } 830 } 831 832 return i; 833 } 834 835 static uint16_t 836 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 837 { 838 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue; 839 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 840 unsigned int added = txq->added; 841 unsigned int pushed = added; 842 unsigned int pkts_sent = 0; 843 efx_desc_t *pend = &txq->pend_desc[0]; 844 const unsigned int hard_max_fill = txq->max_fill_level; 845 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh; 846 unsigned int fill_level = added - txq->completed; 847 boolean_t reap_done; 848 int rc __rte_unused; 849 struct rte_mbuf **pktp; 850 851 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0)) 852 goto done; 853 854 /* 855 * If insufficient space for a single packet is present, 856 * we should reap; otherwise, we shouldn't do that all the time 857 * to avoid latency increase 858 */ 859 reap_done = (fill_level > soft_max_fill); 860 861 if (reap_done) { 862 sfc_efx_tx_reap(txq); 863 /* 864 * Recalculate fill level since 'txq->completed' 865 * might have changed on reap 866 */ 867 fill_level = added - txq->completed; 868 } 869 870 for (pkts_sent = 0, pktp = &tx_pkts[0]; 871 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill); 872 pkts_sent++, pktp++) { 873 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci; 874 struct rte_mbuf *m_seg = *pktp; 875 size_t pkt_len = m_seg->pkt_len; 876 unsigned int pkt_descs = 0; 877 size_t in_off = 0; 878 879 /* 880 * Here VLAN TCI is expected to be zero in case if no 881 * RTE_ETH_TX_OFFLOAD_VLAN_INSERT capability is advertised; 882 * if the calling app ignores the absence of 883 * RTE_ETH_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then 884 * TX_ERROR will occur 885 */ 886 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend); 887 888 if (m_seg->ol_flags & RTE_MBUF_F_TX_TCP_SEG) { 889 /* 890 * We expect correct 'pkt->l[2, 3, 4]_len' values 891 * to be set correctly by the caller 892 */ 893 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend, 894 &pkt_descs, &pkt_len) != 0) { 895 /* We may have reached this place if packet 896 * header linearization is needed but the 897 * header length is greater than 898 * SFC_TSOH_STD_LEN 899 * 900 * We will deceive RTE saying that we have sent 901 * the packet, but we will actually drop it. 902 * Hence, we should revert 'pend' to the 903 * previous state (in case we have added 904 * VLAN descriptor) and start processing 905 * another one packet. But the original 906 * mbuf shouldn't be orphaned 907 */ 908 pend -= pkt_descs; 909 txq->hw_vlan_tci = hw_vlan_tci_prev; 910 911 rte_pktmbuf_free(*pktp); 912 913 continue; 914 } 915 916 /* 917 * We've only added 2 FATSOv2 option descriptors 918 * and 1 descriptor for the linearized packet header. 919 * The outstanding work will be done in the same manner 920 * as for the usual non-TSO path 921 */ 922 } 923 924 for (; m_seg != NULL; m_seg = m_seg->next) { 925 efsys_dma_addr_t next_frag; 926 size_t seg_len; 927 928 seg_len = m_seg->data_len; 929 next_frag = rte_mbuf_data_iova(m_seg); 930 931 /* 932 * If we've started TSO transaction few steps earlier, 933 * we'll skip packet header using an offset in the 934 * current segment (which has been set to the 935 * first one containing payload) 936 */ 937 seg_len -= in_off; 938 next_frag += in_off; 939 in_off = 0; 940 941 do { 942 efsys_dma_addr_t frag_addr = next_frag; 943 size_t frag_len; 944 945 /* 946 * It is assumed here that there is no 947 * limitation on address boundary 948 * crossing by DMA descriptor. 949 */ 950 frag_len = MIN(seg_len, txq->dma_desc_size_max); 951 next_frag += frag_len; 952 seg_len -= frag_len; 953 pkt_len -= frag_len; 954 955 efx_tx_qdesc_dma_create(txq->common, 956 frag_addr, frag_len, 957 (pkt_len == 0), 958 pend++); 959 960 pkt_descs++; 961 } while (seg_len != 0); 962 } 963 964 added += pkt_descs; 965 966 fill_level += pkt_descs; 967 if (unlikely(fill_level > hard_max_fill)) { 968 /* 969 * Our estimation for maximum number of descriptors 970 * required to send a packet seems to be wrong. 971 * Try to reap (if we haven't yet). 972 */ 973 if (!reap_done) { 974 sfc_efx_tx_reap(txq); 975 reap_done = B_TRUE; 976 fill_level = added - txq->completed; 977 if (fill_level > hard_max_fill) { 978 pend -= pkt_descs; 979 txq->hw_vlan_tci = hw_vlan_tci_prev; 980 break; 981 } 982 } else { 983 pend -= pkt_descs; 984 txq->hw_vlan_tci = hw_vlan_tci_prev; 985 break; 986 } 987 } 988 989 /* Assign mbuf to the last used desc */ 990 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp; 991 } 992 993 if (likely(pkts_sent > 0)) { 994 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, 995 pend - &txq->pend_desc[0], 996 txq->completed, &txq->added); 997 SFC_ASSERT(rc == 0); 998 999 if (likely(pushed != txq->added)) { 1000 efx_tx_qpush(txq->common, txq->added, pushed); 1001 txq->dp.dpq.dbells++; 1002 } 1003 } 1004 1005 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE 1006 if (!reap_done) 1007 sfc_efx_tx_reap(txq); 1008 #endif 1009 1010 done: 1011 return pkts_sent; 1012 } 1013 1014 const struct sfc_dp_tx * 1015 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1016 { 1017 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1018 struct rte_eth_dev *eth_dev; 1019 struct sfc_adapter_priv *sap; 1020 1021 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1022 eth_dev = &rte_eth_devices[dpq->port_id]; 1023 1024 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 1025 1026 return sap->dp_tx; 1027 } 1028 1029 struct sfc_txq_info * 1030 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1031 { 1032 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1033 struct rte_eth_dev *eth_dev; 1034 struct sfc_adapter_shared *sas; 1035 1036 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1037 eth_dev = &rte_eth_devices[dpq->port_id]; 1038 1039 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 1040 1041 SFC_ASSERT(dpq->queue_id < sas->txq_count); 1042 return &sas->txq_info[dpq->queue_id]; 1043 } 1044 1045 struct sfc_txq * 1046 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1047 { 1048 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1049 struct rte_eth_dev *eth_dev; 1050 struct sfc_adapter *sa; 1051 1052 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1053 eth_dev = &rte_eth_devices[dpq->port_id]; 1054 1055 sa = sfc_adapter_by_eth_dev(eth_dev); 1056 1057 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count); 1058 return &sa->txq_ctrl[dpq->queue_id]; 1059 } 1060 1061 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings; 1062 static int 1063 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc, 1064 __rte_unused struct sfc_dp_tx_hw_limits *limits, 1065 unsigned int *txq_entries, 1066 unsigned int *evq_entries, 1067 unsigned int *txq_max_fill_level) 1068 { 1069 *txq_entries = nb_tx_desc; 1070 *evq_entries = nb_tx_desc; 1071 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries); 1072 return 0; 1073 } 1074 1075 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate; 1076 static int 1077 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id, 1078 const struct rte_pci_addr *pci_addr, 1079 int socket_id, 1080 const struct sfc_dp_tx_qcreate_info *info, 1081 struct sfc_dp_txq **dp_txqp) 1082 { 1083 struct sfc_efx_txq *txq; 1084 struct sfc_txq *ctrl_txq; 1085 int rc; 1086 1087 rc = ENOTSUP; 1088 if (info->nic_dma_info->nb_regions > 0) 1089 goto fail_nic_dma; 1090 1091 rc = ENOMEM; 1092 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq), 1093 RTE_CACHE_LINE_SIZE, socket_id); 1094 if (txq == NULL) 1095 goto fail_txq_alloc; 1096 1097 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr); 1098 1099 rc = ENOMEM; 1100 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc", 1101 EFX_TXQ_LIMIT(info->txq_entries), 1102 sizeof(*txq->pend_desc), 0, 1103 socket_id); 1104 if (txq->pend_desc == NULL) 1105 goto fail_pend_desc_alloc; 1106 1107 rc = ENOMEM; 1108 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring", 1109 info->txq_entries, 1110 sizeof(*txq->sw_ring), 1111 RTE_CACHE_LINE_SIZE, socket_id); 1112 if (txq->sw_ring == NULL) 1113 goto fail_sw_ring_alloc; 1114 1115 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp); 1116 if (ctrl_txq->evq->sa->tso) { 1117 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring, 1118 info->txq_entries, socket_id); 1119 if (rc != 0) 1120 goto fail_alloc_tsoh_objs; 1121 } 1122 1123 txq->evq = ctrl_txq->evq; 1124 txq->ptr_mask = info->txq_entries - 1; 1125 txq->max_fill_level = info->max_fill_level; 1126 txq->free_thresh = info->free_thresh; 1127 txq->dma_desc_size_max = info->dma_desc_size_max; 1128 1129 *dp_txqp = &txq->dp; 1130 return 0; 1131 1132 fail_alloc_tsoh_objs: 1133 rte_free(txq->sw_ring); 1134 1135 fail_sw_ring_alloc: 1136 rte_free(txq->pend_desc); 1137 1138 fail_pend_desc_alloc: 1139 rte_free(txq); 1140 1141 fail_txq_alloc: 1142 fail_nic_dma: 1143 return rc; 1144 } 1145 1146 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy; 1147 static void 1148 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq) 1149 { 1150 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1151 1152 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1); 1153 rte_free(txq->sw_ring); 1154 rte_free(txq->pend_desc); 1155 rte_free(txq); 1156 } 1157 1158 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart; 1159 static int 1160 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq, 1161 __rte_unused unsigned int evq_read_ptr, 1162 unsigned int txq_desc_index) 1163 { 1164 /* libefx-based datapath is specific to libefx-based PMD */ 1165 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1166 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq); 1167 1168 txq->common = ctrl_txq->common; 1169 1170 txq->pending = txq->completed = txq->added = txq_desc_index; 1171 txq->hw_vlan_tci = 0; 1172 1173 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING); 1174 1175 return 0; 1176 } 1177 1178 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop; 1179 static void 1180 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq, 1181 __rte_unused unsigned int *evq_read_ptr) 1182 { 1183 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1184 1185 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING; 1186 } 1187 1188 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap; 1189 static void 1190 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq) 1191 { 1192 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1193 unsigned int txds; 1194 1195 sfc_efx_tx_reap(txq); 1196 1197 for (txds = 0; txds <= txq->ptr_mask; txds++) { 1198 if (txq->sw_ring[txds].mbuf != NULL) { 1199 rte_pktmbuf_free(txq->sw_ring[txds].mbuf); 1200 txq->sw_ring[txds].mbuf = NULL; 1201 } 1202 } 1203 1204 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED; 1205 } 1206 1207 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status; 1208 static int 1209 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset) 1210 { 1211 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1212 1213 if (unlikely(offset > txq->ptr_mask)) 1214 return -EINVAL; 1215 1216 if (unlikely(offset >= txq->max_fill_level)) 1217 return RTE_ETH_TX_DESC_UNAVAIL; 1218 1219 /* 1220 * Poll EvQ to derive up-to-date 'txq->pending' figure; 1221 * it is required for the queue to be running, but the 1222 * check is omitted because API design assumes that it 1223 * is the duty of the caller to satisfy all conditions 1224 */ 1225 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 1226 SFC_EFX_TXQ_FLAG_RUNNING); 1227 sfc_ev_qpoll(txq->evq); 1228 1229 /* 1230 * Ring tail is 'txq->pending', and although descriptors 1231 * between 'txq->completed' and 'txq->pending' are still 1232 * in use by the driver, they should be reported as DONE 1233 */ 1234 if (unlikely(offset < (txq->added - txq->pending))) 1235 return RTE_ETH_TX_DESC_FULL; 1236 1237 /* 1238 * There is no separate return value for unused descriptors; 1239 * the latter will be reported as DONE because genuine DONE 1240 * descriptors will be freed anyway in SW on the next burst 1241 */ 1242 return RTE_ETH_TX_DESC_DONE; 1243 } 1244 1245 struct sfc_dp_tx sfc_efx_tx = { 1246 .dp = { 1247 .name = SFC_KVARG_DATAPATH_EFX, 1248 .type = SFC_DP_TX, 1249 .hw_fw_caps = SFC_DP_HW_FW_CAP_TX_EFX, 1250 }, 1251 .features = 0, 1252 .dev_offload_capa = RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1253 RTE_ETH_TX_OFFLOAD_MULTI_SEGS, 1254 .queue_offload_capa = RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1255 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1256 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 1257 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1258 RTE_ETH_TX_OFFLOAD_TCP_TSO, 1259 .qsize_up_rings = sfc_efx_tx_qsize_up_rings, 1260 .qcreate = sfc_efx_tx_qcreate, 1261 .qdestroy = sfc_efx_tx_qdestroy, 1262 .qstart = sfc_efx_tx_qstart, 1263 .qstop = sfc_efx_tx_qstop, 1264 .qreap = sfc_efx_tx_qreap, 1265 .qdesc_status = sfc_efx_tx_qdesc_status, 1266 .pkt_prepare = sfc_efx_prepare_pkts, 1267 .pkt_burst = sfc_efx_xmit_pkts, 1268 }; 1269