1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include "sfc.h" 11 #include "sfc_debug.h" 12 #include "sfc_log.h" 13 #include "sfc_ev.h" 14 #include "sfc_tx.h" 15 #include "sfc_tweak.h" 16 #include "sfc_kvargs.h" 17 18 /* 19 * Maximum number of TX queue flush attempts in case of 20 * failure or flush timeout 21 */ 22 #define SFC_TX_QFLUSH_ATTEMPTS (3) 23 24 /* 25 * Time to wait between event queue polling attempts when waiting for TX 26 * queue flush done or flush failed events 27 */ 28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1) 29 30 /* 31 * Maximum number of event queue polling attempts when waiting for TX queue 32 * flush done or flush failed events; it defines TX queue flush attempt timeout 33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS 34 */ 35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000) 36 37 static uint64_t 38 sfc_tx_get_offload_mask(struct sfc_adapter *sa) 39 { 40 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 41 uint64_t no_caps = 0; 42 43 if (!encp->enc_hw_tx_insert_vlan_enabled) 44 no_caps |= DEV_TX_OFFLOAD_VLAN_INSERT; 45 46 if (!encp->enc_tunnel_encapsulations_supported) 47 no_caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 48 49 if (!sa->tso) 50 no_caps |= DEV_TX_OFFLOAD_TCP_TSO; 51 52 if (!sa->tso_encap) 53 no_caps |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 54 DEV_TX_OFFLOAD_GENEVE_TNL_TSO); 55 56 return ~no_caps; 57 } 58 59 uint64_t 60 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa) 61 { 62 return sa->priv.dp_tx->dev_offload_capa & sfc_tx_get_offload_mask(sa); 63 } 64 65 uint64_t 66 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa) 67 { 68 return sa->priv.dp_tx->queue_offload_capa & sfc_tx_get_offload_mask(sa); 69 } 70 71 static int 72 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level, 73 const struct rte_eth_txconf *tx_conf, 74 uint64_t offloads) 75 { 76 int rc = 0; 77 78 if (tx_conf->tx_rs_thresh != 0) { 79 sfc_err(sa, "RS bit in transmit descriptor is not supported"); 80 rc = EINVAL; 81 } 82 83 if (tx_conf->tx_free_thresh > txq_max_fill_level) { 84 sfc_err(sa, 85 "TxQ free threshold too large: %u vs maximum %u", 86 tx_conf->tx_free_thresh, txq_max_fill_level); 87 rc = EINVAL; 88 } 89 90 if (tx_conf->tx_thresh.pthresh != 0 || 91 tx_conf->tx_thresh.hthresh != 0 || 92 tx_conf->tx_thresh.wthresh != 0) { 93 sfc_warn(sa, 94 "prefetch/host/writeback thresholds are not supported"); 95 } 96 97 /* We either perform both TCP and UDP offload, or no offload at all */ 98 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) != 99 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) { 100 sfc_err(sa, "TCP and UDP offloads can't be set independently"); 101 rc = EINVAL; 102 } 103 104 return rc; 105 } 106 107 void 108 sfc_tx_qflush_done(struct sfc_txq_info *txq_info) 109 { 110 txq_info->state |= SFC_TXQ_FLUSHED; 111 txq_info->state &= ~SFC_TXQ_FLUSHING; 112 } 113 114 int 115 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 116 uint16_t nb_tx_desc, unsigned int socket_id, 117 const struct rte_eth_txconf *tx_conf) 118 { 119 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 120 unsigned int txq_entries; 121 unsigned int evq_entries; 122 unsigned int txq_max_fill_level; 123 struct sfc_txq_info *txq_info; 124 struct sfc_evq *evq; 125 struct sfc_txq *txq; 126 int rc = 0; 127 struct sfc_dp_tx_qcreate_info info; 128 uint64_t offloads; 129 struct sfc_dp_tx_hw_limits hw_limits; 130 131 sfc_log_init(sa, "TxQ = %u", sw_index); 132 133 memset(&hw_limits, 0, sizeof(hw_limits)); 134 hw_limits.txq_max_entries = sa->txq_max_entries; 135 hw_limits.txq_min_entries = sa->txq_min_entries; 136 137 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits, 138 &txq_entries, &evq_entries, 139 &txq_max_fill_level); 140 if (rc != 0) 141 goto fail_size_up_rings; 142 SFC_ASSERT(txq_entries >= sa->txq_min_entries); 143 SFC_ASSERT(txq_entries <= sa->txq_max_entries); 144 SFC_ASSERT(txq_entries >= nb_tx_desc); 145 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc); 146 147 offloads = tx_conf->offloads | 148 sa->eth_dev->data->dev_conf.txmode.offloads; 149 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads); 150 if (rc != 0) 151 goto fail_bad_conf; 152 153 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 154 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 155 156 txq_info->entries = txq_entries; 157 158 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index, 159 evq_entries, socket_id, &evq); 160 if (rc != 0) 161 goto fail_ev_qinit; 162 163 txq = &sa->txq_ctrl[sw_index]; 164 txq->hw_index = sw_index; 165 txq->evq = evq; 166 txq_info->free_thresh = 167 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh : 168 SFC_TX_DEFAULT_FREE_THRESH; 169 txq_info->offloads = offloads; 170 171 rc = sfc_dma_alloc(sa, "txq", sw_index, 172 efx_txq_size(sa->nic, txq_info->entries), 173 socket_id, &txq->mem); 174 if (rc != 0) 175 goto fail_dma_alloc; 176 177 memset(&info, 0, sizeof(info)); 178 info.max_fill_level = txq_max_fill_level; 179 info.free_thresh = txq_info->free_thresh; 180 info.offloads = offloads; 181 info.txq_entries = txq_info->entries; 182 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max; 183 info.txq_hw_ring = txq->mem.esm_base; 184 info.evq_entries = evq_entries; 185 info.evq_hw_ring = evq->mem.esm_base; 186 info.hw_index = txq->hw_index; 187 info.mem_bar = sa->mem_bar.esb_base; 188 info.vi_window_shift = encp->enc_vi_window_shift; 189 info.tso_tcp_header_offset_limit = 190 encp->enc_tx_tso_tcp_header_offset_limit; 191 info.tso_max_nb_header_descs = 192 RTE_MIN(encp->enc_tx_tso_max_header_ndescs, 193 (uint32_t)UINT16_MAX); 194 info.tso_max_header_len = 195 RTE_MIN(encp->enc_tx_tso_max_header_length, 196 (uint32_t)UINT16_MAX); 197 info.tso_max_nb_payload_descs = 198 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs, 199 (uint32_t)UINT16_MAX); 200 info.tso_max_payload_len = encp->enc_tx_tso_max_payload_length; 201 info.tso_max_nb_outgoing_frames = encp->enc_tx_tso_max_nframes; 202 203 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index, 204 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 205 socket_id, &info, &txq_info->dp); 206 if (rc != 0) 207 goto fail_dp_tx_qinit; 208 209 evq->dp_txq = txq_info->dp; 210 211 txq_info->state = SFC_TXQ_INITIALIZED; 212 213 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0); 214 215 return 0; 216 217 fail_dp_tx_qinit: 218 sfc_dma_free(sa, &txq->mem); 219 220 fail_dma_alloc: 221 sfc_ev_qfini(evq); 222 223 fail_ev_qinit: 224 txq_info->entries = 0; 225 226 fail_bad_conf: 227 fail_size_up_rings: 228 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc); 229 return rc; 230 } 231 232 void 233 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 234 { 235 struct sfc_txq_info *txq_info; 236 struct sfc_txq *txq; 237 238 sfc_log_init(sa, "TxQ = %u", sw_index); 239 240 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 241 sa->eth_dev->data->tx_queues[sw_index] = NULL; 242 243 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 244 245 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 246 247 sa->priv.dp_tx->qdestroy(txq_info->dp); 248 txq_info->dp = NULL; 249 250 txq_info->state &= ~SFC_TXQ_INITIALIZED; 251 txq_info->entries = 0; 252 253 txq = &sa->txq_ctrl[sw_index]; 254 255 sfc_dma_free(sa, &txq->mem); 256 257 sfc_ev_qfini(txq->evq); 258 txq->evq = NULL; 259 } 260 261 static int 262 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 263 { 264 sfc_log_init(sa, "TxQ = %u", sw_index); 265 266 return 0; 267 } 268 269 static int 270 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode) 271 { 272 int rc = 0; 273 274 switch (txmode->mq_mode) { 275 case ETH_MQ_TX_NONE: 276 break; 277 default: 278 sfc_err(sa, "Tx multi-queue mode %u not supported", 279 txmode->mq_mode); 280 rc = EINVAL; 281 } 282 283 /* 284 * These features are claimed to be i40e-specific, 285 * but it does make sense to double-check their absence 286 */ 287 if (txmode->hw_vlan_reject_tagged) { 288 sfc_err(sa, "Rejecting tagged packets not supported"); 289 rc = EINVAL; 290 } 291 292 if (txmode->hw_vlan_reject_untagged) { 293 sfc_err(sa, "Rejecting untagged packets not supported"); 294 rc = EINVAL; 295 } 296 297 if (txmode->hw_vlan_insert_pvid) { 298 sfc_err(sa, "Port-based VLAN insertion not supported"); 299 rc = EINVAL; 300 } 301 302 return rc; 303 } 304 305 /** 306 * Destroy excess queues that are no longer needed after reconfiguration 307 * or complete close. 308 */ 309 static void 310 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues) 311 { 312 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 313 int sw_index; 314 315 SFC_ASSERT(nb_tx_queues <= sas->txq_count); 316 317 sw_index = sas->txq_count; 318 while (--sw_index >= (int)nb_tx_queues) { 319 if (sas->txq_info[sw_index].state & SFC_TXQ_INITIALIZED) 320 sfc_tx_qfini(sa, sw_index); 321 } 322 323 sas->txq_count = nb_tx_queues; 324 } 325 326 int 327 sfc_tx_configure(struct sfc_adapter *sa) 328 { 329 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 330 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 331 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 332 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues; 333 int rc = 0; 334 335 sfc_log_init(sa, "nb_tx_queues=%u (old %u)", 336 nb_tx_queues, sas->txq_count); 337 338 /* 339 * The datapath implementation assumes absence of boundary 340 * limits on Tx DMA descriptors. Addition of these checks on 341 * datapath would simply make the datapath slower. 342 */ 343 if (encp->enc_tx_dma_desc_boundary != 0) { 344 rc = ENOTSUP; 345 goto fail_tx_dma_desc_boundary; 346 } 347 348 rc = sfc_tx_check_mode(sa, &dev_conf->txmode); 349 if (rc != 0) 350 goto fail_check_mode; 351 352 if (nb_tx_queues == sas->txq_count) 353 goto done; 354 355 if (sas->txq_info == NULL) { 356 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues, 357 sizeof(sas->txq_info[0]), 0, 358 sa->socket_id); 359 if (sas->txq_info == NULL) 360 goto fail_txqs_alloc; 361 362 /* 363 * Allocate primary process only TxQ control from heap 364 * since it should not be shared. 365 */ 366 rc = ENOMEM; 367 sa->txq_ctrl = calloc(nb_tx_queues, sizeof(sa->txq_ctrl[0])); 368 if (sa->txq_ctrl == NULL) 369 goto fail_txqs_ctrl_alloc; 370 } else { 371 struct sfc_txq_info *new_txq_info; 372 struct sfc_txq *new_txq_ctrl; 373 374 if (nb_tx_queues < sas->txq_count) 375 sfc_tx_fini_queues(sa, nb_tx_queues); 376 377 new_txq_info = 378 rte_realloc(sas->txq_info, 379 nb_tx_queues * sizeof(sas->txq_info[0]), 0); 380 if (new_txq_info == NULL && nb_tx_queues > 0) 381 goto fail_txqs_realloc; 382 383 new_txq_ctrl = realloc(sa->txq_ctrl, 384 nb_tx_queues * sizeof(sa->txq_ctrl[0])); 385 if (new_txq_ctrl == NULL && nb_tx_queues > 0) 386 goto fail_txqs_ctrl_realloc; 387 388 sas->txq_info = new_txq_info; 389 sa->txq_ctrl = new_txq_ctrl; 390 if (nb_tx_queues > sas->txq_count) { 391 memset(&sas->txq_info[sas->txq_count], 0, 392 (nb_tx_queues - sas->txq_count) * 393 sizeof(sas->txq_info[0])); 394 memset(&sa->txq_ctrl[sas->txq_count], 0, 395 (nb_tx_queues - sas->txq_count) * 396 sizeof(sa->txq_ctrl[0])); 397 } 398 } 399 400 while (sas->txq_count < nb_tx_queues) { 401 rc = sfc_tx_qinit_info(sa, sas->txq_count); 402 if (rc != 0) 403 goto fail_tx_qinit_info; 404 405 sas->txq_count++; 406 } 407 408 done: 409 return 0; 410 411 fail_tx_qinit_info: 412 fail_txqs_ctrl_realloc: 413 fail_txqs_realloc: 414 fail_txqs_ctrl_alloc: 415 fail_txqs_alloc: 416 sfc_tx_close(sa); 417 418 fail_check_mode: 419 fail_tx_dma_desc_boundary: 420 sfc_log_init(sa, "failed (rc = %d)", rc); 421 return rc; 422 } 423 424 void 425 sfc_tx_close(struct sfc_adapter *sa) 426 { 427 sfc_tx_fini_queues(sa, 0); 428 429 free(sa->txq_ctrl); 430 sa->txq_ctrl = NULL; 431 432 rte_free(sfc_sa2shared(sa)->txq_info); 433 sfc_sa2shared(sa)->txq_info = NULL; 434 } 435 436 int 437 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 438 { 439 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 440 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) | 441 sfc_tx_get_queue_offload_caps(sa); 442 struct rte_eth_dev_data *dev_data; 443 struct sfc_txq_info *txq_info; 444 struct sfc_txq *txq; 445 struct sfc_evq *evq; 446 uint16_t flags = 0; 447 unsigned int desc_index; 448 int rc = 0; 449 450 sfc_log_init(sa, "TxQ = %u", sw_index); 451 452 SFC_ASSERT(sw_index < sas->txq_count); 453 txq_info = &sas->txq_info[sw_index]; 454 455 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 456 457 txq = &sa->txq_ctrl[sw_index]; 458 evq = txq->evq; 459 460 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index)); 461 if (rc != 0) 462 goto fail_ev_qstart; 463 464 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 465 flags |= EFX_TXQ_CKSUM_IPV4; 466 467 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) 468 flags |= EFX_TXQ_CKSUM_INNER_IPV4; 469 470 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 471 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 472 flags |= EFX_TXQ_CKSUM_TCPUDP; 473 474 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) 475 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP; 476 } 477 478 if (txq_info->offloads & (DEV_TX_OFFLOAD_TCP_TSO | 479 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 480 DEV_TX_OFFLOAD_GENEVE_TNL_TSO)) 481 flags |= EFX_TXQ_FATSOV2; 482 483 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem, 484 txq_info->entries, 0 /* not used on EF10 */, 485 flags, evq->common, 486 &txq->common, &desc_index); 487 if (rc != 0) { 488 if (sa->tso && (rc == ENOSPC)) 489 sfc_err(sa, "ran out of TSO contexts"); 490 491 goto fail_tx_qcreate; 492 } 493 494 efx_tx_qenable(txq->common); 495 496 txq_info->state |= SFC_TXQ_STARTED; 497 498 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index); 499 if (rc != 0) 500 goto fail_dp_qstart; 501 502 /* 503 * It seems to be used by DPDK for debug purposes only ('rte_ether') 504 */ 505 dev_data = sa->eth_dev->data; 506 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED; 507 508 return 0; 509 510 fail_dp_qstart: 511 txq_info->state = SFC_TXQ_INITIALIZED; 512 efx_tx_qdestroy(txq->common); 513 514 fail_tx_qcreate: 515 sfc_ev_qstop(evq); 516 517 fail_ev_qstart: 518 return rc; 519 } 520 521 void 522 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 523 { 524 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 525 struct rte_eth_dev_data *dev_data; 526 struct sfc_txq_info *txq_info; 527 struct sfc_txq *txq; 528 unsigned int retry_count; 529 unsigned int wait_count; 530 int rc; 531 532 sfc_log_init(sa, "TxQ = %u", sw_index); 533 534 SFC_ASSERT(sw_index < sas->txq_count); 535 txq_info = &sas->txq_info[sw_index]; 536 537 if (txq_info->state == SFC_TXQ_INITIALIZED) 538 return; 539 540 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED); 541 542 txq = &sa->txq_ctrl[sw_index]; 543 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr); 544 545 /* 546 * Retry TX queue flushing in case of flush failed or 547 * timeout; in the worst case it can delay for 6 seconds 548 */ 549 for (retry_count = 0; 550 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) && 551 (retry_count < SFC_TX_QFLUSH_ATTEMPTS); 552 ++retry_count) { 553 rc = efx_tx_qflush(txq->common); 554 if (rc != 0) { 555 txq_info->state |= (rc == EALREADY) ? 556 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED; 557 break; 558 } 559 560 /* 561 * Wait for TX queue flush done or flush failed event at least 562 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more 563 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied 564 * by SFC_TX_QFLUSH_POLL_ATTEMPTS) 565 */ 566 wait_count = 0; 567 do { 568 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS); 569 sfc_ev_qpoll(txq->evq); 570 } while ((txq_info->state & SFC_TXQ_FLUSHING) && 571 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS); 572 573 if (txq_info->state & SFC_TXQ_FLUSHING) 574 sfc_err(sa, "TxQ %u flush timed out", sw_index); 575 576 if (txq_info->state & SFC_TXQ_FLUSHED) 577 sfc_notice(sa, "TxQ %u flushed", sw_index); 578 } 579 580 sa->priv.dp_tx->qreap(txq_info->dp); 581 582 txq_info->state = SFC_TXQ_INITIALIZED; 583 584 efx_tx_qdestroy(txq->common); 585 586 sfc_ev_qstop(txq->evq); 587 588 /* 589 * It seems to be used by DPDK for debug purposes only ('rte_ether') 590 */ 591 dev_data = sa->eth_dev->data; 592 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED; 593 } 594 595 int 596 sfc_tx_start(struct sfc_adapter *sa) 597 { 598 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 599 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 600 unsigned int sw_index; 601 int rc = 0; 602 603 sfc_log_init(sa, "txq_count = %u", sas->txq_count); 604 605 if (sa->tso) { 606 if (!encp->enc_fw_assisted_tso_v2_enabled && 607 !encp->enc_tso_v3_enabled) { 608 sfc_warn(sa, "TSO support was unable to be restored"); 609 sa->tso = B_FALSE; 610 sa->tso_encap = B_FALSE; 611 } 612 } 613 614 if (sa->tso_encap && !encp->enc_fw_assisted_tso_v2_encap_enabled && 615 !encp->enc_tso_v3_enabled) { 616 sfc_warn(sa, "Encapsulated TSO support was unable to be restored"); 617 sa->tso_encap = B_FALSE; 618 } 619 620 rc = efx_tx_init(sa->nic); 621 if (rc != 0) 622 goto fail_efx_tx_init; 623 624 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) { 625 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED && 626 (!(sas->txq_info[sw_index].deferred_start) || 627 sas->txq_info[sw_index].deferred_started)) { 628 rc = sfc_tx_qstart(sa, sw_index); 629 if (rc != 0) 630 goto fail_tx_qstart; 631 } 632 } 633 634 return 0; 635 636 fail_tx_qstart: 637 while (sw_index-- > 0) 638 sfc_tx_qstop(sa, sw_index); 639 640 efx_tx_fini(sa->nic); 641 642 fail_efx_tx_init: 643 sfc_log_init(sa, "failed (rc = %d)", rc); 644 return rc; 645 } 646 647 void 648 sfc_tx_stop(struct sfc_adapter *sa) 649 { 650 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 651 unsigned int sw_index; 652 653 sfc_log_init(sa, "txq_count = %u", sas->txq_count); 654 655 sw_index = sas->txq_count; 656 while (sw_index-- > 0) { 657 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED) 658 sfc_tx_qstop(sa, sw_index); 659 } 660 661 efx_tx_fini(sa->nic); 662 } 663 664 static void 665 sfc_efx_tx_reap(struct sfc_efx_txq *txq) 666 { 667 unsigned int completed; 668 669 sfc_ev_qpoll(txq->evq); 670 671 for (completed = txq->completed; 672 completed != txq->pending; completed++) { 673 struct sfc_efx_tx_sw_desc *txd; 674 675 txd = &txq->sw_ring[completed & txq->ptr_mask]; 676 677 if (txd->mbuf != NULL) { 678 rte_pktmbuf_free(txd->mbuf); 679 txd->mbuf = NULL; 680 } 681 } 682 683 txq->completed = completed; 684 } 685 686 /* 687 * The function is used to insert or update VLAN tag; 688 * the firmware has state of the firmware tag to insert per TxQ 689 * (controlled by option descriptors), hence, if the tag of the 690 * packet to be sent is different from one remembered by the firmware, 691 * the function will update it 692 */ 693 static unsigned int 694 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m, 695 efx_desc_t **pend) 696 { 697 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ? 698 m->vlan_tci : 0); 699 700 if (this_tag == txq->hw_vlan_tci) 701 return 0; 702 703 /* 704 * The expression inside SFC_ASSERT() is not desired to be checked in 705 * a non-debug build because it might be too expensive on the data path 706 */ 707 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled); 708 709 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag), 710 *pend); 711 (*pend)++; 712 txq->hw_vlan_tci = this_tag; 713 714 return 1; 715 } 716 717 static uint16_t 718 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 719 uint16_t nb_pkts) 720 { 721 struct sfc_dp_txq *dp_txq = tx_queue; 722 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 723 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic); 724 uint16_t i; 725 726 for (i = 0; i < nb_pkts; i++) { 727 int ret; 728 729 /* 730 * EFX Tx datapath may require extra VLAN descriptor if VLAN 731 * insertion offload is requested regardless the offload 732 * requested/supported. 733 */ 734 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i], 0, SFC_TSOH_STD_LEN, 735 encp->enc_tx_tso_tcp_header_offset_limit, 736 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS, 737 1); 738 if (unlikely(ret != 0)) { 739 rte_errno = ret; 740 break; 741 } 742 } 743 744 return i; 745 } 746 747 static uint16_t 748 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 749 { 750 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue; 751 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 752 unsigned int added = txq->added; 753 unsigned int pushed = added; 754 unsigned int pkts_sent = 0; 755 efx_desc_t *pend = &txq->pend_desc[0]; 756 const unsigned int hard_max_fill = txq->max_fill_level; 757 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh; 758 unsigned int fill_level = added - txq->completed; 759 boolean_t reap_done; 760 int rc __rte_unused; 761 struct rte_mbuf **pktp; 762 763 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0)) 764 goto done; 765 766 /* 767 * If insufficient space for a single packet is present, 768 * we should reap; otherwise, we shouldn't do that all the time 769 * to avoid latency increase 770 */ 771 reap_done = (fill_level > soft_max_fill); 772 773 if (reap_done) { 774 sfc_efx_tx_reap(txq); 775 /* 776 * Recalculate fill level since 'txq->completed' 777 * might have changed on reap 778 */ 779 fill_level = added - txq->completed; 780 } 781 782 for (pkts_sent = 0, pktp = &tx_pkts[0]; 783 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill); 784 pkts_sent++, pktp++) { 785 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci; 786 struct rte_mbuf *m_seg = *pktp; 787 size_t pkt_len = m_seg->pkt_len; 788 unsigned int pkt_descs = 0; 789 size_t in_off = 0; 790 791 /* 792 * Here VLAN TCI is expected to be zero in case if no 793 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised; 794 * if the calling app ignores the absence of 795 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then 796 * TX_ERROR will occur 797 */ 798 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend); 799 800 if (m_seg->ol_flags & PKT_TX_TCP_SEG) { 801 /* 802 * We expect correct 'pkt->l[2, 3, 4]_len' values 803 * to be set correctly by the caller 804 */ 805 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend, 806 &pkt_descs, &pkt_len) != 0) { 807 /* We may have reached this place if packet 808 * header linearization is needed but the 809 * header length is greater than 810 * SFC_TSOH_STD_LEN 811 * 812 * We will deceive RTE saying that we have sent 813 * the packet, but we will actually drop it. 814 * Hence, we should revert 'pend' to the 815 * previous state (in case we have added 816 * VLAN descriptor) and start processing 817 * another one packet. But the original 818 * mbuf shouldn't be orphaned 819 */ 820 pend -= pkt_descs; 821 txq->hw_vlan_tci = hw_vlan_tci_prev; 822 823 rte_pktmbuf_free(*pktp); 824 825 continue; 826 } 827 828 /* 829 * We've only added 2 FATSOv2 option descriptors 830 * and 1 descriptor for the linearized packet header. 831 * The outstanding work will be done in the same manner 832 * as for the usual non-TSO path 833 */ 834 } 835 836 for (; m_seg != NULL; m_seg = m_seg->next) { 837 efsys_dma_addr_t next_frag; 838 size_t seg_len; 839 840 seg_len = m_seg->data_len; 841 next_frag = rte_mbuf_data_iova(m_seg); 842 843 /* 844 * If we've started TSO transaction few steps earlier, 845 * we'll skip packet header using an offset in the 846 * current segment (which has been set to the 847 * first one containing payload) 848 */ 849 seg_len -= in_off; 850 next_frag += in_off; 851 in_off = 0; 852 853 do { 854 efsys_dma_addr_t frag_addr = next_frag; 855 size_t frag_len; 856 857 /* 858 * It is assumed here that there is no 859 * limitation on address boundary 860 * crossing by DMA descriptor. 861 */ 862 frag_len = MIN(seg_len, txq->dma_desc_size_max); 863 next_frag += frag_len; 864 seg_len -= frag_len; 865 pkt_len -= frag_len; 866 867 efx_tx_qdesc_dma_create(txq->common, 868 frag_addr, frag_len, 869 (pkt_len == 0), 870 pend++); 871 872 pkt_descs++; 873 } while (seg_len != 0); 874 } 875 876 added += pkt_descs; 877 878 fill_level += pkt_descs; 879 if (unlikely(fill_level > hard_max_fill)) { 880 /* 881 * Our estimation for maximum number of descriptors 882 * required to send a packet seems to be wrong. 883 * Try to reap (if we haven't yet). 884 */ 885 if (!reap_done) { 886 sfc_efx_tx_reap(txq); 887 reap_done = B_TRUE; 888 fill_level = added - txq->completed; 889 if (fill_level > hard_max_fill) { 890 pend -= pkt_descs; 891 txq->hw_vlan_tci = hw_vlan_tci_prev; 892 break; 893 } 894 } else { 895 pend -= pkt_descs; 896 txq->hw_vlan_tci = hw_vlan_tci_prev; 897 break; 898 } 899 } 900 901 /* Assign mbuf to the last used desc */ 902 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp; 903 } 904 905 if (likely(pkts_sent > 0)) { 906 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, 907 pend - &txq->pend_desc[0], 908 txq->completed, &txq->added); 909 SFC_ASSERT(rc == 0); 910 911 if (likely(pushed != txq->added)) 912 efx_tx_qpush(txq->common, txq->added, pushed); 913 } 914 915 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE 916 if (!reap_done) 917 sfc_efx_tx_reap(txq); 918 #endif 919 920 done: 921 return pkts_sent; 922 } 923 924 const struct sfc_dp_tx * 925 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq) 926 { 927 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 928 struct rte_eth_dev *eth_dev; 929 struct sfc_adapter_priv *sap; 930 931 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 932 eth_dev = &rte_eth_devices[dpq->port_id]; 933 934 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 935 936 return sap->dp_tx; 937 } 938 939 struct sfc_txq_info * 940 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq) 941 { 942 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 943 struct rte_eth_dev *eth_dev; 944 struct sfc_adapter_shared *sas; 945 946 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 947 eth_dev = &rte_eth_devices[dpq->port_id]; 948 949 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 950 951 SFC_ASSERT(dpq->queue_id < sas->txq_count); 952 return &sas->txq_info[dpq->queue_id]; 953 } 954 955 struct sfc_txq * 956 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq) 957 { 958 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 959 struct rte_eth_dev *eth_dev; 960 struct sfc_adapter *sa; 961 962 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 963 eth_dev = &rte_eth_devices[dpq->port_id]; 964 965 sa = sfc_adapter_by_eth_dev(eth_dev); 966 967 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count); 968 return &sa->txq_ctrl[dpq->queue_id]; 969 } 970 971 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings; 972 static int 973 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc, 974 __rte_unused struct sfc_dp_tx_hw_limits *limits, 975 unsigned int *txq_entries, 976 unsigned int *evq_entries, 977 unsigned int *txq_max_fill_level) 978 { 979 *txq_entries = nb_tx_desc; 980 *evq_entries = nb_tx_desc; 981 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries); 982 return 0; 983 } 984 985 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate; 986 static int 987 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id, 988 const struct rte_pci_addr *pci_addr, 989 int socket_id, 990 const struct sfc_dp_tx_qcreate_info *info, 991 struct sfc_dp_txq **dp_txqp) 992 { 993 struct sfc_efx_txq *txq; 994 struct sfc_txq *ctrl_txq; 995 int rc; 996 997 rc = ENOMEM; 998 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq), 999 RTE_CACHE_LINE_SIZE, socket_id); 1000 if (txq == NULL) 1001 goto fail_txq_alloc; 1002 1003 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr); 1004 1005 rc = ENOMEM; 1006 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc", 1007 EFX_TXQ_LIMIT(info->txq_entries), 1008 sizeof(*txq->pend_desc), 0, 1009 socket_id); 1010 if (txq->pend_desc == NULL) 1011 goto fail_pend_desc_alloc; 1012 1013 rc = ENOMEM; 1014 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring", 1015 info->txq_entries, 1016 sizeof(*txq->sw_ring), 1017 RTE_CACHE_LINE_SIZE, socket_id); 1018 if (txq->sw_ring == NULL) 1019 goto fail_sw_ring_alloc; 1020 1021 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp); 1022 if (ctrl_txq->evq->sa->tso) { 1023 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring, 1024 info->txq_entries, socket_id); 1025 if (rc != 0) 1026 goto fail_alloc_tsoh_objs; 1027 } 1028 1029 txq->evq = ctrl_txq->evq; 1030 txq->ptr_mask = info->txq_entries - 1; 1031 txq->max_fill_level = info->max_fill_level; 1032 txq->free_thresh = info->free_thresh; 1033 txq->dma_desc_size_max = info->dma_desc_size_max; 1034 1035 *dp_txqp = &txq->dp; 1036 return 0; 1037 1038 fail_alloc_tsoh_objs: 1039 rte_free(txq->sw_ring); 1040 1041 fail_sw_ring_alloc: 1042 rte_free(txq->pend_desc); 1043 1044 fail_pend_desc_alloc: 1045 rte_free(txq); 1046 1047 fail_txq_alloc: 1048 return rc; 1049 } 1050 1051 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy; 1052 static void 1053 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq) 1054 { 1055 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1056 1057 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1); 1058 rte_free(txq->sw_ring); 1059 rte_free(txq->pend_desc); 1060 rte_free(txq); 1061 } 1062 1063 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart; 1064 static int 1065 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq, 1066 __rte_unused unsigned int evq_read_ptr, 1067 unsigned int txq_desc_index) 1068 { 1069 /* libefx-based datapath is specific to libefx-based PMD */ 1070 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1071 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq); 1072 1073 txq->common = ctrl_txq->common; 1074 1075 txq->pending = txq->completed = txq->added = txq_desc_index; 1076 txq->hw_vlan_tci = 0; 1077 1078 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING); 1079 1080 return 0; 1081 } 1082 1083 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop; 1084 static void 1085 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq, 1086 __rte_unused unsigned int *evq_read_ptr) 1087 { 1088 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1089 1090 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING; 1091 } 1092 1093 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap; 1094 static void 1095 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq) 1096 { 1097 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1098 unsigned int txds; 1099 1100 sfc_efx_tx_reap(txq); 1101 1102 for (txds = 0; txds <= txq->ptr_mask; txds++) { 1103 if (txq->sw_ring[txds].mbuf != NULL) { 1104 rte_pktmbuf_free(txq->sw_ring[txds].mbuf); 1105 txq->sw_ring[txds].mbuf = NULL; 1106 } 1107 } 1108 1109 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED; 1110 } 1111 1112 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status; 1113 static int 1114 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset) 1115 { 1116 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1117 1118 if (unlikely(offset > txq->ptr_mask)) 1119 return -EINVAL; 1120 1121 if (unlikely(offset >= txq->max_fill_level)) 1122 return RTE_ETH_TX_DESC_UNAVAIL; 1123 1124 /* 1125 * Poll EvQ to derive up-to-date 'txq->pending' figure; 1126 * it is required for the queue to be running, but the 1127 * check is omitted because API design assumes that it 1128 * is the duty of the caller to satisfy all conditions 1129 */ 1130 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 1131 SFC_EFX_TXQ_FLAG_RUNNING); 1132 sfc_ev_qpoll(txq->evq); 1133 1134 /* 1135 * Ring tail is 'txq->pending', and although descriptors 1136 * between 'txq->completed' and 'txq->pending' are still 1137 * in use by the driver, they should be reported as DONE 1138 */ 1139 if (unlikely(offset < (txq->added - txq->pending))) 1140 return RTE_ETH_TX_DESC_FULL; 1141 1142 /* 1143 * There is no separate return value for unused descriptors; 1144 * the latter will be reported as DONE because genuine DONE 1145 * descriptors will be freed anyway in SW on the next burst 1146 */ 1147 return RTE_ETH_TX_DESC_DONE; 1148 } 1149 1150 struct sfc_dp_tx sfc_efx_tx = { 1151 .dp = { 1152 .name = SFC_KVARG_DATAPATH_EFX, 1153 .type = SFC_DP_TX, 1154 .hw_fw_caps = SFC_DP_HW_FW_CAP_TX_EFX, 1155 }, 1156 .features = 0, 1157 .dev_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 1158 DEV_TX_OFFLOAD_MULTI_SEGS, 1159 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM | 1160 DEV_TX_OFFLOAD_UDP_CKSUM | 1161 DEV_TX_OFFLOAD_TCP_CKSUM | 1162 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1163 DEV_TX_OFFLOAD_TCP_TSO, 1164 .qsize_up_rings = sfc_efx_tx_qsize_up_rings, 1165 .qcreate = sfc_efx_tx_qcreate, 1166 .qdestroy = sfc_efx_tx_qdestroy, 1167 .qstart = sfc_efx_tx_qstart, 1168 .qstop = sfc_efx_tx_qstop, 1169 .qreap = sfc_efx_tx_qreap, 1170 .qdesc_status = sfc_efx_tx_qdesc_status, 1171 .pkt_prepare = sfc_efx_prepare_pkts, 1172 .pkt_burst = sfc_efx_xmit_pkts, 1173 }; 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