1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016-2018 Solarflare Communications Inc. 4 * All rights reserved. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include "sfc.h" 11 #include "sfc_debug.h" 12 #include "sfc_log.h" 13 #include "sfc_ev.h" 14 #include "sfc_tx.h" 15 #include "sfc_tweak.h" 16 #include "sfc_kvargs.h" 17 18 /* 19 * Maximum number of TX queue flush attempts in case of 20 * failure or flush timeout 21 */ 22 #define SFC_TX_QFLUSH_ATTEMPTS (3) 23 24 /* 25 * Time to wait between event queue polling attempts when waiting for TX 26 * queue flush done or flush failed events 27 */ 28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1) 29 30 /* 31 * Maximum number of event queue polling attempts when waiting for TX queue 32 * flush done or flush failed events; it defines TX queue flush attempt timeout 33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS 34 */ 35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000) 36 37 uint64_t 38 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa) 39 { 40 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 41 uint64_t caps = 0; 42 43 if ((sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) && 44 encp->enc_hw_tx_insert_vlan_enabled) 45 caps |= DEV_TX_OFFLOAD_VLAN_INSERT; 46 47 if (sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG) 48 caps |= DEV_TX_OFFLOAD_MULTI_SEGS; 49 50 if ((~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_POOL) && 51 (~sa->dp_tx->features & SFC_DP_TX_FEAT_REFCNT)) 52 caps |= DEV_TX_OFFLOAD_MBUF_FAST_FREE; 53 54 return caps; 55 } 56 57 uint64_t 58 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa) 59 { 60 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 61 uint64_t caps = 0; 62 63 caps |= DEV_TX_OFFLOAD_IPV4_CKSUM; 64 caps |= DEV_TX_OFFLOAD_UDP_CKSUM; 65 caps |= DEV_TX_OFFLOAD_TCP_CKSUM; 66 67 if (encp->enc_tunnel_encapsulations_supported) 68 caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 69 70 if (sa->tso) 71 caps |= DEV_TX_OFFLOAD_TCP_TSO; 72 73 return caps; 74 } 75 76 static void 77 sfc_tx_log_offloads(struct sfc_adapter *sa, const char *offload_group, 78 const char *verdict, uint64_t offloads) 79 { 80 unsigned long long bit; 81 82 while ((bit = __builtin_ffsll(offloads)) != 0) { 83 uint64_t flag = (1ULL << --bit); 84 85 sfc_err(sa, "Tx %s offload %s %s", offload_group, 86 rte_eth_dev_tx_offload_name(flag), verdict); 87 88 offloads &= ~flag; 89 } 90 } 91 92 static int 93 sfc_tx_queue_offload_mismatch(struct sfc_adapter *sa, uint64_t requested) 94 { 95 uint64_t mandatory = sa->eth_dev->data->dev_conf.txmode.offloads; 96 uint64_t supported = sfc_tx_get_dev_offload_caps(sa) | 97 sfc_tx_get_queue_offload_caps(sa); 98 uint64_t rejected = requested & ~supported; 99 uint64_t missing = (requested & mandatory) ^ mandatory; 100 boolean_t mismatch = B_FALSE; 101 102 if (rejected) { 103 sfc_tx_log_offloads(sa, "queue", "is unsupported", rejected); 104 mismatch = B_TRUE; 105 } 106 107 if (missing) { 108 sfc_tx_log_offloads(sa, "queue", "must be set", missing); 109 mismatch = B_TRUE; 110 } 111 112 return mismatch; 113 } 114 115 static int 116 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level, 117 const struct rte_eth_txconf *tx_conf) 118 { 119 int rc = 0; 120 121 if (tx_conf->tx_rs_thresh != 0) { 122 sfc_err(sa, "RS bit in transmit descriptor is not supported"); 123 rc = EINVAL; 124 } 125 126 if (tx_conf->tx_free_thresh > txq_max_fill_level) { 127 sfc_err(sa, 128 "TxQ free threshold too large: %u vs maximum %u", 129 tx_conf->tx_free_thresh, txq_max_fill_level); 130 rc = EINVAL; 131 } 132 133 if (tx_conf->tx_thresh.pthresh != 0 || 134 tx_conf->tx_thresh.hthresh != 0 || 135 tx_conf->tx_thresh.wthresh != 0) { 136 sfc_warn(sa, 137 "prefetch/host/writeback thresholds are not supported"); 138 } 139 140 /* We either perform both TCP and UDP offload, or no offload at all */ 141 if (((tx_conf->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) != 142 ((tx_conf->offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) { 143 sfc_err(sa, "TCP and UDP offloads can't be set independently"); 144 rc = EINVAL; 145 } 146 147 if (sfc_tx_queue_offload_mismatch(sa, tx_conf->offloads)) 148 rc = EINVAL; 149 150 return rc; 151 } 152 153 void 154 sfc_tx_qflush_done(struct sfc_txq *txq) 155 { 156 txq->state |= SFC_TXQ_FLUSHED; 157 txq->state &= ~SFC_TXQ_FLUSHING; 158 } 159 160 int 161 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 162 uint16_t nb_tx_desc, unsigned int socket_id, 163 const struct rte_eth_txconf *tx_conf) 164 { 165 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 166 unsigned int txq_entries; 167 unsigned int evq_entries; 168 unsigned int txq_max_fill_level; 169 struct sfc_txq_info *txq_info; 170 struct sfc_evq *evq; 171 struct sfc_txq *txq; 172 int rc = 0; 173 struct sfc_dp_tx_qcreate_info info; 174 175 sfc_log_init(sa, "TxQ = %u", sw_index); 176 177 rc = sa->dp_tx->qsize_up_rings(nb_tx_desc, &txq_entries, &evq_entries, 178 &txq_max_fill_level); 179 if (rc != 0) 180 goto fail_size_up_rings; 181 SFC_ASSERT(txq_entries >= EFX_TXQ_MINNDESCS); 182 SFC_ASSERT(txq_entries <= sa->txq_max_entries); 183 SFC_ASSERT(txq_entries >= nb_tx_desc); 184 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc); 185 186 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf); 187 if (rc != 0) 188 goto fail_bad_conf; 189 190 SFC_ASSERT(sw_index < sa->txq_count); 191 txq_info = &sa->txq_info[sw_index]; 192 193 txq_info->entries = txq_entries; 194 195 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index, 196 evq_entries, socket_id, &evq); 197 if (rc != 0) 198 goto fail_ev_qinit; 199 200 rc = ENOMEM; 201 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id); 202 if (txq == NULL) 203 goto fail_txq_alloc; 204 205 txq_info->txq = txq; 206 207 txq->hw_index = sw_index; 208 txq->evq = evq; 209 txq->free_thresh = 210 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh : 211 SFC_TX_DEFAULT_FREE_THRESH; 212 txq->flags = tx_conf->txq_flags; 213 txq->offloads = tx_conf->offloads; 214 215 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries), 216 socket_id, &txq->mem); 217 if (rc != 0) 218 goto fail_dma_alloc; 219 220 memset(&info, 0, sizeof(info)); 221 info.max_fill_level = txq_max_fill_level; 222 info.free_thresh = txq->free_thresh; 223 info.flags = tx_conf->txq_flags; 224 info.offloads = tx_conf->offloads; 225 info.txq_entries = txq_info->entries; 226 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max; 227 info.txq_hw_ring = txq->mem.esm_base; 228 info.evq_entries = evq_entries; 229 info.evq_hw_ring = evq->mem.esm_base; 230 info.hw_index = txq->hw_index; 231 info.mem_bar = sa->mem_bar.esb_base; 232 233 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index, 234 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 235 socket_id, &info, &txq->dp); 236 if (rc != 0) 237 goto fail_dp_tx_qinit; 238 239 evq->dp_txq = txq->dp; 240 241 txq->state = SFC_TXQ_INITIALIZED; 242 243 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0); 244 245 return 0; 246 247 fail_dp_tx_qinit: 248 sfc_dma_free(sa, &txq->mem); 249 250 fail_dma_alloc: 251 txq_info->txq = NULL; 252 rte_free(txq); 253 254 fail_txq_alloc: 255 sfc_ev_qfini(evq); 256 257 fail_ev_qinit: 258 txq_info->entries = 0; 259 260 fail_bad_conf: 261 fail_size_up_rings: 262 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc); 263 return rc; 264 } 265 266 void 267 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 268 { 269 struct sfc_txq_info *txq_info; 270 struct sfc_txq *txq; 271 272 sfc_log_init(sa, "TxQ = %u", sw_index); 273 274 SFC_ASSERT(sw_index < sa->txq_count); 275 txq_info = &sa->txq_info[sw_index]; 276 277 txq = txq_info->txq; 278 SFC_ASSERT(txq != NULL); 279 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED); 280 281 sa->dp_tx->qdestroy(txq->dp); 282 txq->dp = NULL; 283 284 txq_info->txq = NULL; 285 txq_info->entries = 0; 286 287 sfc_dma_free(sa, &txq->mem); 288 289 sfc_ev_qfini(txq->evq); 290 txq->evq = NULL; 291 292 rte_free(txq); 293 } 294 295 static int 296 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 297 { 298 sfc_log_init(sa, "TxQ = %u", sw_index); 299 300 return 0; 301 } 302 303 static int 304 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode) 305 { 306 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) | 307 sfc_tx_get_queue_offload_caps(sa); 308 uint64_t offloads_rejected = txmode->offloads & ~offloads_supported; 309 int rc = 0; 310 311 switch (txmode->mq_mode) { 312 case ETH_MQ_TX_NONE: 313 break; 314 default: 315 sfc_err(sa, "Tx multi-queue mode %u not supported", 316 txmode->mq_mode); 317 rc = EINVAL; 318 } 319 320 /* 321 * These features are claimed to be i40e-specific, 322 * but it does make sense to double-check their absence 323 */ 324 if (txmode->hw_vlan_reject_tagged) { 325 sfc_err(sa, "Rejecting tagged packets not supported"); 326 rc = EINVAL; 327 } 328 329 if (txmode->hw_vlan_reject_untagged) { 330 sfc_err(sa, "Rejecting untagged packets not supported"); 331 rc = EINVAL; 332 } 333 334 if (txmode->hw_vlan_insert_pvid) { 335 sfc_err(sa, "Port-based VLAN insertion not supported"); 336 rc = EINVAL; 337 } 338 339 if (offloads_rejected) { 340 sfc_tx_log_offloads(sa, "device", "is unsupported", 341 offloads_rejected); 342 rc = EINVAL; 343 } 344 345 return rc; 346 } 347 348 /** 349 * Destroy excess queues that are no longer needed after reconfiguration 350 * or complete close. 351 */ 352 static void 353 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues) 354 { 355 int sw_index; 356 357 SFC_ASSERT(nb_tx_queues <= sa->txq_count); 358 359 sw_index = sa->txq_count; 360 while (--sw_index >= (int)nb_tx_queues) { 361 if (sa->txq_info[sw_index].txq != NULL) 362 sfc_tx_qfini(sa, sw_index); 363 } 364 365 sa->txq_count = nb_tx_queues; 366 } 367 368 int 369 sfc_tx_configure(struct sfc_adapter *sa) 370 { 371 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 372 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 373 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues; 374 int rc = 0; 375 376 sfc_log_init(sa, "nb_tx_queues=%u (old %u)", 377 nb_tx_queues, sa->txq_count); 378 379 /* 380 * The datapath implementation assumes absence of boundary 381 * limits on Tx DMA descriptors. Addition of these checks on 382 * datapath would simply make the datapath slower. 383 */ 384 if (encp->enc_tx_dma_desc_boundary != 0) { 385 rc = ENOTSUP; 386 goto fail_tx_dma_desc_boundary; 387 } 388 389 rc = sfc_tx_check_mode(sa, &dev_conf->txmode); 390 if (rc != 0) 391 goto fail_check_mode; 392 393 if (nb_tx_queues == sa->txq_count) 394 goto done; 395 396 if (sa->txq_info == NULL) { 397 sa->txq_info = rte_calloc_socket("sfc-txqs", nb_tx_queues, 398 sizeof(sa->txq_info[0]), 0, 399 sa->socket_id); 400 if (sa->txq_info == NULL) 401 goto fail_txqs_alloc; 402 } else { 403 struct sfc_txq_info *new_txq_info; 404 405 if (nb_tx_queues < sa->txq_count) 406 sfc_tx_fini_queues(sa, nb_tx_queues); 407 408 new_txq_info = 409 rte_realloc(sa->txq_info, 410 nb_tx_queues * sizeof(sa->txq_info[0]), 0); 411 if (new_txq_info == NULL && nb_tx_queues > 0) 412 goto fail_txqs_realloc; 413 414 sa->txq_info = new_txq_info; 415 if (nb_tx_queues > sa->txq_count) 416 memset(&sa->txq_info[sa->txq_count], 0, 417 (nb_tx_queues - sa->txq_count) * 418 sizeof(sa->txq_info[0])); 419 } 420 421 while (sa->txq_count < nb_tx_queues) { 422 rc = sfc_tx_qinit_info(sa, sa->txq_count); 423 if (rc != 0) 424 goto fail_tx_qinit_info; 425 426 sa->txq_count++; 427 } 428 429 done: 430 return 0; 431 432 fail_tx_qinit_info: 433 fail_txqs_realloc: 434 fail_txqs_alloc: 435 sfc_tx_close(sa); 436 437 fail_check_mode: 438 fail_tx_dma_desc_boundary: 439 sfc_log_init(sa, "failed (rc = %d)", rc); 440 return rc; 441 } 442 443 void 444 sfc_tx_close(struct sfc_adapter *sa) 445 { 446 sfc_tx_fini_queues(sa, 0); 447 448 rte_free(sa->txq_info); 449 sa->txq_info = NULL; 450 } 451 452 int 453 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 454 { 455 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) | 456 sfc_tx_get_queue_offload_caps(sa); 457 struct rte_eth_dev_data *dev_data; 458 struct sfc_txq_info *txq_info; 459 struct sfc_txq *txq; 460 struct sfc_evq *evq; 461 uint16_t flags = 0; 462 unsigned int desc_index; 463 int rc = 0; 464 465 sfc_log_init(sa, "TxQ = %u", sw_index); 466 467 SFC_ASSERT(sw_index < sa->txq_count); 468 txq_info = &sa->txq_info[sw_index]; 469 470 txq = txq_info->txq; 471 472 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED); 473 474 evq = txq->evq; 475 476 rc = sfc_ev_qstart(evq, sfc_evq_index_by_txq_sw_index(sa, sw_index)); 477 if (rc != 0) 478 goto fail_ev_qstart; 479 480 /* 481 * The absence of ETH_TXQ_FLAGS_IGNORE is associated with a legacy 482 * application which expects that IPv4 checksum offload is enabled 483 * all the time as there is no legacy flag to turn off the offload. 484 */ 485 if ((txq->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) || 486 (~txq->flags & ETH_TXQ_FLAGS_IGNORE)) 487 flags |= EFX_TXQ_CKSUM_IPV4; 488 489 if ((txq->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) || 490 ((~txq->flags & ETH_TXQ_FLAGS_IGNORE) && 491 (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM))) 492 flags |= EFX_TXQ_CKSUM_INNER_IPV4; 493 494 if ((txq->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 495 (txq->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 496 flags |= EFX_TXQ_CKSUM_TCPUDP; 497 498 if ((~txq->flags & ETH_TXQ_FLAGS_IGNORE) && 499 (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) 500 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP; 501 } 502 503 /* 504 * The absence of ETH_TXQ_FLAGS_IGNORE is associated with a legacy 505 * application. In turn, the absence of ETH_TXQ_FLAGS_NOXSUMTCP is 506 * associated specifically with a legacy application which expects 507 * both TCP checksum offload and TSO to be enabled because the legacy 508 * API does not provide a dedicated mechanism to control TSO. 509 */ 510 if ((txq->offloads & DEV_TX_OFFLOAD_TCP_TSO) || 511 ((~txq->flags & ETH_TXQ_FLAGS_IGNORE) && 512 (~txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP))) 513 flags |= EFX_TXQ_FATSOV2; 514 515 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem, 516 txq_info->entries, 0 /* not used on EF10 */, 517 flags, evq->common, 518 &txq->common, &desc_index); 519 if (rc != 0) { 520 if (sa->tso && (rc == ENOSPC)) 521 sfc_err(sa, "ran out of TSO contexts"); 522 523 goto fail_tx_qcreate; 524 } 525 526 efx_tx_qenable(txq->common); 527 528 txq->state |= SFC_TXQ_STARTED; 529 530 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index); 531 if (rc != 0) 532 goto fail_dp_qstart; 533 534 /* 535 * It seems to be used by DPDK for debug purposes only ('rte_ether') 536 */ 537 dev_data = sa->eth_dev->data; 538 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED; 539 540 return 0; 541 542 fail_dp_qstart: 543 txq->state = SFC_TXQ_INITIALIZED; 544 efx_tx_qdestroy(txq->common); 545 546 fail_tx_qcreate: 547 sfc_ev_qstop(evq); 548 549 fail_ev_qstart: 550 return rc; 551 } 552 553 void 554 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 555 { 556 struct rte_eth_dev_data *dev_data; 557 struct sfc_txq_info *txq_info; 558 struct sfc_txq *txq; 559 unsigned int retry_count; 560 unsigned int wait_count; 561 int rc; 562 563 sfc_log_init(sa, "TxQ = %u", sw_index); 564 565 SFC_ASSERT(sw_index < sa->txq_count); 566 txq_info = &sa->txq_info[sw_index]; 567 568 txq = txq_info->txq; 569 570 if (txq->state == SFC_TXQ_INITIALIZED) 571 return; 572 573 SFC_ASSERT(txq->state & SFC_TXQ_STARTED); 574 575 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr); 576 577 /* 578 * Retry TX queue flushing in case of flush failed or 579 * timeout; in the worst case it can delay for 6 seconds 580 */ 581 for (retry_count = 0; 582 ((txq->state & SFC_TXQ_FLUSHED) == 0) && 583 (retry_count < SFC_TX_QFLUSH_ATTEMPTS); 584 ++retry_count) { 585 rc = efx_tx_qflush(txq->common); 586 if (rc != 0) { 587 txq->state |= (rc == EALREADY) ? 588 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED; 589 break; 590 } 591 592 /* 593 * Wait for TX queue flush done or flush failed event at least 594 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more 595 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied 596 * by SFC_TX_QFLUSH_POLL_ATTEMPTS) 597 */ 598 wait_count = 0; 599 do { 600 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS); 601 sfc_ev_qpoll(txq->evq); 602 } while ((txq->state & SFC_TXQ_FLUSHING) && 603 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS); 604 605 if (txq->state & SFC_TXQ_FLUSHING) 606 sfc_err(sa, "TxQ %u flush timed out", sw_index); 607 608 if (txq->state & SFC_TXQ_FLUSHED) 609 sfc_info(sa, "TxQ %u flushed", sw_index); 610 } 611 612 sa->dp_tx->qreap(txq->dp); 613 614 txq->state = SFC_TXQ_INITIALIZED; 615 616 efx_tx_qdestroy(txq->common); 617 618 sfc_ev_qstop(txq->evq); 619 620 /* 621 * It seems to be used by DPDK for debug purposes only ('rte_ether') 622 */ 623 dev_data = sa->eth_dev->data; 624 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED; 625 } 626 627 int 628 sfc_tx_start(struct sfc_adapter *sa) 629 { 630 unsigned int sw_index; 631 int rc = 0; 632 633 sfc_log_init(sa, "txq_count = %u", sa->txq_count); 634 635 if (sa->tso) { 636 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) { 637 sfc_warn(sa, "TSO support was unable to be restored"); 638 sa->tso = B_FALSE; 639 } 640 } 641 642 rc = efx_tx_init(sa->nic); 643 if (rc != 0) 644 goto fail_efx_tx_init; 645 646 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) { 647 if (!(sa->txq_info[sw_index].deferred_start) || 648 sa->txq_info[sw_index].deferred_started) { 649 rc = sfc_tx_qstart(sa, sw_index); 650 if (rc != 0) 651 goto fail_tx_qstart; 652 } 653 } 654 655 return 0; 656 657 fail_tx_qstart: 658 while (sw_index-- > 0) 659 sfc_tx_qstop(sa, sw_index); 660 661 efx_tx_fini(sa->nic); 662 663 fail_efx_tx_init: 664 sfc_log_init(sa, "failed (rc = %d)", rc); 665 return rc; 666 } 667 668 void 669 sfc_tx_stop(struct sfc_adapter *sa) 670 { 671 unsigned int sw_index; 672 673 sfc_log_init(sa, "txq_count = %u", sa->txq_count); 674 675 sw_index = sa->txq_count; 676 while (sw_index-- > 0) { 677 if (sa->txq_info[sw_index].txq != NULL) 678 sfc_tx_qstop(sa, sw_index); 679 } 680 681 efx_tx_fini(sa->nic); 682 } 683 684 static void 685 sfc_efx_tx_reap(struct sfc_efx_txq *txq) 686 { 687 unsigned int completed; 688 689 sfc_ev_qpoll(txq->evq); 690 691 for (completed = txq->completed; 692 completed != txq->pending; completed++) { 693 struct sfc_efx_tx_sw_desc *txd; 694 695 txd = &txq->sw_ring[completed & txq->ptr_mask]; 696 697 if (txd->mbuf != NULL) { 698 rte_pktmbuf_free(txd->mbuf); 699 txd->mbuf = NULL; 700 } 701 } 702 703 txq->completed = completed; 704 } 705 706 /* 707 * The function is used to insert or update VLAN tag; 708 * the firmware has state of the firmware tag to insert per TxQ 709 * (controlled by option descriptors), hence, if the tag of the 710 * packet to be sent is different from one remembered by the firmware, 711 * the function will update it 712 */ 713 static unsigned int 714 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m, 715 efx_desc_t **pend) 716 { 717 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ? 718 m->vlan_tci : 0); 719 720 if (this_tag == txq->hw_vlan_tci) 721 return 0; 722 723 /* 724 * The expression inside SFC_ASSERT() is not desired to be checked in 725 * a non-debug build because it might be too expensive on the data path 726 */ 727 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled); 728 729 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag), 730 *pend); 731 (*pend)++; 732 txq->hw_vlan_tci = this_tag; 733 734 return 1; 735 } 736 737 static uint16_t 738 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 739 { 740 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue; 741 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 742 unsigned int added = txq->added; 743 unsigned int pushed = added; 744 unsigned int pkts_sent = 0; 745 efx_desc_t *pend = &txq->pend_desc[0]; 746 const unsigned int hard_max_fill = txq->max_fill_level; 747 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh; 748 unsigned int fill_level = added - txq->completed; 749 boolean_t reap_done; 750 int rc __rte_unused; 751 struct rte_mbuf **pktp; 752 753 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0)) 754 goto done; 755 756 /* 757 * If insufficient space for a single packet is present, 758 * we should reap; otherwise, we shouldn't do that all the time 759 * to avoid latency increase 760 */ 761 reap_done = (fill_level > soft_max_fill); 762 763 if (reap_done) { 764 sfc_efx_tx_reap(txq); 765 /* 766 * Recalculate fill level since 'txq->completed' 767 * might have changed on reap 768 */ 769 fill_level = added - txq->completed; 770 } 771 772 for (pkts_sent = 0, pktp = &tx_pkts[0]; 773 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill); 774 pkts_sent++, pktp++) { 775 struct rte_mbuf *m_seg = *pktp; 776 size_t pkt_len = m_seg->pkt_len; 777 unsigned int pkt_descs = 0; 778 size_t in_off = 0; 779 780 /* 781 * Here VLAN TCI is expected to be zero in case if no 782 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised; 783 * if the calling app ignores the absence of 784 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then 785 * TX_ERROR will occur 786 */ 787 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend); 788 789 if (m_seg->ol_flags & PKT_TX_TCP_SEG) { 790 /* 791 * We expect correct 'pkt->l[2, 3, 4]_len' values 792 * to be set correctly by the caller 793 */ 794 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend, 795 &pkt_descs, &pkt_len) != 0) { 796 /* We may have reached this place for 797 * one of the following reasons: 798 * 799 * 1) Packet header length is greater 800 * than SFC_TSOH_STD_LEN 801 * 2) TCP header starts at more then 802 * 208 bytes into the frame 803 * 804 * We will deceive RTE saying that we have sent 805 * the packet, but we will actually drop it. 806 * Hence, we should revert 'pend' to the 807 * previous state (in case we have added 808 * VLAN descriptor) and start processing 809 * another one packet. But the original 810 * mbuf shouldn't be orphaned 811 */ 812 pend -= pkt_descs; 813 814 rte_pktmbuf_free(*pktp); 815 816 continue; 817 } 818 819 /* 820 * We've only added 2 FATSOv2 option descriptors 821 * and 1 descriptor for the linearized packet header. 822 * The outstanding work will be done in the same manner 823 * as for the usual non-TSO path 824 */ 825 } 826 827 for (; m_seg != NULL; m_seg = m_seg->next) { 828 efsys_dma_addr_t next_frag; 829 size_t seg_len; 830 831 seg_len = m_seg->data_len; 832 next_frag = rte_mbuf_data_iova(m_seg); 833 834 /* 835 * If we've started TSO transaction few steps earlier, 836 * we'll skip packet header using an offset in the 837 * current segment (which has been set to the 838 * first one containing payload) 839 */ 840 seg_len -= in_off; 841 next_frag += in_off; 842 in_off = 0; 843 844 do { 845 efsys_dma_addr_t frag_addr = next_frag; 846 size_t frag_len; 847 848 /* 849 * It is assumed here that there is no 850 * limitation on address boundary 851 * crossing by DMA descriptor. 852 */ 853 frag_len = MIN(seg_len, txq->dma_desc_size_max); 854 next_frag += frag_len; 855 seg_len -= frag_len; 856 pkt_len -= frag_len; 857 858 efx_tx_qdesc_dma_create(txq->common, 859 frag_addr, frag_len, 860 (pkt_len == 0), 861 pend++); 862 863 pkt_descs++; 864 } while (seg_len != 0); 865 } 866 867 added += pkt_descs; 868 869 fill_level += pkt_descs; 870 if (unlikely(fill_level > hard_max_fill)) { 871 /* 872 * Our estimation for maximum number of descriptors 873 * required to send a packet seems to be wrong. 874 * Try to reap (if we haven't yet). 875 */ 876 if (!reap_done) { 877 sfc_efx_tx_reap(txq); 878 reap_done = B_TRUE; 879 fill_level = added - txq->completed; 880 if (fill_level > hard_max_fill) { 881 pend -= pkt_descs; 882 break; 883 } 884 } else { 885 pend -= pkt_descs; 886 break; 887 } 888 } 889 890 /* Assign mbuf to the last used desc */ 891 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp; 892 } 893 894 if (likely(pkts_sent > 0)) { 895 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, 896 pend - &txq->pend_desc[0], 897 txq->completed, &txq->added); 898 SFC_ASSERT(rc == 0); 899 900 if (likely(pushed != txq->added)) 901 efx_tx_qpush(txq->common, txq->added, pushed); 902 } 903 904 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE 905 if (!reap_done) 906 sfc_efx_tx_reap(txq); 907 #endif 908 909 done: 910 return pkts_sent; 911 } 912 913 struct sfc_txq * 914 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq) 915 { 916 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 917 struct rte_eth_dev *eth_dev; 918 struct sfc_adapter *sa; 919 struct sfc_txq *txq; 920 921 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 922 eth_dev = &rte_eth_devices[dpq->port_id]; 923 924 sa = eth_dev->data->dev_private; 925 926 SFC_ASSERT(dpq->queue_id < sa->txq_count); 927 txq = sa->txq_info[dpq->queue_id].txq; 928 929 SFC_ASSERT(txq != NULL); 930 return txq; 931 } 932 933 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings; 934 static int 935 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc, 936 unsigned int *txq_entries, 937 unsigned int *evq_entries, 938 unsigned int *txq_max_fill_level) 939 { 940 *txq_entries = nb_tx_desc; 941 *evq_entries = nb_tx_desc; 942 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries); 943 return 0; 944 } 945 946 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate; 947 static int 948 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id, 949 const struct rte_pci_addr *pci_addr, 950 int socket_id, 951 const struct sfc_dp_tx_qcreate_info *info, 952 struct sfc_dp_txq **dp_txqp) 953 { 954 struct sfc_efx_txq *txq; 955 struct sfc_txq *ctrl_txq; 956 int rc; 957 958 rc = ENOMEM; 959 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq), 960 RTE_CACHE_LINE_SIZE, socket_id); 961 if (txq == NULL) 962 goto fail_txq_alloc; 963 964 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr); 965 966 rc = ENOMEM; 967 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc", 968 EFX_TXQ_LIMIT(info->txq_entries), 969 sizeof(*txq->pend_desc), 0, 970 socket_id); 971 if (txq->pend_desc == NULL) 972 goto fail_pend_desc_alloc; 973 974 rc = ENOMEM; 975 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring", 976 info->txq_entries, 977 sizeof(*txq->sw_ring), 978 RTE_CACHE_LINE_SIZE, socket_id); 979 if (txq->sw_ring == NULL) 980 goto fail_sw_ring_alloc; 981 982 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp); 983 if (ctrl_txq->evq->sa->tso) { 984 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring, 985 info->txq_entries, socket_id); 986 if (rc != 0) 987 goto fail_alloc_tsoh_objs; 988 } 989 990 txq->evq = ctrl_txq->evq; 991 txq->ptr_mask = info->txq_entries - 1; 992 txq->max_fill_level = info->max_fill_level; 993 txq->free_thresh = info->free_thresh; 994 txq->dma_desc_size_max = info->dma_desc_size_max; 995 996 *dp_txqp = &txq->dp; 997 return 0; 998 999 fail_alloc_tsoh_objs: 1000 rte_free(txq->sw_ring); 1001 1002 fail_sw_ring_alloc: 1003 rte_free(txq->pend_desc); 1004 1005 fail_pend_desc_alloc: 1006 rte_free(txq); 1007 1008 fail_txq_alloc: 1009 return rc; 1010 } 1011 1012 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy; 1013 static void 1014 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq) 1015 { 1016 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1017 1018 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1); 1019 rte_free(txq->sw_ring); 1020 rte_free(txq->pend_desc); 1021 rte_free(txq); 1022 } 1023 1024 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart; 1025 static int 1026 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq, 1027 __rte_unused unsigned int evq_read_ptr, 1028 unsigned int txq_desc_index) 1029 { 1030 /* libefx-based datapath is specific to libefx-based PMD */ 1031 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1032 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq); 1033 1034 txq->common = ctrl_txq->common; 1035 1036 txq->pending = txq->completed = txq->added = txq_desc_index; 1037 txq->hw_vlan_tci = 0; 1038 1039 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING); 1040 1041 return 0; 1042 } 1043 1044 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop; 1045 static void 1046 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq, 1047 __rte_unused unsigned int *evq_read_ptr) 1048 { 1049 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1050 1051 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING; 1052 } 1053 1054 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap; 1055 static void 1056 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq) 1057 { 1058 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1059 unsigned int txds; 1060 1061 sfc_efx_tx_reap(txq); 1062 1063 for (txds = 0; txds <= txq->ptr_mask; txds++) { 1064 if (txq->sw_ring[txds].mbuf != NULL) { 1065 rte_pktmbuf_free(txq->sw_ring[txds].mbuf); 1066 txq->sw_ring[txds].mbuf = NULL; 1067 } 1068 } 1069 1070 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED; 1071 } 1072 1073 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status; 1074 static int 1075 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset) 1076 { 1077 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1078 1079 if (unlikely(offset > txq->ptr_mask)) 1080 return -EINVAL; 1081 1082 if (unlikely(offset >= txq->max_fill_level)) 1083 return RTE_ETH_TX_DESC_UNAVAIL; 1084 1085 /* 1086 * Poll EvQ to derive up-to-date 'txq->pending' figure; 1087 * it is required for the queue to be running, but the 1088 * check is omitted because API design assumes that it 1089 * is the duty of the caller to satisfy all conditions 1090 */ 1091 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 1092 SFC_EFX_TXQ_FLAG_RUNNING); 1093 sfc_ev_qpoll(txq->evq); 1094 1095 /* 1096 * Ring tail is 'txq->pending', and although descriptors 1097 * between 'txq->completed' and 'txq->pending' are still 1098 * in use by the driver, they should be reported as DONE 1099 */ 1100 if (unlikely(offset < (txq->added - txq->pending))) 1101 return RTE_ETH_TX_DESC_FULL; 1102 1103 /* 1104 * There is no separate return value for unused descriptors; 1105 * the latter will be reported as DONE because genuine DONE 1106 * descriptors will be freed anyway in SW on the next burst 1107 */ 1108 return RTE_ETH_TX_DESC_DONE; 1109 } 1110 1111 struct sfc_dp_tx sfc_efx_tx = { 1112 .dp = { 1113 .name = SFC_KVARG_DATAPATH_EFX, 1114 .type = SFC_DP_TX, 1115 .hw_fw_caps = 0, 1116 }, 1117 .features = SFC_DP_TX_FEAT_VLAN_INSERT | 1118 SFC_DP_TX_FEAT_TSO | 1119 SFC_DP_TX_FEAT_MULTI_POOL | 1120 SFC_DP_TX_FEAT_REFCNT | 1121 SFC_DP_TX_FEAT_MULTI_SEG, 1122 .qsize_up_rings = sfc_efx_tx_qsize_up_rings, 1123 .qcreate = sfc_efx_tx_qcreate, 1124 .qdestroy = sfc_efx_tx_qdestroy, 1125 .qstart = sfc_efx_tx_qstart, 1126 .qstop = sfc_efx_tx_qstop, 1127 .qreap = sfc_efx_tx_qreap, 1128 .qdesc_status = sfc_efx_tx_qdesc_status, 1129 .pkt_burst = sfc_efx_xmit_pkts, 1130 }; 1131