1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include "sfc.h" 11 #include "sfc_debug.h" 12 #include "sfc_log.h" 13 #include "sfc_ev.h" 14 #include "sfc_tx.h" 15 #include "sfc_tweak.h" 16 #include "sfc_kvargs.h" 17 18 /* 19 * Maximum number of TX queue flush attempts in case of 20 * failure or flush timeout 21 */ 22 #define SFC_TX_QFLUSH_ATTEMPTS (3) 23 24 /* 25 * Time to wait between event queue polling attempts when waiting for TX 26 * queue flush done or flush failed events 27 */ 28 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1) 29 30 /* 31 * Maximum number of event queue polling attempts when waiting for TX queue 32 * flush done or flush failed events; it defines TX queue flush attempt timeout 33 * together with SFC_TX_QFLUSH_POLL_WAIT_MS 34 */ 35 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000) 36 37 struct sfc_txq_info * 38 sfc_txq_info_by_ethdev_qid(struct sfc_adapter_shared *sas, 39 sfc_ethdev_qid_t ethdev_qid) 40 { 41 sfc_sw_index_t sw_index; 42 43 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_txq_count); 44 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 45 46 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 47 return &sas->txq_info[sw_index]; 48 } 49 50 static uint64_t 51 sfc_tx_get_offload_mask(struct sfc_adapter *sa) 52 { 53 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 54 uint64_t no_caps = 0; 55 56 if (!encp->enc_hw_tx_insert_vlan_enabled) 57 no_caps |= DEV_TX_OFFLOAD_VLAN_INSERT; 58 59 if (!encp->enc_tunnel_encapsulations_supported) 60 no_caps |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 61 62 if (!sa->tso) 63 no_caps |= DEV_TX_OFFLOAD_TCP_TSO; 64 65 if (!sa->tso_encap || 66 (encp->enc_tunnel_encapsulations_supported & 67 (1u << EFX_TUNNEL_PROTOCOL_VXLAN)) == 0) 68 no_caps |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO; 69 70 if (!sa->tso_encap || 71 (encp->enc_tunnel_encapsulations_supported & 72 (1u << EFX_TUNNEL_PROTOCOL_GENEVE)) == 0) 73 no_caps |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO; 74 75 return ~no_caps; 76 } 77 78 uint64_t 79 sfc_tx_get_dev_offload_caps(struct sfc_adapter *sa) 80 { 81 return sa->priv.dp_tx->dev_offload_capa & sfc_tx_get_offload_mask(sa); 82 } 83 84 uint64_t 85 sfc_tx_get_queue_offload_caps(struct sfc_adapter *sa) 86 { 87 return sa->priv.dp_tx->queue_offload_capa & sfc_tx_get_offload_mask(sa); 88 } 89 90 static int 91 sfc_tx_qcheck_conf(struct sfc_adapter *sa, unsigned int txq_max_fill_level, 92 const struct rte_eth_txconf *tx_conf, 93 uint64_t offloads) 94 { 95 int rc = 0; 96 97 if (tx_conf->tx_rs_thresh != 0) { 98 sfc_err(sa, "RS bit in transmit descriptor is not supported"); 99 rc = EINVAL; 100 } 101 102 if (tx_conf->tx_free_thresh > txq_max_fill_level) { 103 sfc_err(sa, 104 "TxQ free threshold too large: %u vs maximum %u", 105 tx_conf->tx_free_thresh, txq_max_fill_level); 106 rc = EINVAL; 107 } 108 109 if (tx_conf->tx_thresh.pthresh != 0 || 110 tx_conf->tx_thresh.hthresh != 0 || 111 tx_conf->tx_thresh.wthresh != 0) { 112 sfc_warn(sa, 113 "prefetch/host/writeback thresholds are not supported"); 114 } 115 116 /* We either perform both TCP and UDP offload, or no offload at all */ 117 if (((offloads & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) != 118 ((offloads & DEV_TX_OFFLOAD_UDP_CKSUM) == 0)) { 119 sfc_err(sa, "TCP and UDP offloads can't be set independently"); 120 rc = EINVAL; 121 } 122 123 return rc; 124 } 125 126 void 127 sfc_tx_qflush_done(struct sfc_txq_info *txq_info) 128 { 129 txq_info->state |= SFC_TXQ_FLUSHED; 130 txq_info->state &= ~SFC_TXQ_FLUSHING; 131 } 132 133 int 134 sfc_tx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 135 uint16_t nb_tx_desc, unsigned int socket_id, 136 const struct rte_eth_txconf *tx_conf) 137 { 138 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 139 sfc_ethdev_qid_t ethdev_qid; 140 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 141 unsigned int txq_entries; 142 unsigned int evq_entries; 143 unsigned int txq_max_fill_level; 144 struct sfc_txq_info *txq_info; 145 struct sfc_evq *evq; 146 struct sfc_txq *txq; 147 int rc = 0; 148 struct sfc_dp_tx_qcreate_info info; 149 uint64_t offloads; 150 struct sfc_dp_tx_hw_limits hw_limits; 151 152 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 153 154 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 155 156 memset(&hw_limits, 0, sizeof(hw_limits)); 157 hw_limits.txq_max_entries = sa->txq_max_entries; 158 hw_limits.txq_min_entries = sa->txq_min_entries; 159 160 rc = sa->priv.dp_tx->qsize_up_rings(nb_tx_desc, &hw_limits, 161 &txq_entries, &evq_entries, 162 &txq_max_fill_level); 163 if (rc != 0) 164 goto fail_size_up_rings; 165 SFC_ASSERT(txq_entries >= sa->txq_min_entries); 166 SFC_ASSERT(txq_entries <= sa->txq_max_entries); 167 SFC_ASSERT(txq_entries >= nb_tx_desc); 168 SFC_ASSERT(txq_max_fill_level <= nb_tx_desc); 169 170 offloads = tx_conf->offloads; 171 /* Add device level Tx offloads if the queue is an ethdev Tx queue */ 172 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 173 offloads |= sa->eth_dev->data->dev_conf.txmode.offloads; 174 175 rc = sfc_tx_qcheck_conf(sa, txq_max_fill_level, tx_conf, offloads); 176 if (rc != 0) 177 goto fail_bad_conf; 178 179 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 180 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 181 182 txq_info->entries = txq_entries; 183 184 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_TX, sw_index, 185 evq_entries, socket_id, &evq); 186 if (rc != 0) 187 goto fail_ev_qinit; 188 189 txq = &sa->txq_ctrl[sw_index]; 190 txq->hw_index = sw_index; 191 txq->evq = evq; 192 txq_info->free_thresh = 193 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh : 194 SFC_TX_DEFAULT_FREE_THRESH; 195 txq_info->offloads = offloads; 196 197 rc = sfc_dma_alloc(sa, "txq", sw_index, 198 efx_txq_size(sa->nic, txq_info->entries), 199 socket_id, &txq->mem); 200 if (rc != 0) 201 goto fail_dma_alloc; 202 203 memset(&info, 0, sizeof(info)); 204 info.max_fill_level = txq_max_fill_level; 205 info.free_thresh = txq_info->free_thresh; 206 info.offloads = offloads; 207 info.txq_entries = txq_info->entries; 208 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max; 209 info.txq_hw_ring = txq->mem.esm_base; 210 info.evq_entries = evq_entries; 211 info.evq_hw_ring = evq->mem.esm_base; 212 info.hw_index = txq->hw_index; 213 info.mem_bar = sa->mem_bar.esb_base; 214 info.vi_window_shift = encp->enc_vi_window_shift; 215 info.tso_tcp_header_offset_limit = 216 encp->enc_tx_tso_tcp_header_offset_limit; 217 info.tso_max_nb_header_descs = 218 RTE_MIN(encp->enc_tx_tso_max_header_ndescs, 219 (uint32_t)UINT16_MAX); 220 info.tso_max_header_len = 221 RTE_MIN(encp->enc_tx_tso_max_header_length, 222 (uint32_t)UINT16_MAX); 223 info.tso_max_nb_payload_descs = 224 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs, 225 (uint32_t)UINT16_MAX); 226 info.tso_max_payload_len = encp->enc_tx_tso_max_payload_length; 227 info.tso_max_nb_outgoing_frames = encp->enc_tx_tso_max_nframes; 228 229 rc = sa->priv.dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index, 230 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 231 socket_id, &info, &txq_info->dp); 232 if (rc != 0) 233 goto fail_dp_tx_qinit; 234 235 evq->dp_txq = txq_info->dp; 236 237 txq_info->state = SFC_TXQ_INITIALIZED; 238 239 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0); 240 241 return 0; 242 243 fail_dp_tx_qinit: 244 sfc_dma_free(sa, &txq->mem); 245 246 fail_dma_alloc: 247 sfc_ev_qfini(evq); 248 249 fail_ev_qinit: 250 txq_info->entries = 0; 251 252 fail_bad_conf: 253 fail_size_up_rings: 254 sfc_log_init(sa, "failed (TxQ = %d (internal %u), rc = %d)", ethdev_qid, 255 sw_index, rc); 256 return rc; 257 } 258 259 void 260 sfc_tx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 261 { 262 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 263 sfc_ethdev_qid_t ethdev_qid; 264 struct sfc_txq_info *txq_info; 265 struct sfc_txq *txq; 266 267 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 268 269 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 270 271 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->txq_count); 272 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 273 sa->eth_dev->data->tx_queues[ethdev_qid] = NULL; 274 275 txq_info = &sfc_sa2shared(sa)->txq_info[sw_index]; 276 277 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 278 279 sa->priv.dp_tx->qdestroy(txq_info->dp); 280 txq_info->dp = NULL; 281 282 txq_info->state &= ~SFC_TXQ_INITIALIZED; 283 txq_info->entries = 0; 284 285 txq = &sa->txq_ctrl[sw_index]; 286 287 sfc_dma_free(sa, &txq->mem); 288 289 sfc_ev_qfini(txq->evq); 290 txq->evq = NULL; 291 } 292 293 int 294 sfc_tx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 295 { 296 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 297 sfc_ethdev_qid_t ethdev_qid; 298 299 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 300 301 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 302 303 return 0; 304 } 305 306 static int 307 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode) 308 { 309 int rc = 0; 310 311 switch (txmode->mq_mode) { 312 case ETH_MQ_TX_NONE: 313 break; 314 default: 315 sfc_err(sa, "Tx multi-queue mode %u not supported", 316 txmode->mq_mode); 317 rc = EINVAL; 318 } 319 320 /* 321 * These features are claimed to be i40e-specific, 322 * but it does make sense to double-check their absence 323 */ 324 if (txmode->hw_vlan_reject_tagged) { 325 sfc_err(sa, "Rejecting tagged packets not supported"); 326 rc = EINVAL; 327 } 328 329 if (txmode->hw_vlan_reject_untagged) { 330 sfc_err(sa, "Rejecting untagged packets not supported"); 331 rc = EINVAL; 332 } 333 334 if (txmode->hw_vlan_insert_pvid) { 335 sfc_err(sa, "Port-based VLAN insertion not supported"); 336 rc = EINVAL; 337 } 338 339 return rc; 340 } 341 342 /** 343 * Destroy excess queues that are no longer needed after reconfiguration 344 * or complete close. 345 */ 346 static void 347 sfc_tx_fini_queues(struct sfc_adapter *sa, unsigned int nb_tx_queues) 348 { 349 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 350 sfc_sw_index_t sw_index; 351 sfc_ethdev_qid_t ethdev_qid; 352 353 SFC_ASSERT(nb_tx_queues <= sas->ethdev_txq_count); 354 355 /* 356 * Finalize only ethdev queues since other ones are finalized only 357 * on device close and they may require additional deinitializaton. 358 */ 359 ethdev_qid = sas->ethdev_txq_count; 360 while (--ethdev_qid >= (int)nb_tx_queues) { 361 struct sfc_txq_info *txq_info; 362 363 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, ethdev_qid); 364 txq_info = sfc_txq_info_by_ethdev_qid(sas, ethdev_qid); 365 if (txq_info->state & SFC_TXQ_INITIALIZED) 366 sfc_tx_qfini(sa, sw_index); 367 } 368 369 sas->ethdev_txq_count = nb_tx_queues; 370 } 371 372 int 373 sfc_tx_configure(struct sfc_adapter *sa) 374 { 375 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 376 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 377 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 378 const unsigned int nb_tx_queues = sa->eth_dev->data->nb_tx_queues; 379 const unsigned int nb_rsvd_tx_queues = sfc_nb_txq_reserved(sas); 380 const unsigned int nb_txq_total = nb_tx_queues + nb_rsvd_tx_queues; 381 bool reconfigure; 382 int rc = 0; 383 384 sfc_log_init(sa, "nb_tx_queues=%u (old %u)", 385 nb_tx_queues, sas->ethdev_txq_count); 386 387 /* 388 * The datapath implementation assumes absence of boundary 389 * limits on Tx DMA descriptors. Addition of these checks on 390 * datapath would simply make the datapath slower. 391 */ 392 if (encp->enc_tx_dma_desc_boundary != 0) { 393 rc = ENOTSUP; 394 goto fail_tx_dma_desc_boundary; 395 } 396 397 rc = sfc_tx_check_mode(sa, &dev_conf->txmode); 398 if (rc != 0) 399 goto fail_check_mode; 400 401 if (nb_txq_total == sas->txq_count) 402 goto done; 403 404 if (sas->txq_info == NULL) { 405 reconfigure = false; 406 sas->txq_info = rte_calloc_socket("sfc-txqs", nb_txq_total, 407 sizeof(sas->txq_info[0]), 0, 408 sa->socket_id); 409 if (sas->txq_info == NULL) 410 goto fail_txqs_alloc; 411 412 /* 413 * Allocate primary process only TxQ control from heap 414 * since it should not be shared. 415 */ 416 rc = ENOMEM; 417 sa->txq_ctrl = calloc(nb_txq_total, sizeof(sa->txq_ctrl[0])); 418 if (sa->txq_ctrl == NULL) 419 goto fail_txqs_ctrl_alloc; 420 } else { 421 struct sfc_txq_info *new_txq_info; 422 struct sfc_txq *new_txq_ctrl; 423 424 reconfigure = true; 425 426 if (nb_tx_queues < sas->ethdev_txq_count) 427 sfc_tx_fini_queues(sa, nb_tx_queues); 428 429 new_txq_info = 430 rte_realloc(sas->txq_info, 431 nb_txq_total * sizeof(sas->txq_info[0]), 0); 432 if (new_txq_info == NULL && nb_txq_total > 0) 433 goto fail_txqs_realloc; 434 435 new_txq_ctrl = realloc(sa->txq_ctrl, 436 nb_txq_total * sizeof(sa->txq_ctrl[0])); 437 if (new_txq_ctrl == NULL && nb_txq_total > 0) 438 goto fail_txqs_ctrl_realloc; 439 440 sas->txq_info = new_txq_info; 441 sa->txq_ctrl = new_txq_ctrl; 442 if (nb_txq_total > sas->txq_count) { 443 memset(&sas->txq_info[sas->txq_count], 0, 444 (nb_txq_total - sas->txq_count) * 445 sizeof(sas->txq_info[0])); 446 memset(&sa->txq_ctrl[sas->txq_count], 0, 447 (nb_txq_total - sas->txq_count) * 448 sizeof(sa->txq_ctrl[0])); 449 } 450 } 451 452 while (sas->ethdev_txq_count < nb_tx_queues) { 453 sfc_sw_index_t sw_index; 454 455 sw_index = sfc_txq_sw_index_by_ethdev_tx_qid(sas, 456 sas->ethdev_txq_count); 457 rc = sfc_tx_qinit_info(sa, sw_index); 458 if (rc != 0) 459 goto fail_tx_qinit_info; 460 461 sas->ethdev_txq_count++; 462 } 463 464 sas->txq_count = sas->ethdev_txq_count + nb_rsvd_tx_queues; 465 466 if (!reconfigure) { 467 rc = sfc_repr_proxy_txq_init(sa); 468 if (rc != 0) 469 goto fail_repr_proxy_txq_init; 470 } 471 472 done: 473 return 0; 474 475 fail_repr_proxy_txq_init: 476 fail_tx_qinit_info: 477 fail_txqs_ctrl_realloc: 478 fail_txqs_realloc: 479 fail_txqs_ctrl_alloc: 480 fail_txqs_alloc: 481 sfc_tx_close(sa); 482 483 fail_check_mode: 484 fail_tx_dma_desc_boundary: 485 sfc_log_init(sa, "failed (rc = %d)", rc); 486 return rc; 487 } 488 489 void 490 sfc_tx_close(struct sfc_adapter *sa) 491 { 492 sfc_tx_fini_queues(sa, 0); 493 sfc_repr_proxy_txq_fini(sa); 494 495 free(sa->txq_ctrl); 496 sa->txq_ctrl = NULL; 497 498 rte_free(sfc_sa2shared(sa)->txq_info); 499 sfc_sa2shared(sa)->txq_info = NULL; 500 } 501 502 int 503 sfc_tx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 504 { 505 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 506 sfc_ethdev_qid_t ethdev_qid; 507 uint64_t offloads_supported = sfc_tx_get_dev_offload_caps(sa) | 508 sfc_tx_get_queue_offload_caps(sa); 509 struct sfc_txq_info *txq_info; 510 struct sfc_txq *txq; 511 struct sfc_evq *evq; 512 uint16_t flags = 0; 513 unsigned int desc_index; 514 int rc = 0; 515 516 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 517 518 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 519 520 SFC_ASSERT(sw_index < sas->txq_count); 521 txq_info = &sas->txq_info[sw_index]; 522 523 SFC_ASSERT(txq_info->state == SFC_TXQ_INITIALIZED); 524 525 txq = &sa->txq_ctrl[sw_index]; 526 evq = txq->evq; 527 528 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_txq_sw_index(sa, sw_index)); 529 if (rc != 0) 530 goto fail_ev_qstart; 531 532 if (txq_info->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 533 flags |= EFX_TXQ_CKSUM_IPV4; 534 535 if (txq_info->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) 536 flags |= EFX_TXQ_CKSUM_INNER_IPV4; 537 538 if ((txq_info->offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 539 (txq_info->offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 540 flags |= EFX_TXQ_CKSUM_TCPUDP; 541 542 if (offloads_supported & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) 543 flags |= EFX_TXQ_CKSUM_INNER_TCPUDP; 544 } 545 546 if (txq_info->offloads & (DEV_TX_OFFLOAD_TCP_TSO | 547 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 548 DEV_TX_OFFLOAD_GENEVE_TNL_TSO)) 549 flags |= EFX_TXQ_FATSOV2; 550 551 rc = efx_tx_qcreate(sa->nic, txq->hw_index, 0, &txq->mem, 552 txq_info->entries, 0 /* not used on EF10 */, 553 flags, evq->common, 554 &txq->common, &desc_index); 555 if (rc != 0) { 556 if (sa->tso && (rc == ENOSPC)) 557 sfc_err(sa, "ran out of TSO contexts"); 558 559 goto fail_tx_qcreate; 560 } 561 562 efx_tx_qenable(txq->common); 563 564 txq_info->state |= SFC_TXQ_STARTED; 565 566 rc = sa->priv.dp_tx->qstart(txq_info->dp, evq->read_ptr, desc_index); 567 if (rc != 0) 568 goto fail_dp_qstart; 569 570 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) { 571 struct rte_eth_dev_data *dev_data; 572 573 /* 574 * It sems to be used by DPDK for debug purposes only 575 * ('rte_ether'). 576 */ 577 dev_data = sa->eth_dev->data; 578 dev_data->tx_queue_state[ethdev_qid] = 579 RTE_ETH_QUEUE_STATE_STARTED; 580 } 581 582 return 0; 583 584 fail_dp_qstart: 585 txq_info->state = SFC_TXQ_INITIALIZED; 586 efx_tx_qdestroy(txq->common); 587 588 fail_tx_qcreate: 589 sfc_ev_qstop(evq); 590 591 fail_ev_qstart: 592 return rc; 593 } 594 595 void 596 sfc_tx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 597 { 598 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 599 sfc_ethdev_qid_t ethdev_qid; 600 struct sfc_txq_info *txq_info; 601 struct sfc_txq *txq; 602 unsigned int retry_count; 603 unsigned int wait_count; 604 int rc; 605 606 ethdev_qid = sfc_ethdev_tx_qid_by_txq_sw_index(sas, sw_index); 607 608 sfc_log_init(sa, "TxQ = %d (internal %u)", ethdev_qid, sw_index); 609 610 SFC_ASSERT(sw_index < sas->txq_count); 611 txq_info = &sas->txq_info[sw_index]; 612 613 if (txq_info->state == SFC_TXQ_INITIALIZED) 614 return; 615 616 SFC_ASSERT(txq_info->state & SFC_TXQ_STARTED); 617 618 txq = &sa->txq_ctrl[sw_index]; 619 sa->priv.dp_tx->qstop(txq_info->dp, &txq->evq->read_ptr); 620 621 /* 622 * Retry TX queue flushing in case of flush failed or 623 * timeout; in the worst case it can delay for 6 seconds 624 */ 625 for (retry_count = 0; 626 ((txq_info->state & SFC_TXQ_FLUSHED) == 0) && 627 (retry_count < SFC_TX_QFLUSH_ATTEMPTS); 628 ++retry_count) { 629 rc = efx_tx_qflush(txq->common); 630 if (rc != 0) { 631 txq_info->state |= (rc == EALREADY) ? 632 SFC_TXQ_FLUSHED : SFC_TXQ_FLUSH_FAILED; 633 break; 634 } 635 636 /* 637 * Wait for TX queue flush done or flush failed event at least 638 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more 639 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied 640 * by SFC_TX_QFLUSH_POLL_ATTEMPTS) 641 */ 642 wait_count = 0; 643 do { 644 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS); 645 sfc_ev_qpoll(txq->evq); 646 } while ((txq_info->state & SFC_TXQ_FLUSHING) && 647 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS); 648 649 if (txq_info->state & SFC_TXQ_FLUSHING) 650 sfc_err(sa, "TxQ %d (internal %u) flush timed out", 651 ethdev_qid, sw_index); 652 653 if (txq_info->state & SFC_TXQ_FLUSHED) 654 sfc_notice(sa, "TxQ %d (internal %u) flushed", 655 ethdev_qid, sw_index); 656 } 657 658 sa->priv.dp_tx->qreap(txq_info->dp); 659 660 txq_info->state = SFC_TXQ_INITIALIZED; 661 662 efx_tx_qdestroy(txq->common); 663 664 sfc_ev_qstop(txq->evq); 665 666 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) { 667 struct rte_eth_dev_data *dev_data; 668 669 /* 670 * It seems to be used by DPDK for debug purposes only 671 * ('rte_ether') 672 */ 673 dev_data = sa->eth_dev->data; 674 dev_data->tx_queue_state[ethdev_qid] = 675 RTE_ETH_QUEUE_STATE_STOPPED; 676 } 677 } 678 679 int 680 sfc_tx_start(struct sfc_adapter *sa) 681 { 682 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 683 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 684 sfc_sw_index_t sw_index; 685 int rc = 0; 686 687 sfc_log_init(sa, "txq_count = %u (internal %u)", 688 sas->ethdev_txq_count, sas->txq_count); 689 690 if (sa->tso) { 691 if (!encp->enc_fw_assisted_tso_v2_enabled && 692 !encp->enc_tso_v3_enabled) { 693 sfc_warn(sa, "TSO support was unable to be restored"); 694 sa->tso = B_FALSE; 695 sa->tso_encap = B_FALSE; 696 } 697 } 698 699 if (sa->tso_encap && !encp->enc_fw_assisted_tso_v2_encap_enabled && 700 !encp->enc_tso_v3_enabled) { 701 sfc_warn(sa, "Encapsulated TSO support was unable to be restored"); 702 sa->tso_encap = B_FALSE; 703 } 704 705 rc = efx_tx_init(sa->nic); 706 if (rc != 0) 707 goto fail_efx_tx_init; 708 709 for (sw_index = 0; sw_index < sas->txq_count; ++sw_index) { 710 if (sas->txq_info[sw_index].state == SFC_TXQ_INITIALIZED && 711 (!(sas->txq_info[sw_index].deferred_start) || 712 sas->txq_info[sw_index].deferred_started)) { 713 rc = sfc_tx_qstart(sa, sw_index); 714 if (rc != 0) 715 goto fail_tx_qstart; 716 } 717 } 718 719 return 0; 720 721 fail_tx_qstart: 722 while (sw_index-- > 0) 723 sfc_tx_qstop(sa, sw_index); 724 725 efx_tx_fini(sa->nic); 726 727 fail_efx_tx_init: 728 sfc_log_init(sa, "failed (rc = %d)", rc); 729 return rc; 730 } 731 732 void 733 sfc_tx_stop(struct sfc_adapter *sa) 734 { 735 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 736 sfc_sw_index_t sw_index; 737 738 sfc_log_init(sa, "txq_count = %u (internal %u)", 739 sas->ethdev_txq_count, sas->txq_count); 740 741 sw_index = sas->txq_count; 742 while (sw_index-- > 0) { 743 if (sas->txq_info[sw_index].state & SFC_TXQ_STARTED) 744 sfc_tx_qstop(sa, sw_index); 745 } 746 747 efx_tx_fini(sa->nic); 748 } 749 750 static void 751 sfc_efx_tx_reap(struct sfc_efx_txq *txq) 752 { 753 unsigned int completed; 754 755 sfc_ev_qpoll(txq->evq); 756 757 for (completed = txq->completed; 758 completed != txq->pending; completed++) { 759 struct sfc_efx_tx_sw_desc *txd; 760 761 txd = &txq->sw_ring[completed & txq->ptr_mask]; 762 763 if (txd->mbuf != NULL) { 764 rte_pktmbuf_free(txd->mbuf); 765 txd->mbuf = NULL; 766 } 767 } 768 769 txq->completed = completed; 770 } 771 772 /* 773 * The function is used to insert or update VLAN tag; 774 * the firmware has state of the firmware tag to insert per TxQ 775 * (controlled by option descriptors), hence, if the tag of the 776 * packet to be sent is different from one remembered by the firmware, 777 * the function will update it 778 */ 779 static unsigned int 780 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m, 781 efx_desc_t **pend) 782 { 783 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ? 784 m->vlan_tci : 0); 785 786 if (this_tag == txq->hw_vlan_tci) 787 return 0; 788 789 /* 790 * The expression inside SFC_ASSERT() is not desired to be checked in 791 * a non-debug build because it might be too expensive on the data path 792 */ 793 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled); 794 795 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag), 796 *pend); 797 (*pend)++; 798 txq->hw_vlan_tci = this_tag; 799 800 return 1; 801 } 802 803 static uint16_t 804 sfc_efx_prepare_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 805 uint16_t nb_pkts) 806 { 807 struct sfc_dp_txq *dp_txq = tx_queue; 808 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 809 const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->evq->sa->nic); 810 uint16_t i; 811 812 for (i = 0; i < nb_pkts; i++) { 813 int ret; 814 815 /* 816 * EFX Tx datapath may require extra VLAN descriptor if VLAN 817 * insertion offload is requested regardless the offload 818 * requested/supported. 819 */ 820 ret = sfc_dp_tx_prepare_pkt(tx_pkts[i], 0, SFC_TSOH_STD_LEN, 821 encp->enc_tx_tso_tcp_header_offset_limit, 822 txq->max_fill_level, EFX_TX_FATSOV2_OPT_NDESCS, 823 1); 824 if (unlikely(ret != 0)) { 825 rte_errno = ret; 826 break; 827 } 828 } 829 830 return i; 831 } 832 833 static uint16_t 834 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) 835 { 836 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue; 837 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 838 unsigned int added = txq->added; 839 unsigned int pushed = added; 840 unsigned int pkts_sent = 0; 841 efx_desc_t *pend = &txq->pend_desc[0]; 842 const unsigned int hard_max_fill = txq->max_fill_level; 843 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh; 844 unsigned int fill_level = added - txq->completed; 845 boolean_t reap_done; 846 int rc __rte_unused; 847 struct rte_mbuf **pktp; 848 849 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0)) 850 goto done; 851 852 /* 853 * If insufficient space for a single packet is present, 854 * we should reap; otherwise, we shouldn't do that all the time 855 * to avoid latency increase 856 */ 857 reap_done = (fill_level > soft_max_fill); 858 859 if (reap_done) { 860 sfc_efx_tx_reap(txq); 861 /* 862 * Recalculate fill level since 'txq->completed' 863 * might have changed on reap 864 */ 865 fill_level = added - txq->completed; 866 } 867 868 for (pkts_sent = 0, pktp = &tx_pkts[0]; 869 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill); 870 pkts_sent++, pktp++) { 871 uint16_t hw_vlan_tci_prev = txq->hw_vlan_tci; 872 struct rte_mbuf *m_seg = *pktp; 873 size_t pkt_len = m_seg->pkt_len; 874 unsigned int pkt_descs = 0; 875 size_t in_off = 0; 876 877 /* 878 * Here VLAN TCI is expected to be zero in case if no 879 * DEV_TX_OFFLOAD_VLAN_INSERT capability is advertised; 880 * if the calling app ignores the absence of 881 * DEV_TX_OFFLOAD_VLAN_INSERT and pushes VLAN TCI, then 882 * TX_ERROR will occur 883 */ 884 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend); 885 886 if (m_seg->ol_flags & PKT_TX_TCP_SEG) { 887 /* 888 * We expect correct 'pkt->l[2, 3, 4]_len' values 889 * to be set correctly by the caller 890 */ 891 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend, 892 &pkt_descs, &pkt_len) != 0) { 893 /* We may have reached this place if packet 894 * header linearization is needed but the 895 * header length is greater than 896 * SFC_TSOH_STD_LEN 897 * 898 * We will deceive RTE saying that we have sent 899 * the packet, but we will actually drop it. 900 * Hence, we should revert 'pend' to the 901 * previous state (in case we have added 902 * VLAN descriptor) and start processing 903 * another one packet. But the original 904 * mbuf shouldn't be orphaned 905 */ 906 pend -= pkt_descs; 907 txq->hw_vlan_tci = hw_vlan_tci_prev; 908 909 rte_pktmbuf_free(*pktp); 910 911 continue; 912 } 913 914 /* 915 * We've only added 2 FATSOv2 option descriptors 916 * and 1 descriptor for the linearized packet header. 917 * The outstanding work will be done in the same manner 918 * as for the usual non-TSO path 919 */ 920 } 921 922 for (; m_seg != NULL; m_seg = m_seg->next) { 923 efsys_dma_addr_t next_frag; 924 size_t seg_len; 925 926 seg_len = m_seg->data_len; 927 next_frag = rte_mbuf_data_iova(m_seg); 928 929 /* 930 * If we've started TSO transaction few steps earlier, 931 * we'll skip packet header using an offset in the 932 * current segment (which has been set to the 933 * first one containing payload) 934 */ 935 seg_len -= in_off; 936 next_frag += in_off; 937 in_off = 0; 938 939 do { 940 efsys_dma_addr_t frag_addr = next_frag; 941 size_t frag_len; 942 943 /* 944 * It is assumed here that there is no 945 * limitation on address boundary 946 * crossing by DMA descriptor. 947 */ 948 frag_len = MIN(seg_len, txq->dma_desc_size_max); 949 next_frag += frag_len; 950 seg_len -= frag_len; 951 pkt_len -= frag_len; 952 953 efx_tx_qdesc_dma_create(txq->common, 954 frag_addr, frag_len, 955 (pkt_len == 0), 956 pend++); 957 958 pkt_descs++; 959 } while (seg_len != 0); 960 } 961 962 added += pkt_descs; 963 964 fill_level += pkt_descs; 965 if (unlikely(fill_level > hard_max_fill)) { 966 /* 967 * Our estimation for maximum number of descriptors 968 * required to send a packet seems to be wrong. 969 * Try to reap (if we haven't yet). 970 */ 971 if (!reap_done) { 972 sfc_efx_tx_reap(txq); 973 reap_done = B_TRUE; 974 fill_level = added - txq->completed; 975 if (fill_level > hard_max_fill) { 976 pend -= pkt_descs; 977 txq->hw_vlan_tci = hw_vlan_tci_prev; 978 break; 979 } 980 } else { 981 pend -= pkt_descs; 982 txq->hw_vlan_tci = hw_vlan_tci_prev; 983 break; 984 } 985 } 986 987 /* Assign mbuf to the last used desc */ 988 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp; 989 } 990 991 if (likely(pkts_sent > 0)) { 992 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc, 993 pend - &txq->pend_desc[0], 994 txq->completed, &txq->added); 995 SFC_ASSERT(rc == 0); 996 997 if (likely(pushed != txq->added)) { 998 efx_tx_qpush(txq->common, txq->added, pushed); 999 txq->dp.dpq.tx_dbells++; 1000 } 1001 } 1002 1003 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE 1004 if (!reap_done) 1005 sfc_efx_tx_reap(txq); 1006 #endif 1007 1008 done: 1009 return pkts_sent; 1010 } 1011 1012 const struct sfc_dp_tx * 1013 sfc_dp_tx_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1014 { 1015 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1016 struct rte_eth_dev *eth_dev; 1017 struct sfc_adapter_priv *sap; 1018 1019 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1020 eth_dev = &rte_eth_devices[dpq->port_id]; 1021 1022 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 1023 1024 return sap->dp_tx; 1025 } 1026 1027 struct sfc_txq_info * 1028 sfc_txq_info_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1029 { 1030 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1031 struct rte_eth_dev *eth_dev; 1032 struct sfc_adapter_shared *sas; 1033 1034 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1035 eth_dev = &rte_eth_devices[dpq->port_id]; 1036 1037 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 1038 1039 SFC_ASSERT(dpq->queue_id < sas->txq_count); 1040 return &sas->txq_info[dpq->queue_id]; 1041 } 1042 1043 struct sfc_txq * 1044 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq) 1045 { 1046 const struct sfc_dp_queue *dpq = &dp_txq->dpq; 1047 struct rte_eth_dev *eth_dev; 1048 struct sfc_adapter *sa; 1049 1050 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 1051 eth_dev = &rte_eth_devices[dpq->port_id]; 1052 1053 sa = sfc_adapter_by_eth_dev(eth_dev); 1054 1055 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->txq_count); 1056 return &sa->txq_ctrl[dpq->queue_id]; 1057 } 1058 1059 static sfc_dp_tx_qsize_up_rings_t sfc_efx_tx_qsize_up_rings; 1060 static int 1061 sfc_efx_tx_qsize_up_rings(uint16_t nb_tx_desc, 1062 __rte_unused struct sfc_dp_tx_hw_limits *limits, 1063 unsigned int *txq_entries, 1064 unsigned int *evq_entries, 1065 unsigned int *txq_max_fill_level) 1066 { 1067 *txq_entries = nb_tx_desc; 1068 *evq_entries = nb_tx_desc; 1069 *txq_max_fill_level = EFX_TXQ_LIMIT(*txq_entries); 1070 return 0; 1071 } 1072 1073 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate; 1074 static int 1075 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id, 1076 const struct rte_pci_addr *pci_addr, 1077 int socket_id, 1078 const struct sfc_dp_tx_qcreate_info *info, 1079 struct sfc_dp_txq **dp_txqp) 1080 { 1081 struct sfc_efx_txq *txq; 1082 struct sfc_txq *ctrl_txq; 1083 int rc; 1084 1085 rc = ENOMEM; 1086 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq), 1087 RTE_CACHE_LINE_SIZE, socket_id); 1088 if (txq == NULL) 1089 goto fail_txq_alloc; 1090 1091 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr); 1092 1093 rc = ENOMEM; 1094 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc", 1095 EFX_TXQ_LIMIT(info->txq_entries), 1096 sizeof(*txq->pend_desc), 0, 1097 socket_id); 1098 if (txq->pend_desc == NULL) 1099 goto fail_pend_desc_alloc; 1100 1101 rc = ENOMEM; 1102 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring", 1103 info->txq_entries, 1104 sizeof(*txq->sw_ring), 1105 RTE_CACHE_LINE_SIZE, socket_id); 1106 if (txq->sw_ring == NULL) 1107 goto fail_sw_ring_alloc; 1108 1109 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp); 1110 if (ctrl_txq->evq->sa->tso) { 1111 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring, 1112 info->txq_entries, socket_id); 1113 if (rc != 0) 1114 goto fail_alloc_tsoh_objs; 1115 } 1116 1117 txq->evq = ctrl_txq->evq; 1118 txq->ptr_mask = info->txq_entries - 1; 1119 txq->max_fill_level = info->max_fill_level; 1120 txq->free_thresh = info->free_thresh; 1121 txq->dma_desc_size_max = info->dma_desc_size_max; 1122 1123 *dp_txqp = &txq->dp; 1124 return 0; 1125 1126 fail_alloc_tsoh_objs: 1127 rte_free(txq->sw_ring); 1128 1129 fail_sw_ring_alloc: 1130 rte_free(txq->pend_desc); 1131 1132 fail_pend_desc_alloc: 1133 rte_free(txq); 1134 1135 fail_txq_alloc: 1136 return rc; 1137 } 1138 1139 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy; 1140 static void 1141 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq) 1142 { 1143 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1144 1145 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1); 1146 rte_free(txq->sw_ring); 1147 rte_free(txq->pend_desc); 1148 rte_free(txq); 1149 } 1150 1151 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart; 1152 static int 1153 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq, 1154 __rte_unused unsigned int evq_read_ptr, 1155 unsigned int txq_desc_index) 1156 { 1157 /* libefx-based datapath is specific to libefx-based PMD */ 1158 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1159 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq); 1160 1161 txq->common = ctrl_txq->common; 1162 1163 txq->pending = txq->completed = txq->added = txq_desc_index; 1164 txq->hw_vlan_tci = 0; 1165 1166 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING); 1167 1168 return 0; 1169 } 1170 1171 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop; 1172 static void 1173 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq, 1174 __rte_unused unsigned int *evq_read_ptr) 1175 { 1176 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1177 1178 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING; 1179 } 1180 1181 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap; 1182 static void 1183 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq) 1184 { 1185 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1186 unsigned int txds; 1187 1188 sfc_efx_tx_reap(txq); 1189 1190 for (txds = 0; txds <= txq->ptr_mask; txds++) { 1191 if (txq->sw_ring[txds].mbuf != NULL) { 1192 rte_pktmbuf_free(txq->sw_ring[txds].mbuf); 1193 txq->sw_ring[txds].mbuf = NULL; 1194 } 1195 } 1196 1197 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED; 1198 } 1199 1200 static sfc_dp_tx_qdesc_status_t sfc_efx_tx_qdesc_status; 1201 static int 1202 sfc_efx_tx_qdesc_status(struct sfc_dp_txq *dp_txq, uint16_t offset) 1203 { 1204 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq); 1205 1206 if (unlikely(offset > txq->ptr_mask)) 1207 return -EINVAL; 1208 1209 if (unlikely(offset >= txq->max_fill_level)) 1210 return RTE_ETH_TX_DESC_UNAVAIL; 1211 1212 /* 1213 * Poll EvQ to derive up-to-date 'txq->pending' figure; 1214 * it is required for the queue to be running, but the 1215 * check is omitted because API design assumes that it 1216 * is the duty of the caller to satisfy all conditions 1217 */ 1218 SFC_ASSERT((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 1219 SFC_EFX_TXQ_FLAG_RUNNING); 1220 sfc_ev_qpoll(txq->evq); 1221 1222 /* 1223 * Ring tail is 'txq->pending', and although descriptors 1224 * between 'txq->completed' and 'txq->pending' are still 1225 * in use by the driver, they should be reported as DONE 1226 */ 1227 if (unlikely(offset < (txq->added - txq->pending))) 1228 return RTE_ETH_TX_DESC_FULL; 1229 1230 /* 1231 * There is no separate return value for unused descriptors; 1232 * the latter will be reported as DONE because genuine DONE 1233 * descriptors will be freed anyway in SW on the next burst 1234 */ 1235 return RTE_ETH_TX_DESC_DONE; 1236 } 1237 1238 struct sfc_dp_tx sfc_efx_tx = { 1239 .dp = { 1240 .name = SFC_KVARG_DATAPATH_EFX, 1241 .type = SFC_DP_TX, 1242 .hw_fw_caps = SFC_DP_HW_FW_CAP_TX_EFX, 1243 }, 1244 .features = 0, 1245 .dev_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 1246 DEV_TX_OFFLOAD_MULTI_SEGS, 1247 .queue_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM | 1248 DEV_TX_OFFLOAD_UDP_CKSUM | 1249 DEV_TX_OFFLOAD_TCP_CKSUM | 1250 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 1251 DEV_TX_OFFLOAD_TCP_TSO, 1252 .qsize_up_rings = sfc_efx_tx_qsize_up_rings, 1253 .qcreate = sfc_efx_tx_qcreate, 1254 .qdestroy = sfc_efx_tx_qdestroy, 1255 .qstart = sfc_efx_tx_qstart, 1256 .qstop = sfc_efx_tx_qstop, 1257 .qreap = sfc_efx_tx_qreap, 1258 .qdesc_status = sfc_efx_tx_qdesc_status, 1259 .pkt_prepare = sfc_efx_prepare_pkts, 1260 .pkt_burst = sfc_efx_xmit_pkts, 1261 }; 1262