1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_flow_tunnel.h" 17 #include "sfc_log.h" 18 #include "sfc_ev.h" 19 #include "sfc_rx.h" 20 #include "sfc_mae_counter.h" 21 #include "sfc_kvargs.h" 22 #include "sfc_tweak.h" 23 24 /* 25 * Maximum number of Rx queue flush attempt in the case of failure or 26 * flush timeout 27 */ 28 #define SFC_RX_QFLUSH_ATTEMPTS (3) 29 30 /* 31 * Time to wait between event queue polling attempts when waiting for Rx 32 * queue flush done or failed events. 33 */ 34 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 35 36 /* 37 * Maximum number of event queue polling attempts when waiting for Rx queue 38 * flush done or failed events. It defines Rx queue flush attempt timeout 39 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 40 */ 41 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 42 43 void 44 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info) 45 { 46 rxq_info->state |= SFC_RXQ_FLUSHED; 47 rxq_info->state &= ~SFC_RXQ_FLUSHING; 48 } 49 50 void 51 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info) 52 { 53 rxq_info->state |= SFC_RXQ_FLUSH_FAILED; 54 rxq_info->state &= ~SFC_RXQ_FLUSHING; 55 } 56 57 /* This returns the running counter, which is not bounded by ring size */ 58 unsigned int 59 sfc_rx_get_pushed(struct sfc_adapter *sa, struct sfc_dp_rxq *dp_rxq) 60 { 61 SFC_ASSERT(sa->priv.dp_rx->get_pushed != NULL); 62 63 return sa->priv.dp_rx->get_pushed(dp_rxq); 64 } 65 66 static int 67 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq) 68 { 69 int rc = 0; 70 71 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) { 72 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr); 73 if (rc == 0) 74 rxq->evq->read_ptr_primed = rxq->evq->read_ptr; 75 } 76 return rc; 77 } 78 79 static void 80 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 81 { 82 unsigned int free_space; 83 unsigned int bulks; 84 void *objs[SFC_RX_REFILL_BULK]; 85 efsys_dma_addr_t addr[RTE_DIM(objs)]; 86 unsigned int added = rxq->added; 87 unsigned int id; 88 unsigned int i; 89 struct sfc_efx_rx_sw_desc *rxd; 90 struct rte_mbuf *m; 91 uint16_t port_id = rxq->dp.dpq.port_id; 92 93 free_space = rxq->max_fill_level - (added - rxq->completed); 94 95 if (free_space < rxq->refill_threshold) 96 return; 97 98 bulks = free_space / RTE_DIM(objs); 99 /* refill_threshold guarantees that bulks is positive */ 100 SFC_ASSERT(bulks > 0); 101 102 id = added & rxq->ptr_mask; 103 do { 104 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 105 RTE_DIM(objs)) < 0)) { 106 /* 107 * It is hardly a safe way to increment counter 108 * from different contexts, but all PMDs do it. 109 */ 110 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 111 RTE_DIM(objs); 112 /* Return if we have posted nothing yet */ 113 if (added == rxq->added) 114 return; 115 /* Push posted */ 116 break; 117 } 118 119 for (i = 0; i < RTE_DIM(objs); 120 ++i, id = (id + 1) & rxq->ptr_mask) { 121 m = objs[i]; 122 123 __rte_mbuf_raw_sanity_check(m); 124 125 rxd = &rxq->sw_desc[id]; 126 rxd->mbuf = m; 127 128 m->data_off = RTE_PKTMBUF_HEADROOM; 129 m->port = port_id; 130 131 addr[i] = rte_pktmbuf_iova(m); 132 } 133 134 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 135 RTE_DIM(objs), rxq->completed, added); 136 added += RTE_DIM(objs); 137 } while (--bulks > 0); 138 139 SFC_ASSERT(added != rxq->added); 140 rxq->added = added; 141 efx_rx_qpush(rxq->common, added, &rxq->pushed); 142 rxq->dp.dpq.dbells++; 143 } 144 145 static uint64_t 146 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 147 { 148 uint64_t mbuf_flags = 0; 149 150 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 151 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 152 mbuf_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 153 break; 154 case EFX_PKT_IPV4: 155 mbuf_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; 156 break; 157 default: 158 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN != 0); 159 SFC_ASSERT((mbuf_flags & RTE_MBUF_F_RX_IP_CKSUM_MASK) == 160 RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN); 161 break; 162 } 163 164 switch ((desc_flags & 165 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 166 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 167 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 168 mbuf_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 169 break; 170 case EFX_PKT_TCP: 171 case EFX_PKT_UDP: 172 mbuf_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; 173 break; 174 default: 175 RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN != 0); 176 SFC_ASSERT((mbuf_flags & RTE_MBUF_F_RX_L4_CKSUM_MASK) == 177 RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN); 178 break; 179 } 180 181 return mbuf_flags; 182 } 183 184 static uint32_t 185 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 186 { 187 return RTE_PTYPE_L2_ETHER | 188 ((desc_flags & EFX_PKT_IPV4) ? 189 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 190 ((desc_flags & EFX_PKT_IPV6) ? 191 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 192 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 193 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 194 } 195 196 static const uint32_t * 197 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps, 198 size_t *no_of_elements) 199 { 200 static const uint32_t ptypes[] = { 201 RTE_PTYPE_L2_ETHER, 202 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 203 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 204 RTE_PTYPE_L4_TCP, 205 RTE_PTYPE_L4_UDP, 206 }; 207 208 *no_of_elements = RTE_DIM(ptypes); 209 return ptypes; 210 } 211 212 static void 213 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 214 struct rte_mbuf *m) 215 { 216 uint8_t *mbuf_data; 217 218 219 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 220 return; 221 222 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 223 224 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 225 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 226 EFX_RX_HASHALG_TOEPLITZ, 227 mbuf_data); 228 229 m->ol_flags |= RTE_MBUF_F_RX_RSS_HASH; 230 } 231 } 232 233 static uint16_t 234 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 235 { 236 struct sfc_dp_rxq *dp_rxq = rx_queue; 237 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 238 unsigned int completed; 239 unsigned int prefix_size = rxq->prefix_size; 240 unsigned int done_pkts = 0; 241 boolean_t discard_next = B_FALSE; 242 struct rte_mbuf *scatter_pkt = NULL; 243 244 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 245 return 0; 246 247 sfc_ev_qpoll(rxq->evq); 248 249 completed = rxq->completed; 250 while (completed != rxq->pending && done_pkts < nb_pkts) { 251 unsigned int id; 252 struct sfc_efx_rx_sw_desc *rxd; 253 struct rte_mbuf *m; 254 unsigned int seg_len; 255 unsigned int desc_flags; 256 257 id = completed++ & rxq->ptr_mask; 258 rxd = &rxq->sw_desc[id]; 259 m = rxd->mbuf; 260 desc_flags = rxd->flags; 261 262 if (discard_next) 263 goto discard; 264 265 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 266 goto discard; 267 268 if (desc_flags & EFX_PKT_PREFIX_LEN) { 269 uint16_t tmp_size; 270 int rc __rte_unused; 271 272 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 273 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 274 SFC_ASSERT(rc == 0); 275 seg_len = tmp_size; 276 } else { 277 seg_len = rxd->size - prefix_size; 278 } 279 280 rte_pktmbuf_data_len(m) = seg_len; 281 rte_pktmbuf_pkt_len(m) = seg_len; 282 283 if (scatter_pkt != NULL) { 284 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 285 rte_pktmbuf_free(scatter_pkt); 286 goto discard; 287 } 288 /* The packet to deliver */ 289 m = scatter_pkt; 290 } 291 292 if (desc_flags & EFX_PKT_CONT) { 293 /* The packet is scattered, more fragments to come */ 294 scatter_pkt = m; 295 /* Further fragments have no prefix */ 296 prefix_size = 0; 297 continue; 298 } 299 300 /* Scattered packet is done */ 301 scatter_pkt = NULL; 302 /* The first fragment of the packet has prefix */ 303 prefix_size = rxq->prefix_size; 304 305 m->ol_flags = 306 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 307 m->packet_type = 308 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 309 310 /* 311 * Extract RSS hash from the packet prefix and 312 * set the corresponding field (if needed and possible) 313 */ 314 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 315 316 m->data_off += prefix_size; 317 318 *rx_pkts++ = m; 319 done_pkts++; 320 continue; 321 322 discard: 323 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 324 rte_mbuf_raw_free(m); 325 rxd->mbuf = NULL; 326 } 327 328 /* pending is only moved when entire packet is received */ 329 SFC_ASSERT(scatter_pkt == NULL); 330 331 rxq->completed = completed; 332 333 sfc_efx_rx_qrefill(rxq); 334 335 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) 336 sfc_efx_rx_qprime(rxq); 337 338 return done_pkts; 339 } 340 341 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 342 static unsigned int 343 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 344 { 345 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 346 347 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 348 return 0; 349 350 sfc_ev_qpoll(rxq->evq); 351 352 return rxq->pending - rxq->completed; 353 } 354 355 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 356 static int 357 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 358 { 359 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 360 361 if (unlikely(offset > rxq->ptr_mask)) 362 return -EINVAL; 363 364 /* 365 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 366 * it is required for the queue to be running, but the 367 * check is omitted because API design assumes that it 368 * is the duty of the caller to satisfy all conditions 369 */ 370 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 371 SFC_EFX_RXQ_FLAG_RUNNING); 372 sfc_ev_qpoll(rxq->evq); 373 374 /* 375 * There is a handful of reserved entries in the ring, 376 * but an explicit check whether the offset points to 377 * a reserved entry is neglected since the two checks 378 * below rely on the figures which take the HW limits 379 * into account and thus if an entry is reserved, the 380 * checks will fail and UNAVAIL code will be returned 381 */ 382 383 if (offset < (rxq->pending - rxq->completed)) 384 return RTE_ETH_RX_DESC_DONE; 385 386 if (offset < (rxq->added - rxq->completed)) 387 return RTE_ETH_RX_DESC_AVAIL; 388 389 return RTE_ETH_RX_DESC_UNAVAIL; 390 } 391 392 boolean_t 393 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size, 394 boolean_t rx_scatter_enabled, uint32_t rx_scatter_max, 395 const char **error) 396 { 397 uint32_t effective_rx_scatter_max; 398 uint32_t rx_scatter_bufs; 399 400 effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1; 401 rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size); 402 403 if (rx_scatter_bufs > effective_rx_scatter_max) { 404 if (rx_scatter_enabled) 405 *error = "Possible number of Rx scatter buffers exceeds maximum number"; 406 else 407 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small"; 408 return B_FALSE; 409 } 410 411 return B_TRUE; 412 } 413 414 /** Get Rx datapath ops by the datapath RxQ handle */ 415 const struct sfc_dp_rx * 416 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 417 { 418 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 419 struct rte_eth_dev *eth_dev; 420 struct sfc_adapter_priv *sap; 421 422 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 423 eth_dev = &rte_eth_devices[dpq->port_id]; 424 425 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 426 427 return sap->dp_rx; 428 } 429 430 struct sfc_rxq_info * 431 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 432 { 433 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 434 struct rte_eth_dev *eth_dev; 435 struct sfc_adapter_shared *sas; 436 437 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 438 eth_dev = &rte_eth_devices[dpq->port_id]; 439 440 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 441 442 SFC_ASSERT(dpq->queue_id < sas->rxq_count); 443 return &sas->rxq_info[dpq->queue_id]; 444 } 445 446 struct sfc_rxq * 447 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 448 { 449 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 450 struct rte_eth_dev *eth_dev; 451 struct sfc_adapter *sa; 452 453 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 454 eth_dev = &rte_eth_devices[dpq->port_id]; 455 456 sa = sfc_adapter_by_eth_dev(eth_dev); 457 458 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count); 459 return &sa->rxq_ctrl[dpq->queue_id]; 460 } 461 462 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 463 static int 464 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 465 __rte_unused struct sfc_dp_rx_hw_limits *limits, 466 __rte_unused struct rte_mempool *mb_pool, 467 unsigned int *rxq_entries, 468 unsigned int *evq_entries, 469 unsigned int *rxq_max_fill_level) 470 { 471 *rxq_entries = nb_rx_desc; 472 *evq_entries = nb_rx_desc; 473 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 474 return 0; 475 } 476 477 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 478 static int 479 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 480 const struct rte_pci_addr *pci_addr, int socket_id, 481 const struct sfc_dp_rx_qcreate_info *info, 482 struct sfc_dp_rxq **dp_rxqp) 483 { 484 struct sfc_efx_rxq *rxq; 485 int rc; 486 487 rc = ENOTSUP; 488 if (info->nic_dma_info->nb_regions > 0) 489 goto fail_nic_dma; 490 491 rc = ENOMEM; 492 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 493 RTE_CACHE_LINE_SIZE, socket_id); 494 if (rxq == NULL) 495 goto fail_rxq_alloc; 496 497 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 498 499 rc = ENOMEM; 500 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 501 info->rxq_entries, 502 sizeof(*rxq->sw_desc), 503 RTE_CACHE_LINE_SIZE, socket_id); 504 if (rxq->sw_desc == NULL) 505 goto fail_desc_alloc; 506 507 /* efx datapath is bound to efx control path */ 508 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 509 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 510 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 511 rxq->ptr_mask = info->rxq_entries - 1; 512 rxq->batch_max = info->batch_max; 513 rxq->prefix_size = info->prefix_size; 514 rxq->max_fill_level = info->max_fill_level; 515 rxq->refill_threshold = info->refill_threshold; 516 rxq->buf_size = info->buf_size; 517 rxq->refill_mb_pool = info->refill_mb_pool; 518 519 *dp_rxqp = &rxq->dp; 520 return 0; 521 522 fail_desc_alloc: 523 rte_free(rxq); 524 525 fail_rxq_alloc: 526 fail_nic_dma: 527 return rc; 528 } 529 530 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 531 static void 532 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 533 { 534 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 535 536 rte_free(rxq->sw_desc); 537 rte_free(rxq); 538 } 539 540 541 /* Use qstop and qstart functions in the case of qstart failure */ 542 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 543 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 544 545 546 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 547 static int 548 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 549 __rte_unused unsigned int evq_read_ptr, 550 const efx_rx_prefix_layout_t *pinfo) 551 { 552 /* libefx-based datapath is specific to libefx-based PMD */ 553 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 554 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 555 int rc; 556 557 /* 558 * libefx API is used to extract information from Rx prefix and 559 * it guarantees consistency. Just do length check to ensure 560 * that we reserved space in Rx buffers correctly. 561 */ 562 if (rxq->prefix_size != pinfo->erpl_length) 563 return ENOTSUP; 564 565 rxq->common = crxq->common; 566 567 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 568 569 sfc_efx_rx_qrefill(rxq); 570 571 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 572 573 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) { 574 rc = sfc_efx_rx_qprime(rxq); 575 if (rc != 0) 576 goto fail_rx_qprime; 577 } 578 579 return 0; 580 581 fail_rx_qprime: 582 sfc_efx_rx_qstop(dp_rxq, NULL); 583 sfc_efx_rx_qpurge(dp_rxq); 584 return rc; 585 } 586 587 static void 588 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 589 __rte_unused unsigned int *evq_read_ptr) 590 { 591 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 592 593 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 594 595 /* libefx-based datapath is bound to libefx-based PMD and uses 596 * event queue structure directly. So, there is no necessity to 597 * return EvQ read pointer. 598 */ 599 } 600 601 static void 602 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 603 { 604 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 605 unsigned int i; 606 struct sfc_efx_rx_sw_desc *rxd; 607 608 for (i = rxq->completed; i != rxq->added; ++i) { 609 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 610 rte_mbuf_raw_free(rxd->mbuf); 611 rxd->mbuf = NULL; 612 /* Packed stream relies on 0 in inactive SW desc. 613 * Rx queue stop is not performance critical, so 614 * there is no harm to do it always. 615 */ 616 rxd->flags = 0; 617 rxd->size = 0; 618 } 619 620 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 621 } 622 623 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable; 624 static int 625 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq) 626 { 627 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 628 int rc = 0; 629 630 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN; 631 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) { 632 rc = sfc_efx_rx_qprime(rxq); 633 if (rc != 0) 634 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 635 } 636 return rc; 637 } 638 639 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable; 640 static int 641 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq) 642 { 643 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 644 645 /* Cannot disarm, just disable rearm */ 646 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 647 return 0; 648 } 649 650 struct sfc_dp_rx sfc_efx_rx = { 651 .dp = { 652 .name = SFC_KVARG_DATAPATH_EFX, 653 .type = SFC_DP_RX, 654 .hw_fw_caps = SFC_DP_HW_FW_CAP_RX_EFX, 655 }, 656 .features = SFC_DP_RX_FEAT_INTR, 657 .dev_offload_capa = RTE_ETH_RX_OFFLOAD_CHECKSUM | 658 RTE_ETH_RX_OFFLOAD_RSS_HASH | 659 RTE_ETH_RX_OFFLOAD_KEEP_CRC, 660 .queue_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER, 661 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 662 .qcreate = sfc_efx_rx_qcreate, 663 .qdestroy = sfc_efx_rx_qdestroy, 664 .qstart = sfc_efx_rx_qstart, 665 .qstop = sfc_efx_rx_qstop, 666 .qpurge = sfc_efx_rx_qpurge, 667 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 668 .qdesc_npending = sfc_efx_rx_qdesc_npending, 669 .qdesc_status = sfc_efx_rx_qdesc_status, 670 .intr_enable = sfc_efx_rx_intr_enable, 671 .intr_disable = sfc_efx_rx_intr_disable, 672 .pkt_burst = sfc_efx_recv_pkts, 673 }; 674 675 static void 676 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 677 { 678 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 679 sfc_ethdev_qid_t ethdev_qid; 680 struct sfc_rxq_info *rxq_info; 681 struct sfc_rxq *rxq; 682 unsigned int retry_count; 683 unsigned int wait_count; 684 int rc; 685 686 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 687 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 688 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 689 690 rxq = &sa->rxq_ctrl[sw_index]; 691 692 /* 693 * Retry Rx queue flushing in the case of flush failed or 694 * timeout. In the worst case it can delay for 6 seconds. 695 */ 696 for (retry_count = 0; 697 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) && 698 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 699 ++retry_count) { 700 rc = efx_rx_qflush(rxq->common); 701 if (rc != 0) { 702 rxq_info->state |= (rc == EALREADY) ? 703 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 704 break; 705 } 706 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED; 707 rxq_info->state |= SFC_RXQ_FLUSHING; 708 709 /* 710 * Wait for Rx queue flush done or failed event at least 711 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 712 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 713 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 714 */ 715 wait_count = 0; 716 do { 717 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 718 sfc_ev_qpoll(rxq->evq); 719 } while ((rxq_info->state & SFC_RXQ_FLUSHING) && 720 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 721 722 if (rxq_info->state & SFC_RXQ_FLUSHING) 723 sfc_err(sa, "RxQ %d (internal %u) flush timed out", 724 ethdev_qid, sw_index); 725 726 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED) 727 sfc_err(sa, "RxQ %d (internal %u) flush failed", 728 ethdev_qid, sw_index); 729 730 if (rxq_info->state & SFC_RXQ_FLUSHED) 731 sfc_notice(sa, "RxQ %d (internal %u) flushed", 732 ethdev_qid, sw_index); 733 } 734 735 sa->priv.dp_rx->qpurge(rxq_info->dp); 736 } 737 738 static int 739 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 740 { 741 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 742 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 743 struct sfc_port *port = &sa->port; 744 int rc; 745 746 /* 747 * If promiscuous or all-multicast mode has been requested, setting 748 * filter for the default Rx queue might fail, in particular, while 749 * running over PCI function which is not a member of corresponding 750 * privilege groups; if this occurs, few iterations will be made to 751 * repeat this step without promiscuous and all-multicast flags set 752 */ 753 retry: 754 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 755 if (rc == 0) 756 return 0; 757 else if (rc != EOPNOTSUPP) 758 return rc; 759 760 if (port->promisc) { 761 sfc_warn(sa, "promiscuous mode has been requested, " 762 "but the HW rejects it"); 763 sfc_warn(sa, "promiscuous mode will be disabled"); 764 765 port->promisc = B_FALSE; 766 sa->eth_dev->data->promiscuous = 0; 767 rc = sfc_set_rx_mode_unchecked(sa); 768 if (rc != 0) 769 return rc; 770 771 goto retry; 772 } 773 774 if (port->allmulti) { 775 sfc_warn(sa, "all-multicast mode has been requested, " 776 "but the HW rejects it"); 777 sfc_warn(sa, "all-multicast mode will be disabled"); 778 779 port->allmulti = B_FALSE; 780 sa->eth_dev->data->all_multicast = 0; 781 rc = sfc_set_rx_mode_unchecked(sa); 782 if (rc != 0) 783 return rc; 784 785 goto retry; 786 } 787 788 return rc; 789 } 790 791 int 792 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 793 { 794 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 795 sfc_ethdev_qid_t ethdev_qid; 796 struct sfc_rxq_info *rxq_info; 797 struct sfc_rxq *rxq; 798 struct sfc_evq *evq; 799 efx_rx_prefix_layout_t pinfo; 800 int rc; 801 802 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 803 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 804 805 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index); 806 807 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 808 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 809 810 rxq = &sa->rxq_ctrl[sw_index]; 811 evq = rxq->evq; 812 813 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index)); 814 if (rc != 0) 815 goto fail_ev_qstart; 816 817 switch (rxq_info->type) { 818 case EFX_RXQ_TYPE_DEFAULT: 819 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 820 rxq->buf_size, 821 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 822 rxq_info->type_flags, evq->common, &rxq->common); 823 break; 824 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 825 struct rte_mempool *mp = rxq_info->refill_mb_pool; 826 struct rte_mempool_info mp_info; 827 828 rc = rte_mempool_ops_get_info(mp, &mp_info); 829 if (rc != 0) { 830 /* Positive errno is used in the driver */ 831 rc = -rc; 832 goto fail_mp_get_info; 833 } 834 if (mp_info.contig_block_size <= 0) { 835 rc = EINVAL; 836 goto fail_bad_contig_block_size; 837 } 838 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 839 mp_info.contig_block_size, rxq->buf_size, 840 mp->header_size + mp->elt_size + mp->trailer_size, 841 sa->rxd_wait_timeout_ns, 842 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 843 evq->common, &rxq->common); 844 break; 845 } 846 default: 847 rc = ENOTSUP; 848 } 849 if (rc != 0) 850 goto fail_rx_qcreate; 851 852 rc = efx_rx_prefix_get_layout(rxq->common, &pinfo); 853 if (rc != 0) 854 goto fail_prefix_get_layout; 855 856 efx_rx_qenable(rxq->common); 857 858 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo); 859 if (rc != 0) 860 goto fail_dp_qstart; 861 862 rxq_info->state |= SFC_RXQ_STARTED; 863 864 if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) { 865 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 866 if (rc != 0) 867 goto fail_mac_filter_default_rxq_set; 868 } 869 870 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 871 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 872 sa->eth_dev->data->rx_queue_state[ethdev_qid] = 873 RTE_ETH_QUEUE_STATE_STARTED; 874 875 return 0; 876 877 fail_mac_filter_default_rxq_set: 878 sfc_rx_qflush(sa, sw_index); 879 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 880 rxq_info->state = SFC_RXQ_INITIALIZED; 881 882 fail_dp_qstart: 883 efx_rx_qdestroy(rxq->common); 884 885 fail_prefix_get_layout: 886 fail_rx_qcreate: 887 fail_bad_contig_block_size: 888 fail_mp_get_info: 889 sfc_ev_qstop(evq); 890 891 fail_ev_qstart: 892 return rc; 893 } 894 895 void 896 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 897 { 898 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 899 sfc_ethdev_qid_t ethdev_qid; 900 struct sfc_rxq_info *rxq_info; 901 struct sfc_rxq *rxq; 902 903 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 904 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 905 906 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index); 907 908 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 909 910 if (rxq_info->state == SFC_RXQ_INITIALIZED) 911 return; 912 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 913 914 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 915 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 916 sa->eth_dev->data->rx_queue_state[ethdev_qid] = 917 RTE_ETH_QUEUE_STATE_STOPPED; 918 919 rxq = &sa->rxq_ctrl[sw_index]; 920 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 921 922 if (ethdev_qid == 0) 923 efx_mac_filter_default_rxq_clear(sa->nic); 924 925 sfc_rx_qflush(sa, sw_index); 926 927 rxq_info->state = SFC_RXQ_INITIALIZED; 928 929 efx_rx_qdestroy(rxq->common); 930 931 sfc_ev_qstop(rxq->evq); 932 } 933 934 static uint64_t 935 sfc_rx_get_offload_mask(struct sfc_adapter *sa) 936 { 937 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 938 uint64_t no_caps = 0; 939 940 if (encp->enc_tunnel_encapsulations_supported == 0) 941 no_caps |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; 942 943 if (encp->enc_rx_include_fcs_supported == 0) 944 no_caps |= RTE_ETH_RX_OFFLOAD_KEEP_CRC; 945 946 if (encp->enc_rx_vlan_stripping_supported == 0) 947 no_caps |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 948 949 return ~no_caps; 950 } 951 952 uint64_t 953 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 954 { 955 uint64_t caps = sa->priv.dp_rx->dev_offload_capa; 956 957 return caps & sfc_rx_get_offload_mask(sa); 958 } 959 960 uint64_t 961 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 962 { 963 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa); 964 } 965 966 static int 967 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 968 const struct rte_eth_rxconf *rx_conf, 969 __rte_unused uint64_t offloads) 970 { 971 int rc = 0; 972 973 if (rx_conf->rx_thresh.pthresh != 0 || 974 rx_conf->rx_thresh.hthresh != 0 || 975 rx_conf->rx_thresh.wthresh != 0) { 976 sfc_warn(sa, 977 "RxQ prefetch/host/writeback thresholds are not supported"); 978 } 979 980 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 981 sfc_err(sa, 982 "RxQ free threshold too large: %u vs maximum %u", 983 rx_conf->rx_free_thresh, rxq_max_fill_level); 984 rc = EINVAL; 985 } 986 987 if (rx_conf->rx_drop_en == 0) { 988 sfc_err(sa, "RxQ drop disable is not supported"); 989 rc = EINVAL; 990 } 991 992 return rc; 993 } 994 995 static unsigned int 996 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 997 { 998 uint32_t data_off; 999 uint32_t order; 1000 1001 /* The mbuf object itself is always cache line aligned */ 1002 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 1003 1004 /* Data offset from mbuf object start */ 1005 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 1006 RTE_PKTMBUF_HEADROOM; 1007 1008 order = MIN(order, rte_bsf32(data_off)); 1009 1010 return 1u << order; 1011 } 1012 1013 static uint16_t 1014 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 1015 { 1016 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1017 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 1018 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 1019 uint16_t buf_size; 1020 unsigned int buf_aligned; 1021 unsigned int start_alignment; 1022 unsigned int end_padding_alignment; 1023 1024 /* Below it is assumed that both alignments are power of 2 */ 1025 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 1026 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 1027 1028 /* 1029 * mbuf is always cache line aligned, double-check 1030 * that it meets rx buffer start alignment requirements. 1031 */ 1032 1033 /* Start from mbuf pool data room size */ 1034 buf_size = rte_pktmbuf_data_room_size(mb_pool); 1035 1036 /* Remove headroom */ 1037 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 1038 sfc_err(sa, 1039 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 1040 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 1041 return 0; 1042 } 1043 buf_size -= RTE_PKTMBUF_HEADROOM; 1044 1045 /* Calculate guaranteed data start alignment */ 1046 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 1047 1048 /* Reserve space for start alignment */ 1049 if (buf_aligned < nic_align_start) { 1050 start_alignment = nic_align_start - buf_aligned; 1051 if (buf_size <= start_alignment) { 1052 sfc_err(sa, 1053 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 1054 mb_pool->name, 1055 rte_pktmbuf_data_room_size(mb_pool), 1056 RTE_PKTMBUF_HEADROOM, start_alignment); 1057 return 0; 1058 } 1059 buf_aligned = nic_align_start; 1060 buf_size -= start_alignment; 1061 } else { 1062 start_alignment = 0; 1063 } 1064 1065 /* Make sure that end padding does not write beyond the buffer */ 1066 if (buf_aligned < nic_align_end) { 1067 /* 1068 * Estimate space which can be lost. If guaranteed buffer 1069 * size is odd, lost space is (nic_align_end - 1). More 1070 * accurate formula is below. 1071 */ 1072 end_padding_alignment = nic_align_end - 1073 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 1074 if (buf_size <= end_padding_alignment) { 1075 sfc_err(sa, 1076 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 1077 mb_pool->name, 1078 rte_pktmbuf_data_room_size(mb_pool), 1079 RTE_PKTMBUF_HEADROOM, start_alignment, 1080 end_padding_alignment); 1081 return 0; 1082 } 1083 buf_size -= end_padding_alignment; 1084 } else { 1085 /* 1086 * Start is aligned the same or better than end, 1087 * just align length. 1088 */ 1089 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end); 1090 } 1091 1092 /* 1093 * Buffer length field of a Rx descriptor may not be wide 1094 * enough to store a 16-bit data count taken from an mbuf. 1095 */ 1096 return MIN(buf_size, encp->enc_rx_dma_desc_size_max); 1097 } 1098 1099 int 1100 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 1101 uint16_t nb_rx_desc, unsigned int socket_id, 1102 const struct rte_eth_rxconf *rx_conf, 1103 struct rte_mempool *mb_pool) 1104 { 1105 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1106 sfc_ethdev_qid_t ethdev_qid; 1107 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1108 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1109 int rc; 1110 unsigned int rxq_entries; 1111 unsigned int evq_entries; 1112 unsigned int rxq_max_fill_level; 1113 uint64_t offloads; 1114 uint16_t buf_size; 1115 struct sfc_rxq_info *rxq_info; 1116 struct sfc_evq *evq; 1117 struct sfc_rxq *rxq; 1118 struct sfc_dp_rx_qcreate_info info; 1119 struct sfc_dp_rx_hw_limits hw_limits; 1120 struct sfc_port *port = &sa->port; 1121 uint16_t rx_free_thresh; 1122 const char *error; 1123 1124 memset(&hw_limits, 0, sizeof(hw_limits)); 1125 hw_limits.rxq_max_entries = sa->rxq_max_entries; 1126 hw_limits.rxq_min_entries = sa->rxq_min_entries; 1127 hw_limits.evq_max_entries = sa->evq_max_entries; 1128 hw_limits.evq_min_entries = sa->evq_min_entries; 1129 1130 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool, 1131 &rxq_entries, &evq_entries, 1132 &rxq_max_fill_level); 1133 if (rc != 0) 1134 goto fail_size_up_rings; 1135 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries); 1136 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries); 1137 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 1138 1139 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 1140 1141 offloads = rx_conf->offloads; 1142 /* Add device level Rx offloads if the queue is an ethdev Rx queue */ 1143 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 1144 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads; 1145 1146 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 1147 if (rc != 0) 1148 goto fail_bad_conf; 1149 1150 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 1151 if (buf_size == 0) { 1152 sfc_err(sa, 1153 "RxQ %d (internal %u) mbuf pool object size is too small", 1154 ethdev_qid, sw_index); 1155 rc = EINVAL; 1156 goto fail_bad_conf; 1157 } 1158 1159 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size, 1160 encp->enc_rx_prefix_size, 1161 (offloads & RTE_ETH_RX_OFFLOAD_SCATTER), 1162 encp->enc_rx_scatter_max, 1163 &error)) { 1164 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s", 1165 ethdev_qid, sw_index, error); 1166 sfc_err(sa, 1167 "RxQ %d (internal %u) calculated Rx buffer size is %u vs " 1168 "PDU size %u plus Rx prefix %u bytes", 1169 ethdev_qid, sw_index, buf_size, 1170 (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size); 1171 rc = EINVAL; 1172 goto fail_bad_conf; 1173 } 1174 1175 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1176 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1177 1178 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1179 rxq_info->entries = rxq_entries; 1180 1181 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1182 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1183 else 1184 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1185 1186 rxq_info->type_flags |= 1187 (offloads & RTE_ETH_RX_OFFLOAD_SCATTER) ? 1188 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1189 1190 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1191 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) & 1192 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0) 1193 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1194 1195 if (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH) 1196 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH; 1197 1198 if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_FLAG) != 0) 1199 rxq_info->type_flags |= EFX_RXQ_FLAG_USER_FLAG; 1200 1201 if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_MARK) != 0 || 1202 sfc_ft_is_active(sa)) 1203 rxq_info->type_flags |= EFX_RXQ_FLAG_USER_MARK; 1204 1205 if (port->vlan_strip) 1206 rxq_info->type_flags |= EFX_RXQ_FLAG_VLAN_STRIPPED_TCI; 1207 1208 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1209 evq_entries, socket_id, &evq); 1210 if (rc != 0) 1211 goto fail_ev_qinit; 1212 1213 rxq = &sa->rxq_ctrl[sw_index]; 1214 rxq->evq = evq; 1215 rxq->hw_index = sw_index; 1216 /* 1217 * If Rx refill threshold is specified (its value is non zero) in 1218 * Rx configuration, use specified value. Otherwise use 1/8 of 1219 * the Rx descriptors number as the default. It allows to keep 1220 * Rx ring full-enough and does not refill too aggressive if 1221 * packet rate is high. 1222 * 1223 * Since PMD refills in bulks waiting for full bulk may be 1224 * refilled (basically round down), it is better to round up 1225 * here to mitigate it a bit. 1226 */ 1227 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ? 1228 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8); 1229 /* Rx refill threshold cannot be smaller than refill bulk */ 1230 rxq_info->refill_threshold = 1231 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK); 1232 rxq_info->refill_mb_pool = mb_pool; 1233 1234 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 && 1235 (offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH)) 1236 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH; 1237 else 1238 rxq_info->rxq_flags = 0; 1239 1240 if (rxq_info->type_flags & EFX_RXQ_FLAG_INGRESS_MPORT) 1241 rxq_info->rxq_flags |= SFC_RXQ_FLAG_INGRESS_MPORT; 1242 1243 if (rxq_info->type_flags & EFX_RXQ_FLAG_VLAN_STRIPPED_TCI) 1244 rxq_info->rxq_flags |= SFC_RXQ_FLAG_VLAN_STRIPPED_TCI; 1245 1246 rxq->buf_size = buf_size; 1247 1248 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_NIC_DMA_ADDR_RX_RING, 1249 efx_rxq_size(sa->nic, rxq_info->entries), 1250 socket_id, &rxq->mem); 1251 if (rc != 0) 1252 goto fail_dma_alloc; 1253 1254 memset(&info, 0, sizeof(info)); 1255 info.refill_mb_pool = rxq_info->refill_mb_pool; 1256 info.max_fill_level = rxq_max_fill_level; 1257 info.refill_threshold = rxq_info->refill_threshold; 1258 info.buf_size = buf_size; 1259 info.batch_max = encp->enc_rx_batch_max; 1260 info.prefix_size = encp->enc_rx_prefix_size; 1261 1262 if (sfc_ft_is_active(sa)) 1263 info.user_mark_mask = SFC_FT_USER_MARK_MASK; 1264 else 1265 info.user_mark_mask = UINT32_MAX; 1266 1267 info.flags = rxq_info->rxq_flags; 1268 info.rxq_entries = rxq_info->entries; 1269 info.rxq_hw_ring = rxq->mem.esm_base; 1270 info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index); 1271 info.evq_entries = evq_entries; 1272 info.evq_hw_ring = evq->mem.esm_base; 1273 info.hw_index = rxq->hw_index; 1274 info.mem_bar = sa->mem_bar.esb_base; 1275 info.vi_window_shift = encp->enc_vi_window_shift; 1276 info.fcw_offset = sa->fcw_offset; 1277 1278 info.nic_dma_info = &sas->nic_dma_info; 1279 1280 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1281 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1282 socket_id, &info, &rxq_info->dp); 1283 if (rc != 0) 1284 goto fail_dp_rx_qcreate; 1285 1286 evq->dp_rxq = rxq_info->dp; 1287 1288 rxq_info->state = SFC_RXQ_INITIALIZED; 1289 1290 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1291 1292 return 0; 1293 1294 fail_dp_rx_qcreate: 1295 sfc_dma_free(sa, &rxq->mem); 1296 1297 fail_dma_alloc: 1298 sfc_ev_qfini(evq); 1299 1300 fail_ev_qinit: 1301 rxq_info->entries = 0; 1302 1303 fail_bad_conf: 1304 fail_size_up_rings: 1305 sfc_log_init(sa, "failed %d", rc); 1306 return rc; 1307 } 1308 1309 void 1310 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 1311 { 1312 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1313 sfc_ethdev_qid_t ethdev_qid; 1314 struct sfc_rxq_info *rxq_info; 1315 struct sfc_rxq *rxq; 1316 1317 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1318 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 1319 1320 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 1321 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL; 1322 1323 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1324 1325 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 1326 1327 sa->priv.dp_rx->qdestroy(rxq_info->dp); 1328 rxq_info->dp = NULL; 1329 1330 rxq_info->state &= ~SFC_RXQ_INITIALIZED; 1331 rxq_info->entries = 0; 1332 1333 rxq = &sa->rxq_ctrl[sw_index]; 1334 1335 sfc_dma_free(sa, &rxq->mem); 1336 1337 sfc_ev_qfini(rxq->evq); 1338 rxq->evq = NULL; 1339 } 1340 1341 /* 1342 * Mapping between RTE RSS hash functions and their EFX counterparts. 1343 */ 1344 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1345 { RTE_ETH_RSS_NONFRAG_IPV4_TCP, 1346 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1347 { RTE_ETH_RSS_NONFRAG_IPV4_UDP, 1348 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1349 { RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_IPV6_TCP_EX, 1350 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1351 { RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_IPV6_UDP_EX, 1352 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1353 { RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 1354 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1355 EFX_RX_HASH(IPV4, 2TUPLE) }, 1356 { RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | RTE_ETH_RSS_NONFRAG_IPV6_OTHER | 1357 RTE_ETH_RSS_IPV6_EX, 1358 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1359 EFX_RX_HASH(IPV6, 2TUPLE) } 1360 }; 1361 1362 static efx_rx_hash_type_t 1363 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1364 unsigned int *hash_type_flags_supported, 1365 unsigned int nb_hash_type_flags_supported) 1366 { 1367 efx_rx_hash_type_t hash_type_masked = 0; 1368 unsigned int i, j; 1369 1370 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1371 unsigned int class_tuple_lbn[] = { 1372 EFX_RX_CLASS_IPV4_TCP_LBN, 1373 EFX_RX_CLASS_IPV4_UDP_LBN, 1374 EFX_RX_CLASS_IPV4_LBN, 1375 EFX_RX_CLASS_IPV6_TCP_LBN, 1376 EFX_RX_CLASS_IPV6_UDP_LBN, 1377 EFX_RX_CLASS_IPV6_LBN 1378 }; 1379 1380 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1381 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1382 unsigned int flag; 1383 1384 tuple_mask <<= class_tuple_lbn[j]; 1385 flag = hash_type & tuple_mask; 1386 1387 if (flag == hash_type_flags_supported[i]) 1388 hash_type_masked |= flag; 1389 } 1390 } 1391 1392 return hash_type_masked; 1393 } 1394 1395 int 1396 sfc_rx_hash_init(struct sfc_adapter *sa) 1397 { 1398 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1399 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1400 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1401 efx_rx_hash_alg_t alg; 1402 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1403 unsigned int nb_flags_supp; 1404 struct sfc_rss_hf_rte_to_efx *hf_map; 1405 struct sfc_rss_hf_rte_to_efx *entry; 1406 efx_rx_hash_type_t efx_hash_types; 1407 unsigned int i; 1408 int rc; 1409 1410 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1411 alg = EFX_RX_HASHALG_TOEPLITZ; 1412 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1413 alg = EFX_RX_HASHALG_PACKED_STREAM; 1414 else 1415 return EINVAL; 1416 1417 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1418 RTE_DIM(flags_supp), &nb_flags_supp); 1419 if (rc != 0) 1420 return rc; 1421 1422 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1423 RTE_DIM(sfc_rss_hf_map), 1424 sizeof(*hf_map), 0, sa->socket_id); 1425 if (hf_map == NULL) 1426 return ENOMEM; 1427 1428 entry = hf_map; 1429 efx_hash_types = 0; 1430 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1431 efx_rx_hash_type_t ht; 1432 1433 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1434 flags_supp, nb_flags_supp); 1435 if (ht != 0) { 1436 entry->rte = sfc_rss_hf_map[i].rte; 1437 entry->efx = ht; 1438 efx_hash_types |= ht; 1439 ++entry; 1440 } 1441 } 1442 1443 rss->hash_alg = alg; 1444 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1445 rss->hf_map = hf_map; 1446 rss->hash_types = efx_hash_types; 1447 1448 return 0; 1449 } 1450 1451 void 1452 sfc_rx_hash_fini(struct sfc_adapter *sa) 1453 { 1454 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1455 1456 rte_free(rss->hf_map); 1457 } 1458 1459 int 1460 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1461 efx_rx_hash_type_t *efx) 1462 { 1463 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1464 efx_rx_hash_type_t hash_types = 0; 1465 unsigned int i; 1466 1467 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1468 uint64_t rte_mask = rss->hf_map[i].rte; 1469 1470 if ((rte & rte_mask) != 0) { 1471 rte &= ~rte_mask; 1472 hash_types |= rss->hf_map[i].efx; 1473 } 1474 } 1475 1476 if (rte != 0) { 1477 sfc_err(sa, "unsupported hash functions requested"); 1478 return EINVAL; 1479 } 1480 1481 *efx = hash_types; 1482 1483 return 0; 1484 } 1485 1486 uint64_t 1487 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx) 1488 { 1489 uint64_t rte = 0; 1490 unsigned int i; 1491 1492 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1493 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1494 1495 if ((efx & hash_type) == hash_type) 1496 rte |= rss->hf_map[i].rte; 1497 } 1498 1499 return rte; 1500 } 1501 1502 static int 1503 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1504 struct rte_eth_rss_conf *conf) 1505 { 1506 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1507 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1508 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types); 1509 int rc; 1510 1511 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1512 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1513 conf->rss_key != NULL) 1514 return EINVAL; 1515 } 1516 1517 if (conf->rss_hf != 0) { 1518 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1519 if (rc != 0) 1520 return rc; 1521 } 1522 1523 if (conf->rss_key != NULL) { 1524 if (conf->rss_key_len != sizeof(rss->key)) { 1525 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1526 sizeof(rss->key)); 1527 return EINVAL; 1528 } 1529 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1530 } 1531 1532 rss->hash_types = efx_hash_types; 1533 1534 return 0; 1535 } 1536 1537 static int 1538 sfc_rx_rss_config(struct sfc_adapter *sa) 1539 { 1540 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1541 int rc = 0; 1542 1543 if (rss->channels > 0) { 1544 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1545 rss->hash_alg, rss->hash_types, 1546 B_TRUE); 1547 if (rc != 0) 1548 goto finish; 1549 1550 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1551 rss->key, sizeof(rss->key)); 1552 if (rc != 0) 1553 goto finish; 1554 1555 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1556 rss->tbl, RTE_DIM(rss->tbl)); 1557 } 1558 1559 finish: 1560 return rc; 1561 } 1562 1563 struct sfc_rxq_info * 1564 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas, 1565 sfc_ethdev_qid_t ethdev_qid) 1566 { 1567 sfc_sw_index_t sw_index; 1568 1569 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count); 1570 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 1571 1572 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid); 1573 return &sas->rxq_info[sw_index]; 1574 } 1575 1576 struct sfc_rxq * 1577 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid) 1578 { 1579 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1580 sfc_sw_index_t sw_index; 1581 1582 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count); 1583 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 1584 1585 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid); 1586 return &sa->rxq_ctrl[sw_index]; 1587 } 1588 1589 int 1590 sfc_rx_start(struct sfc_adapter *sa) 1591 { 1592 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1593 sfc_sw_index_t sw_index; 1594 int rc; 1595 1596 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count, 1597 sas->rxq_count); 1598 1599 rc = efx_rx_init(sa->nic); 1600 if (rc != 0) 1601 goto fail_rx_init; 1602 1603 rc = sfc_rx_rss_config(sa); 1604 if (rc != 0) 1605 goto fail_rss_config; 1606 1607 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) { 1608 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED && 1609 (!sas->rxq_info[sw_index].deferred_start || 1610 sas->rxq_info[sw_index].deferred_started)) { 1611 rc = sfc_rx_qstart(sa, sw_index); 1612 if (rc != 0) 1613 goto fail_rx_qstart; 1614 } 1615 } 1616 1617 return 0; 1618 1619 fail_rx_qstart: 1620 while (sw_index-- > 0) 1621 sfc_rx_qstop(sa, sw_index); 1622 1623 fail_rss_config: 1624 efx_rx_fini(sa->nic); 1625 1626 fail_rx_init: 1627 sfc_log_init(sa, "failed %d", rc); 1628 return rc; 1629 } 1630 1631 void 1632 sfc_rx_stop(struct sfc_adapter *sa) 1633 { 1634 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1635 sfc_sw_index_t sw_index; 1636 1637 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count, 1638 sas->rxq_count); 1639 1640 sw_index = sas->rxq_count; 1641 while (sw_index-- > 0) { 1642 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED) 1643 sfc_rx_qstop(sa, sw_index); 1644 } 1645 1646 efx_rx_fini(sa->nic); 1647 } 1648 1649 int 1650 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 1651 unsigned int extra_efx_type_flags) 1652 { 1653 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1654 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index]; 1655 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1656 unsigned int max_entries; 1657 1658 max_entries = encp->enc_rxq_max_ndescs; 1659 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1660 1661 rxq_info->max_entries = max_entries; 1662 rxq_info->type_flags = extra_efx_type_flags; 1663 1664 return 0; 1665 } 1666 1667 static int 1668 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1669 { 1670 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1671 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1672 sfc_rx_get_queue_offload_caps(sa); 1673 struct sfc_rss *rss = &sas->rss; 1674 int rc = 0; 1675 1676 switch (rxmode->mq_mode) { 1677 case RTE_ETH_MQ_RX_NONE: 1678 /* No special checks are required */ 1679 break; 1680 case RTE_ETH_MQ_RX_RSS: 1681 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1682 sfc_err(sa, "RSS is not available"); 1683 rc = EINVAL; 1684 } 1685 break; 1686 default: 1687 sfc_err(sa, "Rx multi-queue mode %u not supported", 1688 rxmode->mq_mode); 1689 rc = EINVAL; 1690 } 1691 1692 /* 1693 * Requested offloads are validated against supported by ethdev, 1694 * so unsupported offloads cannot be added as the result of 1695 * below check. 1696 */ 1697 if ((rxmode->offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM) != 1698 (offloads_supported & RTE_ETH_RX_OFFLOAD_CHECKSUM)) { 1699 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1700 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_CHECKSUM; 1701 } 1702 1703 if ((offloads_supported & RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1704 (~rxmode->offloads & RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1705 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1706 rxmode->offloads |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1707 } 1708 1709 return rc; 1710 } 1711 1712 /** 1713 * Destroy excess queues that are no longer needed after reconfiguration 1714 * or complete close. 1715 */ 1716 static void 1717 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1718 { 1719 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1720 sfc_sw_index_t sw_index; 1721 sfc_ethdev_qid_t ethdev_qid; 1722 1723 SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count); 1724 1725 /* 1726 * Finalize only ethdev queues since other ones are finalized only 1727 * on device close and they may require additional deinitialization. 1728 */ 1729 ethdev_qid = sas->ethdev_rxq_count; 1730 while (--ethdev_qid >= (int)nb_rx_queues) { 1731 struct sfc_rxq_info *rxq_info; 1732 1733 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid); 1734 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 1735 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, 1736 ethdev_qid); 1737 sfc_rx_qfini(sa, sw_index); 1738 } 1739 1740 } 1741 1742 sas->ethdev_rxq_count = nb_rx_queues; 1743 } 1744 1745 /** 1746 * Initialize Rx subsystem. 1747 * 1748 * Called at device (re)configuration stage when number of receive queues is 1749 * specified together with other device level receive configuration. 1750 * 1751 * It should be used to allocate NUMA-unaware resources. 1752 */ 1753 int 1754 sfc_rx_configure(struct sfc_adapter *sa) 1755 { 1756 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1757 struct sfc_rss *rss = &sas->rss; 1758 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1759 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1760 const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas); 1761 const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues; 1762 bool reconfigure; 1763 int rc; 1764 1765 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1766 nb_rx_queues, sas->ethdev_rxq_count); 1767 1768 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1769 if (rc != 0) 1770 goto fail_check_mode; 1771 1772 if (nb_rxq_total == sas->rxq_count) { 1773 reconfigure = true; 1774 goto configure_rss; 1775 } 1776 1777 if (sas->rxq_info == NULL) { 1778 reconfigure = false; 1779 rc = ENOMEM; 1780 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total, 1781 sizeof(sas->rxq_info[0]), 0, 1782 sa->socket_id); 1783 if (sas->rxq_info == NULL) 1784 goto fail_rxqs_alloc; 1785 1786 /* 1787 * Allocate primary process only RxQ control from heap 1788 * since it should not be shared. 1789 */ 1790 rc = ENOMEM; 1791 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0])); 1792 if (sa->rxq_ctrl == NULL) 1793 goto fail_rxqs_ctrl_alloc; 1794 } else { 1795 struct sfc_rxq_info *new_rxq_info; 1796 struct sfc_rxq *new_rxq_ctrl; 1797 1798 reconfigure = true; 1799 1800 /* Do not uninitialize reserved queues */ 1801 if (nb_rx_queues < sas->ethdev_rxq_count) 1802 sfc_rx_fini_queues(sa, nb_rx_queues); 1803 1804 rc = ENOMEM; 1805 new_rxq_info = 1806 rte_realloc(sas->rxq_info, 1807 nb_rxq_total * sizeof(sas->rxq_info[0]), 0); 1808 if (new_rxq_info == NULL && nb_rxq_total > 0) 1809 goto fail_rxqs_realloc; 1810 1811 rc = ENOMEM; 1812 new_rxq_ctrl = realloc(sa->rxq_ctrl, 1813 nb_rxq_total * sizeof(sa->rxq_ctrl[0])); 1814 if (new_rxq_ctrl == NULL && nb_rxq_total > 0) 1815 goto fail_rxqs_ctrl_realloc; 1816 1817 sas->rxq_info = new_rxq_info; 1818 sa->rxq_ctrl = new_rxq_ctrl; 1819 if (nb_rxq_total > sas->rxq_count) { 1820 unsigned int rxq_count = sas->rxq_count; 1821 1822 memset(&sas->rxq_info[rxq_count], 0, 1823 (nb_rxq_total - rxq_count) * 1824 sizeof(sas->rxq_info[0])); 1825 memset(&sa->rxq_ctrl[rxq_count], 0, 1826 (nb_rxq_total - rxq_count) * 1827 sizeof(sa->rxq_ctrl[0])); 1828 } 1829 } 1830 1831 while (sas->ethdev_rxq_count < nb_rx_queues) { 1832 sfc_sw_index_t sw_index; 1833 1834 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, 1835 sas->ethdev_rxq_count); 1836 rc = sfc_rx_qinit_info(sa, sw_index, 0); 1837 if (rc != 0) 1838 goto fail_rx_qinit_info; 1839 1840 sas->ethdev_rxq_count++; 1841 } 1842 1843 sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues; 1844 1845 if (!reconfigure) { 1846 rc = sfc_mae_counter_rxq_init(sa); 1847 if (rc != 0) 1848 goto fail_count_rxq_init; 1849 } 1850 1851 configure_rss: 1852 rss->channels = (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) ? 1853 MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0; 1854 1855 if (rss->channels > 0) { 1856 struct rte_eth_rss_conf *adv_conf_rss; 1857 sfc_sw_index_t sw_index; 1858 1859 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1860 rss->tbl[sw_index] = sw_index % rss->channels; 1861 1862 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1863 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1864 if (rc != 0) 1865 goto fail_rx_process_adv_conf_rss; 1866 } 1867 1868 return 0; 1869 1870 fail_rx_process_adv_conf_rss: 1871 if (!reconfigure) 1872 sfc_mae_counter_rxq_fini(sa); 1873 1874 fail_count_rxq_init: 1875 fail_rx_qinit_info: 1876 fail_rxqs_ctrl_realloc: 1877 fail_rxqs_realloc: 1878 fail_rxqs_ctrl_alloc: 1879 fail_rxqs_alloc: 1880 sfc_rx_close(sa); 1881 1882 fail_check_mode: 1883 sfc_log_init(sa, "failed %d", rc); 1884 return rc; 1885 } 1886 1887 /** 1888 * Shutdown Rx subsystem. 1889 * 1890 * Called at device close stage, for example, before device shutdown. 1891 */ 1892 void 1893 sfc_rx_close(struct sfc_adapter *sa) 1894 { 1895 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1896 1897 sfc_rx_fini_queues(sa, 0); 1898 sfc_mae_counter_rxq_fini(sa); 1899 1900 rss->channels = 0; 1901 1902 free(sa->rxq_ctrl); 1903 sa->rxq_ctrl = NULL; 1904 1905 rte_free(sfc_sa2shared(sa)->rxq_info); 1906 sfc_sa2shared(sa)->rxq_info = NULL; 1907 } 1908