1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016-2018 Solarflare Communications Inc. 4 * All rights reserved. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_log.h" 17 #include "sfc_ev.h" 18 #include "sfc_rx.h" 19 #include "sfc_kvargs.h" 20 #include "sfc_tweak.h" 21 22 /* 23 * Maximum number of Rx queue flush attempt in the case of failure or 24 * flush timeout 25 */ 26 #define SFC_RX_QFLUSH_ATTEMPTS (3) 27 28 /* 29 * Time to wait between event queue polling attempts when waiting for Rx 30 * queue flush done or failed events. 31 */ 32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 33 34 /* 35 * Maximum number of event queue polling attempts when waiting for Rx queue 36 * flush done or failed events. It defines Rx queue flush attempt timeout 37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 38 */ 39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 40 41 void 42 sfc_rx_qflush_done(struct sfc_rxq *rxq) 43 { 44 rxq->state |= SFC_RXQ_FLUSHED; 45 rxq->state &= ~SFC_RXQ_FLUSHING; 46 } 47 48 void 49 sfc_rx_qflush_failed(struct sfc_rxq *rxq) 50 { 51 rxq->state |= SFC_RXQ_FLUSH_FAILED; 52 rxq->state &= ~SFC_RXQ_FLUSHING; 53 } 54 55 static void 56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 57 { 58 unsigned int free_space; 59 unsigned int bulks; 60 void *objs[SFC_RX_REFILL_BULK]; 61 efsys_dma_addr_t addr[RTE_DIM(objs)]; 62 unsigned int added = rxq->added; 63 unsigned int id; 64 unsigned int i; 65 struct sfc_efx_rx_sw_desc *rxd; 66 struct rte_mbuf *m; 67 uint16_t port_id = rxq->dp.dpq.port_id; 68 69 free_space = rxq->max_fill_level - (added - rxq->completed); 70 71 if (free_space < rxq->refill_threshold) 72 return; 73 74 bulks = free_space / RTE_DIM(objs); 75 /* refill_threshold guarantees that bulks is positive */ 76 SFC_ASSERT(bulks > 0); 77 78 id = added & rxq->ptr_mask; 79 do { 80 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 81 RTE_DIM(objs)) < 0)) { 82 /* 83 * It is hardly a safe way to increment counter 84 * from different contexts, but all PMDs do it. 85 */ 86 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 87 RTE_DIM(objs); 88 /* Return if we have posted nothing yet */ 89 if (added == rxq->added) 90 return; 91 /* Push posted */ 92 break; 93 } 94 95 for (i = 0; i < RTE_DIM(objs); 96 ++i, id = (id + 1) & rxq->ptr_mask) { 97 m = objs[i]; 98 99 rxd = &rxq->sw_desc[id]; 100 rxd->mbuf = m; 101 102 SFC_ASSERT(rte_mbuf_refcnt_read(m) == 1); 103 m->data_off = RTE_PKTMBUF_HEADROOM; 104 SFC_ASSERT(m->next == NULL); 105 SFC_ASSERT(m->nb_segs == 1); 106 m->port = port_id; 107 108 addr[i] = rte_pktmbuf_iova(m); 109 } 110 111 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 112 RTE_DIM(objs), rxq->completed, added); 113 added += RTE_DIM(objs); 114 } while (--bulks > 0); 115 116 SFC_ASSERT(added != rxq->added); 117 rxq->added = added; 118 efx_rx_qpush(rxq->common, added, &rxq->pushed); 119 } 120 121 static uint64_t 122 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 123 { 124 uint64_t mbuf_flags = 0; 125 126 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 127 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 128 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; 129 break; 130 case EFX_PKT_IPV4: 131 mbuf_flags |= PKT_RX_IP_CKSUM_BAD; 132 break; 133 default: 134 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0); 135 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) == 136 PKT_RX_IP_CKSUM_UNKNOWN); 137 break; 138 } 139 140 switch ((desc_flags & 141 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 142 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 143 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 144 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; 145 break; 146 case EFX_PKT_TCP: 147 case EFX_PKT_UDP: 148 mbuf_flags |= PKT_RX_L4_CKSUM_BAD; 149 break; 150 default: 151 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0); 152 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) == 153 PKT_RX_L4_CKSUM_UNKNOWN); 154 break; 155 } 156 157 return mbuf_flags; 158 } 159 160 static uint32_t 161 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 162 { 163 return RTE_PTYPE_L2_ETHER | 164 ((desc_flags & EFX_PKT_IPV4) ? 165 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 166 ((desc_flags & EFX_PKT_IPV6) ? 167 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 168 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 169 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 170 } 171 172 static const uint32_t * 173 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps) 174 { 175 static const uint32_t ptypes[] = { 176 RTE_PTYPE_L2_ETHER, 177 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 178 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 179 RTE_PTYPE_L4_TCP, 180 RTE_PTYPE_L4_UDP, 181 RTE_PTYPE_UNKNOWN 182 }; 183 184 return ptypes; 185 } 186 187 static void 188 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 189 struct rte_mbuf *m) 190 { 191 uint8_t *mbuf_data; 192 193 194 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 195 return; 196 197 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 198 199 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 200 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 201 EFX_RX_HASHALG_TOEPLITZ, 202 mbuf_data); 203 204 m->ol_flags |= PKT_RX_RSS_HASH; 205 } 206 } 207 208 static uint16_t 209 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 210 { 211 struct sfc_dp_rxq *dp_rxq = rx_queue; 212 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 213 unsigned int completed; 214 unsigned int prefix_size = rxq->prefix_size; 215 unsigned int done_pkts = 0; 216 boolean_t discard_next = B_FALSE; 217 struct rte_mbuf *scatter_pkt = NULL; 218 219 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 220 return 0; 221 222 sfc_ev_qpoll(rxq->evq); 223 224 completed = rxq->completed; 225 while (completed != rxq->pending && done_pkts < nb_pkts) { 226 unsigned int id; 227 struct sfc_efx_rx_sw_desc *rxd; 228 struct rte_mbuf *m; 229 unsigned int seg_len; 230 unsigned int desc_flags; 231 232 id = completed++ & rxq->ptr_mask; 233 rxd = &rxq->sw_desc[id]; 234 m = rxd->mbuf; 235 desc_flags = rxd->flags; 236 237 if (discard_next) 238 goto discard; 239 240 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 241 goto discard; 242 243 if (desc_flags & EFX_PKT_PREFIX_LEN) { 244 uint16_t tmp_size; 245 int rc __rte_unused; 246 247 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 248 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 249 SFC_ASSERT(rc == 0); 250 seg_len = tmp_size; 251 } else { 252 seg_len = rxd->size - prefix_size; 253 } 254 255 rte_pktmbuf_data_len(m) = seg_len; 256 rte_pktmbuf_pkt_len(m) = seg_len; 257 258 if (scatter_pkt != NULL) { 259 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 260 rte_pktmbuf_free(scatter_pkt); 261 goto discard; 262 } 263 /* The packet to deliver */ 264 m = scatter_pkt; 265 } 266 267 if (desc_flags & EFX_PKT_CONT) { 268 /* The packet is scattered, more fragments to come */ 269 scatter_pkt = m; 270 /* Further fragments have no prefix */ 271 prefix_size = 0; 272 continue; 273 } 274 275 /* Scattered packet is done */ 276 scatter_pkt = NULL; 277 /* The first fragment of the packet has prefix */ 278 prefix_size = rxq->prefix_size; 279 280 m->ol_flags = 281 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 282 m->packet_type = 283 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 284 285 /* 286 * Extract RSS hash from the packet prefix and 287 * set the corresponding field (if needed and possible) 288 */ 289 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 290 291 m->data_off += prefix_size; 292 293 *rx_pkts++ = m; 294 done_pkts++; 295 continue; 296 297 discard: 298 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 299 rte_mempool_put(rxq->refill_mb_pool, m); 300 rxd->mbuf = NULL; 301 } 302 303 /* pending is only moved when entire packet is received */ 304 SFC_ASSERT(scatter_pkt == NULL); 305 306 rxq->completed = completed; 307 308 sfc_efx_rx_qrefill(rxq); 309 310 return done_pkts; 311 } 312 313 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 314 static unsigned int 315 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 316 { 317 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 318 319 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 320 return 0; 321 322 sfc_ev_qpoll(rxq->evq); 323 324 return rxq->pending - rxq->completed; 325 } 326 327 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 328 static int 329 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 330 { 331 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 332 333 if (unlikely(offset > rxq->ptr_mask)) 334 return -EINVAL; 335 336 /* 337 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 338 * it is required for the queue to be running, but the 339 * check is omitted because API design assumes that it 340 * is the duty of the caller to satisfy all conditions 341 */ 342 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 343 SFC_EFX_RXQ_FLAG_RUNNING); 344 sfc_ev_qpoll(rxq->evq); 345 346 /* 347 * There is a handful of reserved entries in the ring, 348 * but an explicit check whether the offset points to 349 * a reserved entry is neglected since the two checks 350 * below rely on the figures which take the HW limits 351 * into account and thus if an entry is reserved, the 352 * checks will fail and UNAVAIL code will be returned 353 */ 354 355 if (offset < (rxq->pending - rxq->completed)) 356 return RTE_ETH_RX_DESC_DONE; 357 358 if (offset < (rxq->added - rxq->completed)) 359 return RTE_ETH_RX_DESC_AVAIL; 360 361 return RTE_ETH_RX_DESC_UNAVAIL; 362 } 363 364 struct sfc_rxq * 365 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 366 { 367 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 368 struct rte_eth_dev *eth_dev; 369 struct sfc_adapter *sa; 370 struct sfc_rxq *rxq; 371 372 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 373 eth_dev = &rte_eth_devices[dpq->port_id]; 374 375 sa = eth_dev->data->dev_private; 376 377 SFC_ASSERT(dpq->queue_id < sa->rxq_count); 378 rxq = sa->rxq_info[dpq->queue_id].rxq; 379 380 SFC_ASSERT(rxq != NULL); 381 return rxq; 382 } 383 384 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 385 static int 386 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 387 __rte_unused struct rte_mempool *mb_pool, 388 unsigned int *rxq_entries, 389 unsigned int *evq_entries, 390 unsigned int *rxq_max_fill_level) 391 { 392 *rxq_entries = nb_rx_desc; 393 *evq_entries = nb_rx_desc; 394 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 395 return 0; 396 } 397 398 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 399 static int 400 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 401 const struct rte_pci_addr *pci_addr, int socket_id, 402 const struct sfc_dp_rx_qcreate_info *info, 403 struct sfc_dp_rxq **dp_rxqp) 404 { 405 struct sfc_efx_rxq *rxq; 406 int rc; 407 408 rc = ENOMEM; 409 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 410 RTE_CACHE_LINE_SIZE, socket_id); 411 if (rxq == NULL) 412 goto fail_rxq_alloc; 413 414 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 415 416 rc = ENOMEM; 417 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 418 info->rxq_entries, 419 sizeof(*rxq->sw_desc), 420 RTE_CACHE_LINE_SIZE, socket_id); 421 if (rxq->sw_desc == NULL) 422 goto fail_desc_alloc; 423 424 /* efx datapath is bound to efx control path */ 425 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 426 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 427 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 428 rxq->ptr_mask = info->rxq_entries - 1; 429 rxq->batch_max = info->batch_max; 430 rxq->prefix_size = info->prefix_size; 431 rxq->max_fill_level = info->max_fill_level; 432 rxq->refill_threshold = info->refill_threshold; 433 rxq->buf_size = info->buf_size; 434 rxq->refill_mb_pool = info->refill_mb_pool; 435 436 *dp_rxqp = &rxq->dp; 437 return 0; 438 439 fail_desc_alloc: 440 rte_free(rxq); 441 442 fail_rxq_alloc: 443 return rc; 444 } 445 446 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 447 static void 448 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 449 { 450 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 451 452 rte_free(rxq->sw_desc); 453 rte_free(rxq); 454 } 455 456 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 457 static int 458 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 459 __rte_unused unsigned int evq_read_ptr) 460 { 461 /* libefx-based datapath is specific to libefx-based PMD */ 462 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 463 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 464 465 rxq->common = crxq->common; 466 467 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 468 469 sfc_efx_rx_qrefill(rxq); 470 471 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 472 473 return 0; 474 } 475 476 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 477 static void 478 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 479 __rte_unused unsigned int *evq_read_ptr) 480 { 481 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 482 483 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 484 485 /* libefx-based datapath is bound to libefx-based PMD and uses 486 * event queue structure directly. So, there is no necessity to 487 * return EvQ read pointer. 488 */ 489 } 490 491 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 492 static void 493 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 494 { 495 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 496 unsigned int i; 497 struct sfc_efx_rx_sw_desc *rxd; 498 499 for (i = rxq->completed; i != rxq->added; ++i) { 500 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 501 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf); 502 rxd->mbuf = NULL; 503 /* Packed stream relies on 0 in inactive SW desc. 504 * Rx queue stop is not performance critical, so 505 * there is no harm to do it always. 506 */ 507 rxd->flags = 0; 508 rxd->size = 0; 509 } 510 511 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 512 } 513 514 struct sfc_dp_rx sfc_efx_rx = { 515 .dp = { 516 .name = SFC_KVARG_DATAPATH_EFX, 517 .type = SFC_DP_RX, 518 .hw_fw_caps = 0, 519 }, 520 .features = SFC_DP_RX_FEAT_SCATTER | 521 SFC_DP_RX_FEAT_CHECKSUM, 522 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 523 .qcreate = sfc_efx_rx_qcreate, 524 .qdestroy = sfc_efx_rx_qdestroy, 525 .qstart = sfc_efx_rx_qstart, 526 .qstop = sfc_efx_rx_qstop, 527 .qpurge = sfc_efx_rx_qpurge, 528 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 529 .qdesc_npending = sfc_efx_rx_qdesc_npending, 530 .qdesc_status = sfc_efx_rx_qdesc_status, 531 .pkt_burst = sfc_efx_recv_pkts, 532 }; 533 534 unsigned int 535 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index) 536 { 537 struct sfc_rxq *rxq; 538 539 SFC_ASSERT(sw_index < sa->rxq_count); 540 rxq = sa->rxq_info[sw_index].rxq; 541 542 if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0) 543 return 0; 544 545 return sa->dp_rx->qdesc_npending(rxq->dp); 546 } 547 548 int 549 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset) 550 { 551 struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq); 552 553 return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq); 554 } 555 556 static void 557 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index) 558 { 559 struct sfc_rxq *rxq; 560 unsigned int retry_count; 561 unsigned int wait_count; 562 int rc; 563 564 rxq = sa->rxq_info[sw_index].rxq; 565 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED); 566 567 /* 568 * Retry Rx queue flushing in the case of flush failed or 569 * timeout. In the worst case it can delay for 6 seconds. 570 */ 571 for (retry_count = 0; 572 ((rxq->state & SFC_RXQ_FLUSHED) == 0) && 573 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 574 ++retry_count) { 575 rc = efx_rx_qflush(rxq->common); 576 if (rc != 0) { 577 rxq->state |= (rc == EALREADY) ? 578 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 579 break; 580 } 581 rxq->state &= ~SFC_RXQ_FLUSH_FAILED; 582 rxq->state |= SFC_RXQ_FLUSHING; 583 584 /* 585 * Wait for Rx queue flush done or failed event at least 586 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 587 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 588 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 589 */ 590 wait_count = 0; 591 do { 592 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 593 sfc_ev_qpoll(rxq->evq); 594 } while ((rxq->state & SFC_RXQ_FLUSHING) && 595 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 596 597 if (rxq->state & SFC_RXQ_FLUSHING) 598 sfc_err(sa, "RxQ %u flush timed out", sw_index); 599 600 if (rxq->state & SFC_RXQ_FLUSH_FAILED) 601 sfc_err(sa, "RxQ %u flush failed", sw_index); 602 603 if (rxq->state & SFC_RXQ_FLUSHED) 604 sfc_notice(sa, "RxQ %u flushed", sw_index); 605 } 606 607 sa->dp_rx->qpurge(rxq->dp); 608 } 609 610 static int 611 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 612 { 613 struct sfc_rss *rss = &sa->rss; 614 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 615 struct sfc_port *port = &sa->port; 616 int rc; 617 618 /* 619 * If promiscuous or all-multicast mode has been requested, setting 620 * filter for the default Rx queue might fail, in particular, while 621 * running over PCI function which is not a member of corresponding 622 * privilege groups; if this occurs, few iterations will be made to 623 * repeat this step without promiscuous and all-multicast flags set 624 */ 625 retry: 626 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 627 if (rc == 0) 628 return 0; 629 else if (rc != EOPNOTSUPP) 630 return rc; 631 632 if (port->promisc) { 633 sfc_warn(sa, "promiscuous mode has been requested, " 634 "but the HW rejects it"); 635 sfc_warn(sa, "promiscuous mode will be disabled"); 636 637 port->promisc = B_FALSE; 638 rc = sfc_set_rx_mode(sa); 639 if (rc != 0) 640 return rc; 641 642 goto retry; 643 } 644 645 if (port->allmulti) { 646 sfc_warn(sa, "all-multicast mode has been requested, " 647 "but the HW rejects it"); 648 sfc_warn(sa, "all-multicast mode will be disabled"); 649 650 port->allmulti = B_FALSE; 651 rc = sfc_set_rx_mode(sa); 652 if (rc != 0) 653 return rc; 654 655 goto retry; 656 } 657 658 return rc; 659 } 660 661 int 662 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 663 { 664 struct sfc_port *port = &sa->port; 665 struct sfc_rxq_info *rxq_info; 666 struct sfc_rxq *rxq; 667 struct sfc_evq *evq; 668 int rc; 669 670 sfc_log_init(sa, "sw_index=%u", sw_index); 671 672 SFC_ASSERT(sw_index < sa->rxq_count); 673 674 rxq_info = &sa->rxq_info[sw_index]; 675 rxq = rxq_info->rxq; 676 SFC_ASSERT(rxq != NULL); 677 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED); 678 679 evq = rxq->evq; 680 681 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index)); 682 if (rc != 0) 683 goto fail_ev_qstart; 684 685 switch (rxq_info->type) { 686 case EFX_RXQ_TYPE_DEFAULT: 687 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 688 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 689 rxq_info->type_flags, evq->common, &rxq->common); 690 break; 691 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 692 struct rte_mempool *mp = rxq->refill_mb_pool; 693 struct rte_mempool_info mp_info; 694 695 rc = rte_mempool_ops_get_info(mp, &mp_info); 696 if (rc != 0) { 697 /* Positive errno is used in the driver */ 698 rc = -rc; 699 goto fail_mp_get_info; 700 } 701 if (mp_info.contig_block_size <= 0) { 702 rc = EINVAL; 703 goto fail_bad_contig_block_size; 704 } 705 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 706 mp_info.contig_block_size, rxq->buf_size, 707 mp->header_size + mp->elt_size + mp->trailer_size, 708 sa->rxd_wait_timeout_ns, 709 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 710 evq->common, &rxq->common); 711 break; 712 } 713 default: 714 rc = ENOTSUP; 715 } 716 if (rc != 0) 717 goto fail_rx_qcreate; 718 719 efx_rx_qenable(rxq->common); 720 721 rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr); 722 if (rc != 0) 723 goto fail_dp_qstart; 724 725 rxq->state |= SFC_RXQ_STARTED; 726 727 if ((sw_index == 0) && !port->isolated) { 728 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 729 if (rc != 0) 730 goto fail_mac_filter_default_rxq_set; 731 } 732 733 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 734 sa->eth_dev->data->rx_queue_state[sw_index] = 735 RTE_ETH_QUEUE_STATE_STARTED; 736 737 return 0; 738 739 fail_mac_filter_default_rxq_set: 740 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr); 741 742 fail_dp_qstart: 743 sfc_rx_qflush(sa, sw_index); 744 745 fail_rx_qcreate: 746 fail_bad_contig_block_size: 747 fail_mp_get_info: 748 sfc_ev_qstop(evq); 749 750 fail_ev_qstart: 751 return rc; 752 } 753 754 void 755 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 756 { 757 struct sfc_rxq_info *rxq_info; 758 struct sfc_rxq *rxq; 759 760 sfc_log_init(sa, "sw_index=%u", sw_index); 761 762 SFC_ASSERT(sw_index < sa->rxq_count); 763 764 rxq_info = &sa->rxq_info[sw_index]; 765 rxq = rxq_info->rxq; 766 767 if (rxq == NULL || rxq->state == SFC_RXQ_INITIALIZED) 768 return; 769 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED); 770 771 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 772 sa->eth_dev->data->rx_queue_state[sw_index] = 773 RTE_ETH_QUEUE_STATE_STOPPED; 774 775 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr); 776 777 if (sw_index == 0) 778 efx_mac_filter_default_rxq_clear(sa->nic); 779 780 sfc_rx_qflush(sa, sw_index); 781 782 rxq->state = SFC_RXQ_INITIALIZED; 783 784 efx_rx_qdestroy(rxq->common); 785 786 sfc_ev_qstop(rxq->evq); 787 } 788 789 uint64_t 790 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 791 { 792 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 793 uint64_t caps = 0; 794 795 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME; 796 797 if (sa->dp_rx->features & SFC_DP_RX_FEAT_CHECKSUM) { 798 caps |= DEV_RX_OFFLOAD_IPV4_CKSUM; 799 caps |= DEV_RX_OFFLOAD_UDP_CKSUM; 800 caps |= DEV_RX_OFFLOAD_TCP_CKSUM; 801 } 802 803 if (encp->enc_tunnel_encapsulations_supported && 804 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS)) 805 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 806 807 return caps; 808 } 809 810 uint64_t 811 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 812 { 813 uint64_t caps = 0; 814 815 if (sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER) 816 caps |= DEV_RX_OFFLOAD_SCATTER; 817 818 return caps; 819 } 820 821 static int 822 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 823 const struct rte_eth_rxconf *rx_conf, 824 __rte_unused uint64_t offloads) 825 { 826 int rc = 0; 827 828 if (rx_conf->rx_thresh.pthresh != 0 || 829 rx_conf->rx_thresh.hthresh != 0 || 830 rx_conf->rx_thresh.wthresh != 0) { 831 sfc_warn(sa, 832 "RxQ prefetch/host/writeback thresholds are not supported"); 833 } 834 835 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 836 sfc_err(sa, 837 "RxQ free threshold too large: %u vs maximum %u", 838 rx_conf->rx_free_thresh, rxq_max_fill_level); 839 rc = EINVAL; 840 } 841 842 if (rx_conf->rx_drop_en == 0) { 843 sfc_err(sa, "RxQ drop disable is not supported"); 844 rc = EINVAL; 845 } 846 847 return rc; 848 } 849 850 static unsigned int 851 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 852 { 853 uint32_t data_off; 854 uint32_t order; 855 856 /* The mbuf object itself is always cache line aligned */ 857 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 858 859 /* Data offset from mbuf object start */ 860 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 861 RTE_PKTMBUF_HEADROOM; 862 863 order = MIN(order, rte_bsf32(data_off)); 864 865 return 1u << order; 866 } 867 868 static uint16_t 869 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 870 { 871 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 872 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 873 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 874 uint16_t buf_size; 875 unsigned int buf_aligned; 876 unsigned int start_alignment; 877 unsigned int end_padding_alignment; 878 879 /* Below it is assumed that both alignments are power of 2 */ 880 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 881 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 882 883 /* 884 * mbuf is always cache line aligned, double-check 885 * that it meets rx buffer start alignment requirements. 886 */ 887 888 /* Start from mbuf pool data room size */ 889 buf_size = rte_pktmbuf_data_room_size(mb_pool); 890 891 /* Remove headroom */ 892 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 893 sfc_err(sa, 894 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 895 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 896 return 0; 897 } 898 buf_size -= RTE_PKTMBUF_HEADROOM; 899 900 /* Calculate guaranteed data start alignment */ 901 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 902 903 /* Reserve space for start alignment */ 904 if (buf_aligned < nic_align_start) { 905 start_alignment = nic_align_start - buf_aligned; 906 if (buf_size <= start_alignment) { 907 sfc_err(sa, 908 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 909 mb_pool->name, 910 rte_pktmbuf_data_room_size(mb_pool), 911 RTE_PKTMBUF_HEADROOM, start_alignment); 912 return 0; 913 } 914 buf_aligned = nic_align_start; 915 buf_size -= start_alignment; 916 } else { 917 start_alignment = 0; 918 } 919 920 /* Make sure that end padding does not write beyond the buffer */ 921 if (buf_aligned < nic_align_end) { 922 /* 923 * Estimate space which can be lost. If guarnteed buffer 924 * size is odd, lost space is (nic_align_end - 1). More 925 * accurate formula is below. 926 */ 927 end_padding_alignment = nic_align_end - 928 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 929 if (buf_size <= end_padding_alignment) { 930 sfc_err(sa, 931 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 932 mb_pool->name, 933 rte_pktmbuf_data_room_size(mb_pool), 934 RTE_PKTMBUF_HEADROOM, start_alignment, 935 end_padding_alignment); 936 return 0; 937 } 938 buf_size -= end_padding_alignment; 939 } else { 940 /* 941 * Start is aligned the same or better than end, 942 * just align length. 943 */ 944 buf_size = P2ALIGN(buf_size, nic_align_end); 945 } 946 947 return buf_size; 948 } 949 950 int 951 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 952 uint16_t nb_rx_desc, unsigned int socket_id, 953 const struct rte_eth_rxconf *rx_conf, 954 struct rte_mempool *mb_pool) 955 { 956 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 957 struct sfc_rss *rss = &sa->rss; 958 int rc; 959 unsigned int rxq_entries; 960 unsigned int evq_entries; 961 unsigned int rxq_max_fill_level; 962 uint64_t offloads; 963 uint16_t buf_size; 964 struct sfc_rxq_info *rxq_info; 965 struct sfc_evq *evq; 966 struct sfc_rxq *rxq; 967 struct sfc_dp_rx_qcreate_info info; 968 969 rc = sa->dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries, 970 &evq_entries, &rxq_max_fill_level); 971 if (rc != 0) 972 goto fail_size_up_rings; 973 SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS); 974 SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS); 975 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 976 977 offloads = rx_conf->offloads | 978 sa->eth_dev->data->dev_conf.rxmode.offloads; 979 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 980 if (rc != 0) 981 goto fail_bad_conf; 982 983 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 984 if (buf_size == 0) { 985 sfc_err(sa, "RxQ %u mbuf pool object size is too small", 986 sw_index); 987 rc = EINVAL; 988 goto fail_bad_conf; 989 } 990 991 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) && 992 (~offloads & DEV_RX_OFFLOAD_SCATTER)) { 993 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool " 994 "object size is too small", sw_index); 995 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs " 996 "PDU size %u plus Rx prefix %u bytes", 997 sw_index, buf_size, (unsigned int)sa->port.pdu, 998 encp->enc_rx_prefix_size); 999 rc = EINVAL; 1000 goto fail_bad_conf; 1001 } 1002 1003 SFC_ASSERT(sw_index < sa->rxq_count); 1004 rxq_info = &sa->rxq_info[sw_index]; 1005 1006 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1007 rxq_info->entries = rxq_entries; 1008 1009 if (sa->dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1010 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1011 else 1012 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1013 1014 rxq_info->type_flags = 1015 (offloads & DEV_RX_OFFLOAD_SCATTER) ? 1016 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1017 1018 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1019 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS)) 1020 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1021 1022 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1023 evq_entries, socket_id, &evq); 1024 if (rc != 0) 1025 goto fail_ev_qinit; 1026 1027 rc = ENOMEM; 1028 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE, 1029 socket_id); 1030 if (rxq == NULL) 1031 goto fail_rxq_alloc; 1032 1033 rxq_info->rxq = rxq; 1034 1035 rxq->evq = evq; 1036 rxq->hw_index = sw_index; 1037 rxq->refill_threshold = 1038 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK); 1039 rxq->refill_mb_pool = mb_pool; 1040 rxq->buf_size = buf_size; 1041 1042 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries), 1043 socket_id, &rxq->mem); 1044 if (rc != 0) 1045 goto fail_dma_alloc; 1046 1047 memset(&info, 0, sizeof(info)); 1048 info.refill_mb_pool = rxq->refill_mb_pool; 1049 info.max_fill_level = rxq_max_fill_level; 1050 info.refill_threshold = rxq->refill_threshold; 1051 info.buf_size = buf_size; 1052 info.batch_max = encp->enc_rx_batch_max; 1053 info.prefix_size = encp->enc_rx_prefix_size; 1054 1055 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0) 1056 info.flags |= SFC_RXQ_FLAG_RSS_HASH; 1057 1058 info.rxq_entries = rxq_info->entries; 1059 info.rxq_hw_ring = rxq->mem.esm_base; 1060 info.evq_entries = evq_entries; 1061 info.evq_hw_ring = evq->mem.esm_base; 1062 info.hw_index = rxq->hw_index; 1063 info.mem_bar = sa->mem_bar.esb_base; 1064 info.vi_window_shift = encp->enc_vi_window_shift; 1065 1066 rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1067 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1068 socket_id, &info, &rxq->dp); 1069 if (rc != 0) 1070 goto fail_dp_rx_qcreate; 1071 1072 evq->dp_rxq = rxq->dp; 1073 1074 rxq->state = SFC_RXQ_INITIALIZED; 1075 1076 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1077 1078 return 0; 1079 1080 fail_dp_rx_qcreate: 1081 sfc_dma_free(sa, &rxq->mem); 1082 1083 fail_dma_alloc: 1084 rxq_info->rxq = NULL; 1085 rte_free(rxq); 1086 1087 fail_rxq_alloc: 1088 sfc_ev_qfini(evq); 1089 1090 fail_ev_qinit: 1091 rxq_info->entries = 0; 1092 1093 fail_bad_conf: 1094 fail_size_up_rings: 1095 sfc_log_init(sa, "failed %d", rc); 1096 return rc; 1097 } 1098 1099 void 1100 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 1101 { 1102 struct sfc_rxq_info *rxq_info; 1103 struct sfc_rxq *rxq; 1104 1105 SFC_ASSERT(sw_index < sa->rxq_count); 1106 sa->eth_dev->data->rx_queues[sw_index] = NULL; 1107 1108 rxq_info = &sa->rxq_info[sw_index]; 1109 1110 rxq = rxq_info->rxq; 1111 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED); 1112 1113 sa->dp_rx->qdestroy(rxq->dp); 1114 rxq->dp = NULL; 1115 1116 rxq_info->rxq = NULL; 1117 rxq_info->entries = 0; 1118 1119 sfc_dma_free(sa, &rxq->mem); 1120 1121 sfc_ev_qfini(rxq->evq); 1122 rxq->evq = NULL; 1123 1124 rte_free(rxq); 1125 } 1126 1127 /* 1128 * Mapping between RTE RSS hash functions and their EFX counterparts. 1129 */ 1130 struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1131 { ETH_RSS_NONFRAG_IPV4_TCP, 1132 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1133 { ETH_RSS_NONFRAG_IPV4_UDP, 1134 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1135 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX, 1136 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1137 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX, 1138 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1139 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER, 1140 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1141 EFX_RX_HASH(IPV4, 2TUPLE) }, 1142 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER | 1143 ETH_RSS_IPV6_EX, 1144 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1145 EFX_RX_HASH(IPV6, 2TUPLE) } 1146 }; 1147 1148 static efx_rx_hash_type_t 1149 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1150 unsigned int *hash_type_flags_supported, 1151 unsigned int nb_hash_type_flags_supported) 1152 { 1153 efx_rx_hash_type_t hash_type_masked = 0; 1154 unsigned int i, j; 1155 1156 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1157 unsigned int class_tuple_lbn[] = { 1158 EFX_RX_CLASS_IPV4_TCP_LBN, 1159 EFX_RX_CLASS_IPV4_UDP_LBN, 1160 EFX_RX_CLASS_IPV4_LBN, 1161 EFX_RX_CLASS_IPV6_TCP_LBN, 1162 EFX_RX_CLASS_IPV6_UDP_LBN, 1163 EFX_RX_CLASS_IPV6_LBN 1164 }; 1165 1166 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1167 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1168 unsigned int flag; 1169 1170 tuple_mask <<= class_tuple_lbn[j]; 1171 flag = hash_type & tuple_mask; 1172 1173 if (flag == hash_type_flags_supported[i]) 1174 hash_type_masked |= flag; 1175 } 1176 } 1177 1178 return hash_type_masked; 1179 } 1180 1181 int 1182 sfc_rx_hash_init(struct sfc_adapter *sa) 1183 { 1184 struct sfc_rss *rss = &sa->rss; 1185 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1186 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1187 efx_rx_hash_alg_t alg; 1188 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1189 unsigned int nb_flags_supp; 1190 struct sfc_rss_hf_rte_to_efx *hf_map; 1191 struct sfc_rss_hf_rte_to_efx *entry; 1192 efx_rx_hash_type_t efx_hash_types; 1193 unsigned int i; 1194 int rc; 1195 1196 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1197 alg = EFX_RX_HASHALG_TOEPLITZ; 1198 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1199 alg = EFX_RX_HASHALG_PACKED_STREAM; 1200 else 1201 return EINVAL; 1202 1203 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1204 RTE_DIM(flags_supp), &nb_flags_supp); 1205 if (rc != 0) 1206 return rc; 1207 1208 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1209 RTE_DIM(sfc_rss_hf_map), 1210 sizeof(*hf_map), 0, sa->socket_id); 1211 if (hf_map == NULL) 1212 return ENOMEM; 1213 1214 entry = hf_map; 1215 efx_hash_types = 0; 1216 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1217 efx_rx_hash_type_t ht; 1218 1219 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1220 flags_supp, nb_flags_supp); 1221 if (ht != 0) { 1222 entry->rte = sfc_rss_hf_map[i].rte; 1223 entry->efx = ht; 1224 efx_hash_types |= ht; 1225 ++entry; 1226 } 1227 } 1228 1229 rss->hash_alg = alg; 1230 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1231 rss->hf_map = hf_map; 1232 rss->hash_types = efx_hash_types; 1233 1234 return 0; 1235 } 1236 1237 void 1238 sfc_rx_hash_fini(struct sfc_adapter *sa) 1239 { 1240 struct sfc_rss *rss = &sa->rss; 1241 1242 rte_free(rss->hf_map); 1243 } 1244 1245 int 1246 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1247 efx_rx_hash_type_t *efx) 1248 { 1249 struct sfc_rss *rss = &sa->rss; 1250 efx_rx_hash_type_t hash_types = 0; 1251 unsigned int i; 1252 1253 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1254 uint64_t rte_mask = rss->hf_map[i].rte; 1255 1256 if ((rte & rte_mask) != 0) { 1257 rte &= ~rte_mask; 1258 hash_types |= rss->hf_map[i].efx; 1259 } 1260 } 1261 1262 if (rte != 0) { 1263 sfc_err(sa, "unsupported hash functions requested"); 1264 return EINVAL; 1265 } 1266 1267 *efx = hash_types; 1268 1269 return 0; 1270 } 1271 1272 uint64_t 1273 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx) 1274 { 1275 struct sfc_rss *rss = &sa->rss; 1276 uint64_t rte = 0; 1277 unsigned int i; 1278 1279 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1280 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1281 1282 if ((efx & hash_type) == hash_type) 1283 rte |= rss->hf_map[i].rte; 1284 } 1285 1286 return rte; 1287 } 1288 1289 static int 1290 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1291 struct rte_eth_rss_conf *conf) 1292 { 1293 struct sfc_rss *rss = &sa->rss; 1294 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1295 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types); 1296 int rc; 1297 1298 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1299 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1300 conf->rss_key != NULL) 1301 return EINVAL; 1302 } 1303 1304 if (conf->rss_hf != 0) { 1305 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1306 if (rc != 0) 1307 return rc; 1308 } 1309 1310 if (conf->rss_key != NULL) { 1311 if (conf->rss_key_len != sizeof(rss->key)) { 1312 sfc_err(sa, "RSS key size is wrong (should be %lu)", 1313 sizeof(rss->key)); 1314 return EINVAL; 1315 } 1316 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1317 } 1318 1319 rss->hash_types = efx_hash_types; 1320 1321 return 0; 1322 } 1323 1324 static int 1325 sfc_rx_rss_config(struct sfc_adapter *sa) 1326 { 1327 struct sfc_rss *rss = &sa->rss; 1328 int rc = 0; 1329 1330 if (rss->channels > 0) { 1331 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1332 rss->hash_alg, rss->hash_types, 1333 B_TRUE); 1334 if (rc != 0) 1335 goto finish; 1336 1337 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1338 rss->key, sizeof(rss->key)); 1339 if (rc != 0) 1340 goto finish; 1341 1342 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1343 rss->tbl, RTE_DIM(rss->tbl)); 1344 } 1345 1346 finish: 1347 return rc; 1348 } 1349 1350 int 1351 sfc_rx_start(struct sfc_adapter *sa) 1352 { 1353 unsigned int sw_index; 1354 int rc; 1355 1356 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count); 1357 1358 rc = efx_rx_init(sa->nic); 1359 if (rc != 0) 1360 goto fail_rx_init; 1361 1362 rc = sfc_rx_rss_config(sa); 1363 if (rc != 0) 1364 goto fail_rss_config; 1365 1366 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) { 1367 if (sa->rxq_info[sw_index].rxq != NULL && 1368 (!sa->rxq_info[sw_index].deferred_start || 1369 sa->rxq_info[sw_index].deferred_started)) { 1370 rc = sfc_rx_qstart(sa, sw_index); 1371 if (rc != 0) 1372 goto fail_rx_qstart; 1373 } 1374 } 1375 1376 return 0; 1377 1378 fail_rx_qstart: 1379 while (sw_index-- > 0) 1380 sfc_rx_qstop(sa, sw_index); 1381 1382 fail_rss_config: 1383 efx_rx_fini(sa->nic); 1384 1385 fail_rx_init: 1386 sfc_log_init(sa, "failed %d", rc); 1387 return rc; 1388 } 1389 1390 void 1391 sfc_rx_stop(struct sfc_adapter *sa) 1392 { 1393 unsigned int sw_index; 1394 1395 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count); 1396 1397 sw_index = sa->rxq_count; 1398 while (sw_index-- > 0) { 1399 if (sa->rxq_info[sw_index].rxq != NULL) 1400 sfc_rx_qstop(sa, sw_index); 1401 } 1402 1403 efx_rx_fini(sa->nic); 1404 } 1405 1406 static int 1407 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 1408 { 1409 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index]; 1410 unsigned int max_entries; 1411 1412 max_entries = EFX_RXQ_MAXNDESCS; 1413 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1414 1415 rxq_info->max_entries = max_entries; 1416 1417 return 0; 1418 } 1419 1420 static int 1421 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1422 { 1423 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1424 sfc_rx_get_queue_offload_caps(sa); 1425 struct sfc_rss *rss = &sa->rss; 1426 int rc = 0; 1427 1428 switch (rxmode->mq_mode) { 1429 case ETH_MQ_RX_NONE: 1430 /* No special checks are required */ 1431 break; 1432 case ETH_MQ_RX_RSS: 1433 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1434 sfc_err(sa, "RSS is not available"); 1435 rc = EINVAL; 1436 } 1437 break; 1438 default: 1439 sfc_err(sa, "Rx multi-queue mode %u not supported", 1440 rxmode->mq_mode); 1441 rc = EINVAL; 1442 } 1443 1444 /* 1445 * Requested offloads are validated against supported by ethdev, 1446 * so unsupported offloads cannot be added as the result of 1447 * below check. 1448 */ 1449 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) != 1450 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) { 1451 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1452 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM; 1453 } 1454 1455 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1456 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1457 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1458 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1459 } 1460 1461 return rc; 1462 } 1463 1464 /** 1465 * Destroy excess queues that are no longer needed after reconfiguration 1466 * or complete close. 1467 */ 1468 static void 1469 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1470 { 1471 int sw_index; 1472 1473 SFC_ASSERT(nb_rx_queues <= sa->rxq_count); 1474 1475 sw_index = sa->rxq_count; 1476 while (--sw_index >= (int)nb_rx_queues) { 1477 if (sa->rxq_info[sw_index].rxq != NULL) 1478 sfc_rx_qfini(sa, sw_index); 1479 } 1480 1481 sa->rxq_count = nb_rx_queues; 1482 } 1483 1484 /** 1485 * Initialize Rx subsystem. 1486 * 1487 * Called at device (re)configuration stage when number of receive queues is 1488 * specified together with other device level receive configuration. 1489 * 1490 * It should be used to allocate NUMA-unaware resources. 1491 */ 1492 int 1493 sfc_rx_configure(struct sfc_adapter *sa) 1494 { 1495 struct sfc_rss *rss = &sa->rss; 1496 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1497 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1498 int rc; 1499 1500 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1501 nb_rx_queues, sa->rxq_count); 1502 1503 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1504 if (rc != 0) 1505 goto fail_check_mode; 1506 1507 if (nb_rx_queues == sa->rxq_count) 1508 goto done; 1509 1510 if (sa->rxq_info == NULL) { 1511 rc = ENOMEM; 1512 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues, 1513 sizeof(sa->rxq_info[0]), 0, 1514 sa->socket_id); 1515 if (sa->rxq_info == NULL) 1516 goto fail_rxqs_alloc; 1517 } else { 1518 struct sfc_rxq_info *new_rxq_info; 1519 1520 if (nb_rx_queues < sa->rxq_count) 1521 sfc_rx_fini_queues(sa, nb_rx_queues); 1522 1523 rc = ENOMEM; 1524 new_rxq_info = 1525 rte_realloc(sa->rxq_info, 1526 nb_rx_queues * sizeof(sa->rxq_info[0]), 0); 1527 if (new_rxq_info == NULL && nb_rx_queues > 0) 1528 goto fail_rxqs_realloc; 1529 1530 sa->rxq_info = new_rxq_info; 1531 if (nb_rx_queues > sa->rxq_count) 1532 memset(&sa->rxq_info[sa->rxq_count], 0, 1533 (nb_rx_queues - sa->rxq_count) * 1534 sizeof(sa->rxq_info[0])); 1535 } 1536 1537 while (sa->rxq_count < nb_rx_queues) { 1538 rc = sfc_rx_qinit_info(sa, sa->rxq_count); 1539 if (rc != 0) 1540 goto fail_rx_qinit_info; 1541 1542 sa->rxq_count++; 1543 } 1544 1545 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ? 1546 MIN(sa->rxq_count, EFX_MAXRSS) : 0; 1547 1548 if (rss->channels > 0) { 1549 struct rte_eth_rss_conf *adv_conf_rss; 1550 unsigned int sw_index; 1551 1552 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1553 rss->tbl[sw_index] = sw_index % rss->channels; 1554 1555 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1556 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1557 if (rc != 0) 1558 goto fail_rx_process_adv_conf_rss; 1559 } 1560 1561 done: 1562 return 0; 1563 1564 fail_rx_process_adv_conf_rss: 1565 fail_rx_qinit_info: 1566 fail_rxqs_realloc: 1567 fail_rxqs_alloc: 1568 sfc_rx_close(sa); 1569 1570 fail_check_mode: 1571 sfc_log_init(sa, "failed %d", rc); 1572 return rc; 1573 } 1574 1575 /** 1576 * Shutdown Rx subsystem. 1577 * 1578 * Called at device close stage, for example, before device shutdown. 1579 */ 1580 void 1581 sfc_rx_close(struct sfc_adapter *sa) 1582 { 1583 struct sfc_rss *rss = &sa->rss; 1584 1585 sfc_rx_fini_queues(sa, 0); 1586 1587 rss->channels = 0; 1588 1589 rte_free(sa->rxq_info); 1590 sa->rxq_info = NULL; 1591 } 1592