1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016-2018 Solarflare Communications Inc. 4 * All rights reserved. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_log.h" 17 #include "sfc_ev.h" 18 #include "sfc_rx.h" 19 #include "sfc_kvargs.h" 20 #include "sfc_tweak.h" 21 22 /* 23 * Maximum number of Rx queue flush attempt in the case of failure or 24 * flush timeout 25 */ 26 #define SFC_RX_QFLUSH_ATTEMPTS (3) 27 28 /* 29 * Time to wait between event queue polling attempts when waiting for Rx 30 * queue flush done or failed events. 31 */ 32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 33 34 /* 35 * Maximum number of event queue polling attempts when waiting for Rx queue 36 * flush done or failed events. It defines Rx queue flush attempt timeout 37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 38 */ 39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 40 41 void 42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info) 43 { 44 rxq_info->state |= SFC_RXQ_FLUSHED; 45 rxq_info->state &= ~SFC_RXQ_FLUSHING; 46 } 47 48 void 49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info) 50 { 51 rxq_info->state |= SFC_RXQ_FLUSH_FAILED; 52 rxq_info->state &= ~SFC_RXQ_FLUSHING; 53 } 54 55 static int 56 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq) 57 { 58 int rc = 0; 59 60 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) { 61 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr); 62 if (rc == 0) 63 rxq->evq->read_ptr_primed = rxq->evq->read_ptr; 64 } 65 return rc; 66 } 67 68 static void 69 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 70 { 71 unsigned int free_space; 72 unsigned int bulks; 73 void *objs[SFC_RX_REFILL_BULK]; 74 efsys_dma_addr_t addr[RTE_DIM(objs)]; 75 unsigned int added = rxq->added; 76 unsigned int id; 77 unsigned int i; 78 struct sfc_efx_rx_sw_desc *rxd; 79 struct rte_mbuf *m; 80 uint16_t port_id = rxq->dp.dpq.port_id; 81 82 free_space = rxq->max_fill_level - (added - rxq->completed); 83 84 if (free_space < rxq->refill_threshold) 85 return; 86 87 bulks = free_space / RTE_DIM(objs); 88 /* refill_threshold guarantees that bulks is positive */ 89 SFC_ASSERT(bulks > 0); 90 91 id = added & rxq->ptr_mask; 92 do { 93 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 94 RTE_DIM(objs)) < 0)) { 95 /* 96 * It is hardly a safe way to increment counter 97 * from different contexts, but all PMDs do it. 98 */ 99 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 100 RTE_DIM(objs); 101 /* Return if we have posted nothing yet */ 102 if (added == rxq->added) 103 return; 104 /* Push posted */ 105 break; 106 } 107 108 for (i = 0; i < RTE_DIM(objs); 109 ++i, id = (id + 1) & rxq->ptr_mask) { 110 m = objs[i]; 111 112 MBUF_RAW_ALLOC_CHECK(m); 113 114 rxd = &rxq->sw_desc[id]; 115 rxd->mbuf = m; 116 117 m->data_off = RTE_PKTMBUF_HEADROOM; 118 m->port = port_id; 119 120 addr[i] = rte_pktmbuf_iova(m); 121 } 122 123 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 124 RTE_DIM(objs), rxq->completed, added); 125 added += RTE_DIM(objs); 126 } while (--bulks > 0); 127 128 SFC_ASSERT(added != rxq->added); 129 rxq->added = added; 130 efx_rx_qpush(rxq->common, added, &rxq->pushed); 131 } 132 133 static uint64_t 134 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 135 { 136 uint64_t mbuf_flags = 0; 137 138 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 139 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 140 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; 141 break; 142 case EFX_PKT_IPV4: 143 mbuf_flags |= PKT_RX_IP_CKSUM_BAD; 144 break; 145 default: 146 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0); 147 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) == 148 PKT_RX_IP_CKSUM_UNKNOWN); 149 break; 150 } 151 152 switch ((desc_flags & 153 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 154 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 155 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 156 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; 157 break; 158 case EFX_PKT_TCP: 159 case EFX_PKT_UDP: 160 mbuf_flags |= PKT_RX_L4_CKSUM_BAD; 161 break; 162 default: 163 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0); 164 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) == 165 PKT_RX_L4_CKSUM_UNKNOWN); 166 break; 167 } 168 169 return mbuf_flags; 170 } 171 172 static uint32_t 173 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 174 { 175 return RTE_PTYPE_L2_ETHER | 176 ((desc_flags & EFX_PKT_IPV4) ? 177 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 178 ((desc_flags & EFX_PKT_IPV6) ? 179 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 180 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 181 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 182 } 183 184 static const uint32_t * 185 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps) 186 { 187 static const uint32_t ptypes[] = { 188 RTE_PTYPE_L2_ETHER, 189 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 190 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 191 RTE_PTYPE_L4_TCP, 192 RTE_PTYPE_L4_UDP, 193 RTE_PTYPE_UNKNOWN 194 }; 195 196 return ptypes; 197 } 198 199 static void 200 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 201 struct rte_mbuf *m) 202 { 203 uint8_t *mbuf_data; 204 205 206 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 207 return; 208 209 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 210 211 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 212 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 213 EFX_RX_HASHALG_TOEPLITZ, 214 mbuf_data); 215 216 m->ol_flags |= PKT_RX_RSS_HASH; 217 } 218 } 219 220 static uint16_t 221 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 222 { 223 struct sfc_dp_rxq *dp_rxq = rx_queue; 224 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 225 unsigned int completed; 226 unsigned int prefix_size = rxq->prefix_size; 227 unsigned int done_pkts = 0; 228 boolean_t discard_next = B_FALSE; 229 struct rte_mbuf *scatter_pkt = NULL; 230 231 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 232 return 0; 233 234 sfc_ev_qpoll(rxq->evq); 235 236 completed = rxq->completed; 237 while (completed != rxq->pending && done_pkts < nb_pkts) { 238 unsigned int id; 239 struct sfc_efx_rx_sw_desc *rxd; 240 struct rte_mbuf *m; 241 unsigned int seg_len; 242 unsigned int desc_flags; 243 244 id = completed++ & rxq->ptr_mask; 245 rxd = &rxq->sw_desc[id]; 246 m = rxd->mbuf; 247 desc_flags = rxd->flags; 248 249 if (discard_next) 250 goto discard; 251 252 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 253 goto discard; 254 255 if (desc_flags & EFX_PKT_PREFIX_LEN) { 256 uint16_t tmp_size; 257 int rc __rte_unused; 258 259 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 260 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 261 SFC_ASSERT(rc == 0); 262 seg_len = tmp_size; 263 } else { 264 seg_len = rxd->size - prefix_size; 265 } 266 267 rte_pktmbuf_data_len(m) = seg_len; 268 rte_pktmbuf_pkt_len(m) = seg_len; 269 270 if (scatter_pkt != NULL) { 271 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 272 rte_pktmbuf_free(scatter_pkt); 273 goto discard; 274 } 275 /* The packet to deliver */ 276 m = scatter_pkt; 277 } 278 279 if (desc_flags & EFX_PKT_CONT) { 280 /* The packet is scattered, more fragments to come */ 281 scatter_pkt = m; 282 /* Further fragments have no prefix */ 283 prefix_size = 0; 284 continue; 285 } 286 287 /* Scattered packet is done */ 288 scatter_pkt = NULL; 289 /* The first fragment of the packet has prefix */ 290 prefix_size = rxq->prefix_size; 291 292 m->ol_flags = 293 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 294 m->packet_type = 295 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 296 297 /* 298 * Extract RSS hash from the packet prefix and 299 * set the corresponding field (if needed and possible) 300 */ 301 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 302 303 m->data_off += prefix_size; 304 305 *rx_pkts++ = m; 306 done_pkts++; 307 continue; 308 309 discard: 310 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 311 rte_mbuf_raw_free(m); 312 rxd->mbuf = NULL; 313 } 314 315 /* pending is only moved when entire packet is received */ 316 SFC_ASSERT(scatter_pkt == NULL); 317 318 rxq->completed = completed; 319 320 sfc_efx_rx_qrefill(rxq); 321 322 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) 323 sfc_efx_rx_qprime(rxq); 324 325 return done_pkts; 326 } 327 328 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 329 static unsigned int 330 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 331 { 332 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 333 334 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 335 return 0; 336 337 sfc_ev_qpoll(rxq->evq); 338 339 return rxq->pending - rxq->completed; 340 } 341 342 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 343 static int 344 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 345 { 346 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 347 348 if (unlikely(offset > rxq->ptr_mask)) 349 return -EINVAL; 350 351 /* 352 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 353 * it is required for the queue to be running, but the 354 * check is omitted because API design assumes that it 355 * is the duty of the caller to satisfy all conditions 356 */ 357 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 358 SFC_EFX_RXQ_FLAG_RUNNING); 359 sfc_ev_qpoll(rxq->evq); 360 361 /* 362 * There is a handful of reserved entries in the ring, 363 * but an explicit check whether the offset points to 364 * a reserved entry is neglected since the two checks 365 * below rely on the figures which take the HW limits 366 * into account and thus if an entry is reserved, the 367 * checks will fail and UNAVAIL code will be returned 368 */ 369 370 if (offset < (rxq->pending - rxq->completed)) 371 return RTE_ETH_RX_DESC_DONE; 372 373 if (offset < (rxq->added - rxq->completed)) 374 return RTE_ETH_RX_DESC_AVAIL; 375 376 return RTE_ETH_RX_DESC_UNAVAIL; 377 } 378 379 boolean_t 380 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size, 381 boolean_t rx_scatter_enabled, const char **error) 382 { 383 if ((rx_buf_size < pdu + rx_prefix_size) && !rx_scatter_enabled) { 384 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small"; 385 return B_FALSE; 386 } 387 388 return B_TRUE; 389 } 390 391 /** Get Rx datapath ops by the datapath RxQ handle */ 392 const struct sfc_dp_rx * 393 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 394 { 395 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 396 struct rte_eth_dev *eth_dev; 397 struct sfc_adapter_priv *sap; 398 399 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 400 eth_dev = &rte_eth_devices[dpq->port_id]; 401 402 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 403 404 return sap->dp_rx; 405 } 406 407 struct sfc_rxq_info * 408 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 409 { 410 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 411 struct rte_eth_dev *eth_dev; 412 struct sfc_adapter_shared *sas; 413 414 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 415 eth_dev = &rte_eth_devices[dpq->port_id]; 416 417 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 418 419 SFC_ASSERT(dpq->queue_id < sas->rxq_count); 420 return &sas->rxq_info[dpq->queue_id]; 421 } 422 423 struct sfc_rxq * 424 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 425 { 426 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 427 struct rte_eth_dev *eth_dev; 428 struct sfc_adapter *sa; 429 430 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 431 eth_dev = &rte_eth_devices[dpq->port_id]; 432 433 sa = sfc_adapter_by_eth_dev(eth_dev); 434 435 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count); 436 return &sa->rxq_ctrl[dpq->queue_id]; 437 } 438 439 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 440 static int 441 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 442 __rte_unused struct sfc_dp_rx_hw_limits *limits, 443 __rte_unused struct rte_mempool *mb_pool, 444 unsigned int *rxq_entries, 445 unsigned int *evq_entries, 446 unsigned int *rxq_max_fill_level) 447 { 448 *rxq_entries = nb_rx_desc; 449 *evq_entries = nb_rx_desc; 450 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 451 return 0; 452 } 453 454 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 455 static int 456 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 457 const struct rte_pci_addr *pci_addr, int socket_id, 458 const struct sfc_dp_rx_qcreate_info *info, 459 struct sfc_dp_rxq **dp_rxqp) 460 { 461 struct sfc_efx_rxq *rxq; 462 int rc; 463 464 rc = ENOMEM; 465 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 466 RTE_CACHE_LINE_SIZE, socket_id); 467 if (rxq == NULL) 468 goto fail_rxq_alloc; 469 470 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 471 472 rc = ENOMEM; 473 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 474 info->rxq_entries, 475 sizeof(*rxq->sw_desc), 476 RTE_CACHE_LINE_SIZE, socket_id); 477 if (rxq->sw_desc == NULL) 478 goto fail_desc_alloc; 479 480 /* efx datapath is bound to efx control path */ 481 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 482 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 483 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 484 rxq->ptr_mask = info->rxq_entries - 1; 485 rxq->batch_max = info->batch_max; 486 rxq->prefix_size = info->prefix_size; 487 rxq->max_fill_level = info->max_fill_level; 488 rxq->refill_threshold = info->refill_threshold; 489 rxq->buf_size = info->buf_size; 490 rxq->refill_mb_pool = info->refill_mb_pool; 491 492 *dp_rxqp = &rxq->dp; 493 return 0; 494 495 fail_desc_alloc: 496 rte_free(rxq); 497 498 fail_rxq_alloc: 499 return rc; 500 } 501 502 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 503 static void 504 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 505 { 506 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 507 508 rte_free(rxq->sw_desc); 509 rte_free(rxq); 510 } 511 512 513 /* Use qstop and qstart functions in the case of qstart failure */ 514 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 515 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 516 517 518 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 519 static int 520 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 521 __rte_unused unsigned int evq_read_ptr) 522 { 523 /* libefx-based datapath is specific to libefx-based PMD */ 524 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 525 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 526 int rc; 527 528 rxq->common = crxq->common; 529 530 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 531 532 sfc_efx_rx_qrefill(rxq); 533 534 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 535 536 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) { 537 rc = sfc_efx_rx_qprime(rxq); 538 if (rc != 0) 539 goto fail_rx_qprime; 540 } 541 542 return 0; 543 544 fail_rx_qprime: 545 sfc_efx_rx_qstop(dp_rxq, NULL); 546 sfc_efx_rx_qpurge(dp_rxq); 547 return rc; 548 } 549 550 static void 551 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 552 __rte_unused unsigned int *evq_read_ptr) 553 { 554 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 555 556 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 557 558 /* libefx-based datapath is bound to libefx-based PMD and uses 559 * event queue structure directly. So, there is no necessity to 560 * return EvQ read pointer. 561 */ 562 } 563 564 static void 565 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 566 { 567 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 568 unsigned int i; 569 struct sfc_efx_rx_sw_desc *rxd; 570 571 for (i = rxq->completed; i != rxq->added; ++i) { 572 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 573 rte_mbuf_raw_free(rxd->mbuf); 574 rxd->mbuf = NULL; 575 /* Packed stream relies on 0 in inactive SW desc. 576 * Rx queue stop is not performance critical, so 577 * there is no harm to do it always. 578 */ 579 rxd->flags = 0; 580 rxd->size = 0; 581 } 582 583 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 584 } 585 586 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable; 587 static int 588 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq) 589 { 590 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 591 int rc = 0; 592 593 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN; 594 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) { 595 rc = sfc_efx_rx_qprime(rxq); 596 if (rc != 0) 597 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 598 } 599 return rc; 600 } 601 602 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable; 603 static int 604 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq) 605 { 606 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 607 608 /* Cannot disarm, just disable rearm */ 609 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 610 return 0; 611 } 612 613 struct sfc_dp_rx sfc_efx_rx = { 614 .dp = { 615 .name = SFC_KVARG_DATAPATH_EFX, 616 .type = SFC_DP_RX, 617 .hw_fw_caps = 0, 618 }, 619 .features = SFC_DP_RX_FEAT_INTR, 620 .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM | 621 DEV_RX_OFFLOAD_RSS_HASH, 622 .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER, 623 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 624 .qcreate = sfc_efx_rx_qcreate, 625 .qdestroy = sfc_efx_rx_qdestroy, 626 .qstart = sfc_efx_rx_qstart, 627 .qstop = sfc_efx_rx_qstop, 628 .qpurge = sfc_efx_rx_qpurge, 629 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 630 .qdesc_npending = sfc_efx_rx_qdesc_npending, 631 .qdesc_status = sfc_efx_rx_qdesc_status, 632 .intr_enable = sfc_efx_rx_intr_enable, 633 .intr_disable = sfc_efx_rx_intr_disable, 634 .pkt_burst = sfc_efx_recv_pkts, 635 }; 636 637 static void 638 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index) 639 { 640 struct sfc_rxq_info *rxq_info; 641 struct sfc_rxq *rxq; 642 unsigned int retry_count; 643 unsigned int wait_count; 644 int rc; 645 646 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 647 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 648 649 rxq = &sa->rxq_ctrl[sw_index]; 650 651 /* 652 * Retry Rx queue flushing in the case of flush failed or 653 * timeout. In the worst case it can delay for 6 seconds. 654 */ 655 for (retry_count = 0; 656 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) && 657 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 658 ++retry_count) { 659 rc = efx_rx_qflush(rxq->common); 660 if (rc != 0) { 661 rxq_info->state |= (rc == EALREADY) ? 662 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 663 break; 664 } 665 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED; 666 rxq_info->state |= SFC_RXQ_FLUSHING; 667 668 /* 669 * Wait for Rx queue flush done or failed event at least 670 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 671 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 672 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 673 */ 674 wait_count = 0; 675 do { 676 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 677 sfc_ev_qpoll(rxq->evq); 678 } while ((rxq_info->state & SFC_RXQ_FLUSHING) && 679 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 680 681 if (rxq_info->state & SFC_RXQ_FLUSHING) 682 sfc_err(sa, "RxQ %u flush timed out", sw_index); 683 684 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED) 685 sfc_err(sa, "RxQ %u flush failed", sw_index); 686 687 if (rxq_info->state & SFC_RXQ_FLUSHED) 688 sfc_notice(sa, "RxQ %u flushed", sw_index); 689 } 690 691 sa->priv.dp_rx->qpurge(rxq_info->dp); 692 } 693 694 static int 695 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 696 { 697 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 698 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 699 struct sfc_port *port = &sa->port; 700 int rc; 701 702 /* 703 * If promiscuous or all-multicast mode has been requested, setting 704 * filter for the default Rx queue might fail, in particular, while 705 * running over PCI function which is not a member of corresponding 706 * privilege groups; if this occurs, few iterations will be made to 707 * repeat this step without promiscuous and all-multicast flags set 708 */ 709 retry: 710 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 711 if (rc == 0) 712 return 0; 713 else if (rc != EOPNOTSUPP) 714 return rc; 715 716 if (port->promisc) { 717 sfc_warn(sa, "promiscuous mode has been requested, " 718 "but the HW rejects it"); 719 sfc_warn(sa, "promiscuous mode will be disabled"); 720 721 port->promisc = B_FALSE; 722 rc = sfc_set_rx_mode(sa); 723 if (rc != 0) 724 return rc; 725 726 goto retry; 727 } 728 729 if (port->allmulti) { 730 sfc_warn(sa, "all-multicast mode has been requested, " 731 "but the HW rejects it"); 732 sfc_warn(sa, "all-multicast mode will be disabled"); 733 734 port->allmulti = B_FALSE; 735 rc = sfc_set_rx_mode(sa); 736 if (rc != 0) 737 return rc; 738 739 goto retry; 740 } 741 742 return rc; 743 } 744 745 int 746 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 747 { 748 struct sfc_rxq_info *rxq_info; 749 struct sfc_rxq *rxq; 750 struct sfc_evq *evq; 751 int rc; 752 753 sfc_log_init(sa, "sw_index=%u", sw_index); 754 755 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 756 757 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 758 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 759 760 rxq = &sa->rxq_ctrl[sw_index]; 761 evq = rxq->evq; 762 763 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index)); 764 if (rc != 0) 765 goto fail_ev_qstart; 766 767 switch (rxq_info->type) { 768 case EFX_RXQ_TYPE_DEFAULT: 769 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 770 rxq->buf_size, 771 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 772 rxq_info->type_flags, evq->common, &rxq->common); 773 break; 774 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 775 struct rte_mempool *mp = rxq_info->refill_mb_pool; 776 struct rte_mempool_info mp_info; 777 778 rc = rte_mempool_ops_get_info(mp, &mp_info); 779 if (rc != 0) { 780 /* Positive errno is used in the driver */ 781 rc = -rc; 782 goto fail_mp_get_info; 783 } 784 if (mp_info.contig_block_size <= 0) { 785 rc = EINVAL; 786 goto fail_bad_contig_block_size; 787 } 788 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 789 mp_info.contig_block_size, rxq->buf_size, 790 mp->header_size + mp->elt_size + mp->trailer_size, 791 sa->rxd_wait_timeout_ns, 792 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 793 evq->common, &rxq->common); 794 break; 795 } 796 default: 797 rc = ENOTSUP; 798 } 799 if (rc != 0) 800 goto fail_rx_qcreate; 801 802 efx_rx_qenable(rxq->common); 803 804 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr); 805 if (rc != 0) 806 goto fail_dp_qstart; 807 808 rxq_info->state |= SFC_RXQ_STARTED; 809 810 if (sw_index == 0 && !sfc_sa2shared(sa)->isolated) { 811 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 812 if (rc != 0) 813 goto fail_mac_filter_default_rxq_set; 814 } 815 816 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 817 sa->eth_dev->data->rx_queue_state[sw_index] = 818 RTE_ETH_QUEUE_STATE_STARTED; 819 820 return 0; 821 822 fail_mac_filter_default_rxq_set: 823 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 824 825 fail_dp_qstart: 826 sfc_rx_qflush(sa, sw_index); 827 828 fail_rx_qcreate: 829 fail_bad_contig_block_size: 830 fail_mp_get_info: 831 sfc_ev_qstop(evq); 832 833 fail_ev_qstart: 834 return rc; 835 } 836 837 void 838 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 839 { 840 struct sfc_rxq_info *rxq_info; 841 struct sfc_rxq *rxq; 842 843 sfc_log_init(sa, "sw_index=%u", sw_index); 844 845 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 846 847 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 848 849 if (rxq_info->state == SFC_RXQ_INITIALIZED) 850 return; 851 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 852 853 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 854 sa->eth_dev->data->rx_queue_state[sw_index] = 855 RTE_ETH_QUEUE_STATE_STOPPED; 856 857 rxq = &sa->rxq_ctrl[sw_index]; 858 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 859 860 if (sw_index == 0) 861 efx_mac_filter_default_rxq_clear(sa->nic); 862 863 sfc_rx_qflush(sa, sw_index); 864 865 rxq_info->state = SFC_RXQ_INITIALIZED; 866 867 efx_rx_qdestroy(rxq->common); 868 869 sfc_ev_qstop(rxq->evq); 870 } 871 872 static uint64_t 873 sfc_rx_get_offload_mask(struct sfc_adapter *sa) 874 { 875 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 876 uint64_t no_caps = 0; 877 878 if (encp->enc_tunnel_encapsulations_supported == 0) 879 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 880 881 return ~no_caps; 882 } 883 884 uint64_t 885 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 886 { 887 uint64_t caps = sa->priv.dp_rx->dev_offload_capa; 888 889 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME; 890 891 return caps & sfc_rx_get_offload_mask(sa); 892 } 893 894 uint64_t 895 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 896 { 897 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa); 898 } 899 900 static int 901 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 902 const struct rte_eth_rxconf *rx_conf, 903 __rte_unused uint64_t offloads) 904 { 905 int rc = 0; 906 907 if (rx_conf->rx_thresh.pthresh != 0 || 908 rx_conf->rx_thresh.hthresh != 0 || 909 rx_conf->rx_thresh.wthresh != 0) { 910 sfc_warn(sa, 911 "RxQ prefetch/host/writeback thresholds are not supported"); 912 } 913 914 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 915 sfc_err(sa, 916 "RxQ free threshold too large: %u vs maximum %u", 917 rx_conf->rx_free_thresh, rxq_max_fill_level); 918 rc = EINVAL; 919 } 920 921 if (rx_conf->rx_drop_en == 0) { 922 sfc_err(sa, "RxQ drop disable is not supported"); 923 rc = EINVAL; 924 } 925 926 return rc; 927 } 928 929 static unsigned int 930 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 931 { 932 uint32_t data_off; 933 uint32_t order; 934 935 /* The mbuf object itself is always cache line aligned */ 936 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 937 938 /* Data offset from mbuf object start */ 939 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 940 RTE_PKTMBUF_HEADROOM; 941 942 order = MIN(order, rte_bsf32(data_off)); 943 944 return 1u << order; 945 } 946 947 static uint16_t 948 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 949 { 950 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 951 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 952 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 953 uint16_t buf_size; 954 unsigned int buf_aligned; 955 unsigned int start_alignment; 956 unsigned int end_padding_alignment; 957 958 /* Below it is assumed that both alignments are power of 2 */ 959 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 960 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 961 962 /* 963 * mbuf is always cache line aligned, double-check 964 * that it meets rx buffer start alignment requirements. 965 */ 966 967 /* Start from mbuf pool data room size */ 968 buf_size = rte_pktmbuf_data_room_size(mb_pool); 969 970 /* Remove headroom */ 971 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 972 sfc_err(sa, 973 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 974 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 975 return 0; 976 } 977 buf_size -= RTE_PKTMBUF_HEADROOM; 978 979 /* Calculate guaranteed data start alignment */ 980 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 981 982 /* Reserve space for start alignment */ 983 if (buf_aligned < nic_align_start) { 984 start_alignment = nic_align_start - buf_aligned; 985 if (buf_size <= start_alignment) { 986 sfc_err(sa, 987 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 988 mb_pool->name, 989 rte_pktmbuf_data_room_size(mb_pool), 990 RTE_PKTMBUF_HEADROOM, start_alignment); 991 return 0; 992 } 993 buf_aligned = nic_align_start; 994 buf_size -= start_alignment; 995 } else { 996 start_alignment = 0; 997 } 998 999 /* Make sure that end padding does not write beyond the buffer */ 1000 if (buf_aligned < nic_align_end) { 1001 /* 1002 * Estimate space which can be lost. If guarnteed buffer 1003 * size is odd, lost space is (nic_align_end - 1). More 1004 * accurate formula is below. 1005 */ 1006 end_padding_alignment = nic_align_end - 1007 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 1008 if (buf_size <= end_padding_alignment) { 1009 sfc_err(sa, 1010 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 1011 mb_pool->name, 1012 rte_pktmbuf_data_room_size(mb_pool), 1013 RTE_PKTMBUF_HEADROOM, start_alignment, 1014 end_padding_alignment); 1015 return 0; 1016 } 1017 buf_size -= end_padding_alignment; 1018 } else { 1019 /* 1020 * Start is aligned the same or better than end, 1021 * just align length. 1022 */ 1023 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end); 1024 } 1025 1026 return buf_size; 1027 } 1028 1029 int 1030 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 1031 uint16_t nb_rx_desc, unsigned int socket_id, 1032 const struct rte_eth_rxconf *rx_conf, 1033 struct rte_mempool *mb_pool) 1034 { 1035 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1036 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1037 int rc; 1038 unsigned int rxq_entries; 1039 unsigned int evq_entries; 1040 unsigned int rxq_max_fill_level; 1041 uint64_t offloads; 1042 uint16_t buf_size; 1043 struct sfc_rxq_info *rxq_info; 1044 struct sfc_evq *evq; 1045 struct sfc_rxq *rxq; 1046 struct sfc_dp_rx_qcreate_info info; 1047 struct sfc_dp_rx_hw_limits hw_limits; 1048 uint16_t rx_free_thresh; 1049 const char *error; 1050 1051 memset(&hw_limits, 0, sizeof(hw_limits)); 1052 hw_limits.rxq_max_entries = sa->rxq_max_entries; 1053 hw_limits.rxq_min_entries = sa->rxq_min_entries; 1054 hw_limits.evq_max_entries = sa->evq_max_entries; 1055 hw_limits.evq_min_entries = sa->evq_min_entries; 1056 1057 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool, 1058 &rxq_entries, &evq_entries, 1059 &rxq_max_fill_level); 1060 if (rc != 0) 1061 goto fail_size_up_rings; 1062 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries); 1063 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries); 1064 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 1065 1066 offloads = rx_conf->offloads | 1067 sa->eth_dev->data->dev_conf.rxmode.offloads; 1068 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 1069 if (rc != 0) 1070 goto fail_bad_conf; 1071 1072 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 1073 if (buf_size == 0) { 1074 sfc_err(sa, "RxQ %u mbuf pool object size is too small", 1075 sw_index); 1076 rc = EINVAL; 1077 goto fail_bad_conf; 1078 } 1079 1080 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size, 1081 encp->enc_rx_prefix_size, 1082 (offloads & DEV_RX_OFFLOAD_SCATTER), 1083 &error)) { 1084 sfc_err(sa, "RxQ %u MTU check failed: %s", sw_index, error); 1085 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs " 1086 "PDU size %u plus Rx prefix %u bytes", 1087 sw_index, buf_size, (unsigned int)sa->port.pdu, 1088 encp->enc_rx_prefix_size); 1089 rc = EINVAL; 1090 goto fail_bad_conf; 1091 } 1092 1093 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1094 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1095 1096 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1097 rxq_info->entries = rxq_entries; 1098 1099 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1100 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1101 else 1102 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1103 1104 rxq_info->type_flags = 1105 (offloads & DEV_RX_OFFLOAD_SCATTER) ? 1106 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1107 1108 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1109 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) & 1110 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0) 1111 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1112 1113 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1114 evq_entries, socket_id, &evq); 1115 if (rc != 0) 1116 goto fail_ev_qinit; 1117 1118 rxq = &sa->rxq_ctrl[sw_index]; 1119 rxq->evq = evq; 1120 rxq->hw_index = sw_index; 1121 /* 1122 * If Rx refill threshold is specified (its value is non zero) in 1123 * Rx configuration, use specified value. Otherwise use 1/8 of 1124 * the Rx descriptors number as the default. It allows to keep 1125 * Rx ring full-enough and does not refill too aggressive if 1126 * packet rate is high. 1127 * 1128 * Since PMD refills in bulks waiting for full bulk may be 1129 * refilled (basically round down), it is better to round up 1130 * here to mitigate it a bit. 1131 */ 1132 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ? 1133 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8); 1134 /* Rx refill threshold cannot be smaller than refill bulk */ 1135 rxq_info->refill_threshold = 1136 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK); 1137 rxq_info->refill_mb_pool = mb_pool; 1138 rxq->buf_size = buf_size; 1139 1140 rc = sfc_dma_alloc(sa, "rxq", sw_index, 1141 efx_rxq_size(sa->nic, rxq_info->entries), 1142 socket_id, &rxq->mem); 1143 if (rc != 0) 1144 goto fail_dma_alloc; 1145 1146 memset(&info, 0, sizeof(info)); 1147 info.refill_mb_pool = rxq_info->refill_mb_pool; 1148 info.max_fill_level = rxq_max_fill_level; 1149 info.refill_threshold = rxq_info->refill_threshold; 1150 info.buf_size = buf_size; 1151 info.batch_max = encp->enc_rx_batch_max; 1152 info.prefix_size = encp->enc_rx_prefix_size; 1153 1154 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0) 1155 info.flags |= SFC_RXQ_FLAG_RSS_HASH; 1156 1157 info.rxq_entries = rxq_info->entries; 1158 info.rxq_hw_ring = rxq->mem.esm_base; 1159 info.evq_hw_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index); 1160 info.evq_entries = evq_entries; 1161 info.evq_hw_ring = evq->mem.esm_base; 1162 info.hw_index = rxq->hw_index; 1163 info.mem_bar = sa->mem_bar.esb_base; 1164 info.vi_window_shift = encp->enc_vi_window_shift; 1165 1166 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1167 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1168 socket_id, &info, &rxq_info->dp); 1169 if (rc != 0) 1170 goto fail_dp_rx_qcreate; 1171 1172 evq->dp_rxq = rxq_info->dp; 1173 1174 rxq_info->state = SFC_RXQ_INITIALIZED; 1175 1176 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1177 1178 return 0; 1179 1180 fail_dp_rx_qcreate: 1181 sfc_dma_free(sa, &rxq->mem); 1182 1183 fail_dma_alloc: 1184 sfc_ev_qfini(evq); 1185 1186 fail_ev_qinit: 1187 rxq_info->entries = 0; 1188 1189 fail_bad_conf: 1190 fail_size_up_rings: 1191 sfc_log_init(sa, "failed %d", rc); 1192 return rc; 1193 } 1194 1195 void 1196 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 1197 { 1198 struct sfc_rxq_info *rxq_info; 1199 struct sfc_rxq *rxq; 1200 1201 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1202 sa->eth_dev->data->rx_queues[sw_index] = NULL; 1203 1204 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1205 1206 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 1207 1208 sa->priv.dp_rx->qdestroy(rxq_info->dp); 1209 rxq_info->dp = NULL; 1210 1211 rxq_info->state &= ~SFC_RXQ_INITIALIZED; 1212 rxq_info->entries = 0; 1213 1214 rxq = &sa->rxq_ctrl[sw_index]; 1215 1216 sfc_dma_free(sa, &rxq->mem); 1217 1218 sfc_ev_qfini(rxq->evq); 1219 rxq->evq = NULL; 1220 } 1221 1222 /* 1223 * Mapping between RTE RSS hash functions and their EFX counterparts. 1224 */ 1225 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1226 { ETH_RSS_NONFRAG_IPV4_TCP, 1227 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1228 { ETH_RSS_NONFRAG_IPV4_UDP, 1229 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1230 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX, 1231 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1232 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX, 1233 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1234 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER, 1235 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1236 EFX_RX_HASH(IPV4, 2TUPLE) }, 1237 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER | 1238 ETH_RSS_IPV6_EX, 1239 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1240 EFX_RX_HASH(IPV6, 2TUPLE) } 1241 }; 1242 1243 static efx_rx_hash_type_t 1244 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1245 unsigned int *hash_type_flags_supported, 1246 unsigned int nb_hash_type_flags_supported) 1247 { 1248 efx_rx_hash_type_t hash_type_masked = 0; 1249 unsigned int i, j; 1250 1251 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1252 unsigned int class_tuple_lbn[] = { 1253 EFX_RX_CLASS_IPV4_TCP_LBN, 1254 EFX_RX_CLASS_IPV4_UDP_LBN, 1255 EFX_RX_CLASS_IPV4_LBN, 1256 EFX_RX_CLASS_IPV6_TCP_LBN, 1257 EFX_RX_CLASS_IPV6_UDP_LBN, 1258 EFX_RX_CLASS_IPV6_LBN 1259 }; 1260 1261 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1262 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1263 unsigned int flag; 1264 1265 tuple_mask <<= class_tuple_lbn[j]; 1266 flag = hash_type & tuple_mask; 1267 1268 if (flag == hash_type_flags_supported[i]) 1269 hash_type_masked |= flag; 1270 } 1271 } 1272 1273 return hash_type_masked; 1274 } 1275 1276 int 1277 sfc_rx_hash_init(struct sfc_adapter *sa) 1278 { 1279 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1280 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1281 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1282 efx_rx_hash_alg_t alg; 1283 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1284 unsigned int nb_flags_supp; 1285 struct sfc_rss_hf_rte_to_efx *hf_map; 1286 struct sfc_rss_hf_rte_to_efx *entry; 1287 efx_rx_hash_type_t efx_hash_types; 1288 unsigned int i; 1289 int rc; 1290 1291 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1292 alg = EFX_RX_HASHALG_TOEPLITZ; 1293 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1294 alg = EFX_RX_HASHALG_PACKED_STREAM; 1295 else 1296 return EINVAL; 1297 1298 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1299 RTE_DIM(flags_supp), &nb_flags_supp); 1300 if (rc != 0) 1301 return rc; 1302 1303 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1304 RTE_DIM(sfc_rss_hf_map), 1305 sizeof(*hf_map), 0, sa->socket_id); 1306 if (hf_map == NULL) 1307 return ENOMEM; 1308 1309 entry = hf_map; 1310 efx_hash_types = 0; 1311 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1312 efx_rx_hash_type_t ht; 1313 1314 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1315 flags_supp, nb_flags_supp); 1316 if (ht != 0) { 1317 entry->rte = sfc_rss_hf_map[i].rte; 1318 entry->efx = ht; 1319 efx_hash_types |= ht; 1320 ++entry; 1321 } 1322 } 1323 1324 rss->hash_alg = alg; 1325 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1326 rss->hf_map = hf_map; 1327 rss->hash_types = efx_hash_types; 1328 1329 return 0; 1330 } 1331 1332 void 1333 sfc_rx_hash_fini(struct sfc_adapter *sa) 1334 { 1335 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1336 1337 rte_free(rss->hf_map); 1338 } 1339 1340 int 1341 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1342 efx_rx_hash_type_t *efx) 1343 { 1344 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1345 efx_rx_hash_type_t hash_types = 0; 1346 unsigned int i; 1347 1348 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1349 uint64_t rte_mask = rss->hf_map[i].rte; 1350 1351 if ((rte & rte_mask) != 0) { 1352 rte &= ~rte_mask; 1353 hash_types |= rss->hf_map[i].efx; 1354 } 1355 } 1356 1357 if (rte != 0) { 1358 sfc_err(sa, "unsupported hash functions requested"); 1359 return EINVAL; 1360 } 1361 1362 *efx = hash_types; 1363 1364 return 0; 1365 } 1366 1367 uint64_t 1368 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx) 1369 { 1370 uint64_t rte = 0; 1371 unsigned int i; 1372 1373 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1374 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1375 1376 if ((efx & hash_type) == hash_type) 1377 rte |= rss->hf_map[i].rte; 1378 } 1379 1380 return rte; 1381 } 1382 1383 static int 1384 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1385 struct rte_eth_rss_conf *conf) 1386 { 1387 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1388 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1389 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types); 1390 int rc; 1391 1392 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1393 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1394 conf->rss_key != NULL) 1395 return EINVAL; 1396 } 1397 1398 if (conf->rss_hf != 0) { 1399 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1400 if (rc != 0) 1401 return rc; 1402 } 1403 1404 if (conf->rss_key != NULL) { 1405 if (conf->rss_key_len != sizeof(rss->key)) { 1406 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1407 sizeof(rss->key)); 1408 return EINVAL; 1409 } 1410 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1411 } 1412 1413 rss->hash_types = efx_hash_types; 1414 1415 return 0; 1416 } 1417 1418 static int 1419 sfc_rx_rss_config(struct sfc_adapter *sa) 1420 { 1421 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1422 int rc = 0; 1423 1424 if (rss->channels > 0) { 1425 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1426 rss->hash_alg, rss->hash_types, 1427 B_TRUE); 1428 if (rc != 0) 1429 goto finish; 1430 1431 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1432 rss->key, sizeof(rss->key)); 1433 if (rc != 0) 1434 goto finish; 1435 1436 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1437 rss->tbl, RTE_DIM(rss->tbl)); 1438 } 1439 1440 finish: 1441 return rc; 1442 } 1443 1444 int 1445 sfc_rx_start(struct sfc_adapter *sa) 1446 { 1447 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1448 unsigned int sw_index; 1449 int rc; 1450 1451 sfc_log_init(sa, "rxq_count=%u", sas->rxq_count); 1452 1453 rc = efx_rx_init(sa->nic); 1454 if (rc != 0) 1455 goto fail_rx_init; 1456 1457 rc = sfc_rx_rss_config(sa); 1458 if (rc != 0) 1459 goto fail_rss_config; 1460 1461 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) { 1462 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED && 1463 (!sas->rxq_info[sw_index].deferred_start || 1464 sas->rxq_info[sw_index].deferred_started)) { 1465 rc = sfc_rx_qstart(sa, sw_index); 1466 if (rc != 0) 1467 goto fail_rx_qstart; 1468 } 1469 } 1470 1471 return 0; 1472 1473 fail_rx_qstart: 1474 while (sw_index-- > 0) 1475 sfc_rx_qstop(sa, sw_index); 1476 1477 fail_rss_config: 1478 efx_rx_fini(sa->nic); 1479 1480 fail_rx_init: 1481 sfc_log_init(sa, "failed %d", rc); 1482 return rc; 1483 } 1484 1485 void 1486 sfc_rx_stop(struct sfc_adapter *sa) 1487 { 1488 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1489 unsigned int sw_index; 1490 1491 sfc_log_init(sa, "rxq_count=%u", sas->rxq_count); 1492 1493 sw_index = sas->rxq_count; 1494 while (sw_index-- > 0) { 1495 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED) 1496 sfc_rx_qstop(sa, sw_index); 1497 } 1498 1499 efx_rx_fini(sa->nic); 1500 } 1501 1502 static int 1503 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 1504 { 1505 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1506 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index]; 1507 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1508 unsigned int max_entries; 1509 1510 max_entries = encp->enc_rxq_max_ndescs; 1511 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1512 1513 rxq_info->max_entries = max_entries; 1514 1515 return 0; 1516 } 1517 1518 static int 1519 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1520 { 1521 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1522 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1523 sfc_rx_get_queue_offload_caps(sa); 1524 struct sfc_rss *rss = &sas->rss; 1525 int rc = 0; 1526 1527 switch (rxmode->mq_mode) { 1528 case ETH_MQ_RX_NONE: 1529 /* No special checks are required */ 1530 break; 1531 case ETH_MQ_RX_RSS: 1532 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1533 sfc_err(sa, "RSS is not available"); 1534 rc = EINVAL; 1535 } 1536 break; 1537 default: 1538 sfc_err(sa, "Rx multi-queue mode %u not supported", 1539 rxmode->mq_mode); 1540 rc = EINVAL; 1541 } 1542 1543 /* 1544 * Requested offloads are validated against supported by ethdev, 1545 * so unsupported offloads cannot be added as the result of 1546 * below check. 1547 */ 1548 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) != 1549 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) { 1550 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1551 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM; 1552 } 1553 1554 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1555 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1556 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1557 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1558 } 1559 1560 if ((offloads_supported & DEV_RX_OFFLOAD_RSS_HASH) && 1561 (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)) 1562 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1563 1564 return rc; 1565 } 1566 1567 /** 1568 * Destroy excess queues that are no longer needed after reconfiguration 1569 * or complete close. 1570 */ 1571 static void 1572 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1573 { 1574 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1575 int sw_index; 1576 1577 SFC_ASSERT(nb_rx_queues <= sas->rxq_count); 1578 1579 sw_index = sas->rxq_count; 1580 while (--sw_index >= (int)nb_rx_queues) { 1581 if (sas->rxq_info[sw_index].state & SFC_RXQ_INITIALIZED) 1582 sfc_rx_qfini(sa, sw_index); 1583 } 1584 1585 sas->rxq_count = nb_rx_queues; 1586 } 1587 1588 /** 1589 * Initialize Rx subsystem. 1590 * 1591 * Called at device (re)configuration stage when number of receive queues is 1592 * specified together with other device level receive configuration. 1593 * 1594 * It should be used to allocate NUMA-unaware resources. 1595 */ 1596 int 1597 sfc_rx_configure(struct sfc_adapter *sa) 1598 { 1599 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1600 struct sfc_rss *rss = &sas->rss; 1601 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1602 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1603 int rc; 1604 1605 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1606 nb_rx_queues, sas->rxq_count); 1607 1608 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1609 if (rc != 0) 1610 goto fail_check_mode; 1611 1612 if (nb_rx_queues == sas->rxq_count) 1613 goto configure_rss; 1614 1615 if (sas->rxq_info == NULL) { 1616 rc = ENOMEM; 1617 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues, 1618 sizeof(sas->rxq_info[0]), 0, 1619 sa->socket_id); 1620 if (sas->rxq_info == NULL) 1621 goto fail_rxqs_alloc; 1622 1623 /* 1624 * Allocate primary process only RxQ control from heap 1625 * since it should not be shared. 1626 */ 1627 rc = ENOMEM; 1628 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0])); 1629 if (sa->rxq_ctrl == NULL) 1630 goto fail_rxqs_ctrl_alloc; 1631 } else { 1632 struct sfc_rxq_info *new_rxq_info; 1633 struct sfc_rxq *new_rxq_ctrl; 1634 1635 if (nb_rx_queues < sas->rxq_count) 1636 sfc_rx_fini_queues(sa, nb_rx_queues); 1637 1638 rc = ENOMEM; 1639 new_rxq_info = 1640 rte_realloc(sas->rxq_info, 1641 nb_rx_queues * sizeof(sas->rxq_info[0]), 0); 1642 if (new_rxq_info == NULL && nb_rx_queues > 0) 1643 goto fail_rxqs_realloc; 1644 1645 rc = ENOMEM; 1646 new_rxq_ctrl = realloc(sa->rxq_ctrl, 1647 nb_rx_queues * sizeof(sa->rxq_ctrl[0])); 1648 if (new_rxq_ctrl == NULL && nb_rx_queues > 0) 1649 goto fail_rxqs_ctrl_realloc; 1650 1651 sas->rxq_info = new_rxq_info; 1652 sa->rxq_ctrl = new_rxq_ctrl; 1653 if (nb_rx_queues > sas->rxq_count) { 1654 memset(&sas->rxq_info[sas->rxq_count], 0, 1655 (nb_rx_queues - sas->rxq_count) * 1656 sizeof(sas->rxq_info[0])); 1657 memset(&sa->rxq_ctrl[sas->rxq_count], 0, 1658 (nb_rx_queues - sas->rxq_count) * 1659 sizeof(sa->rxq_ctrl[0])); 1660 } 1661 } 1662 1663 while (sas->rxq_count < nb_rx_queues) { 1664 rc = sfc_rx_qinit_info(sa, sas->rxq_count); 1665 if (rc != 0) 1666 goto fail_rx_qinit_info; 1667 1668 sas->rxq_count++; 1669 } 1670 1671 configure_rss: 1672 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ? 1673 MIN(sas->rxq_count, EFX_MAXRSS) : 0; 1674 1675 if (rss->channels > 0) { 1676 struct rte_eth_rss_conf *adv_conf_rss; 1677 unsigned int sw_index; 1678 1679 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1680 rss->tbl[sw_index] = sw_index % rss->channels; 1681 1682 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1683 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1684 if (rc != 0) 1685 goto fail_rx_process_adv_conf_rss; 1686 } 1687 1688 return 0; 1689 1690 fail_rx_process_adv_conf_rss: 1691 fail_rx_qinit_info: 1692 fail_rxqs_ctrl_realloc: 1693 fail_rxqs_realloc: 1694 fail_rxqs_ctrl_alloc: 1695 fail_rxqs_alloc: 1696 sfc_rx_close(sa); 1697 1698 fail_check_mode: 1699 sfc_log_init(sa, "failed %d", rc); 1700 return rc; 1701 } 1702 1703 /** 1704 * Shutdown Rx subsystem. 1705 * 1706 * Called at device close stage, for example, before device shutdown. 1707 */ 1708 void 1709 sfc_rx_close(struct sfc_adapter *sa) 1710 { 1711 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1712 1713 sfc_rx_fini_queues(sa, 0); 1714 1715 rss->channels = 0; 1716 1717 free(sa->rxq_ctrl); 1718 sa->rxq_ctrl = NULL; 1719 1720 rte_free(sfc_sa2shared(sa)->rxq_info); 1721 sfc_sa2shared(sa)->rxq_info = NULL; 1722 } 1723