1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016-2018 Solarflare Communications Inc. 4 * All rights reserved. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_log.h" 17 #include "sfc_ev.h" 18 #include "sfc_rx.h" 19 #include "sfc_kvargs.h" 20 #include "sfc_tweak.h" 21 22 /* 23 * Maximum number of Rx queue flush attempt in the case of failure or 24 * flush timeout 25 */ 26 #define SFC_RX_QFLUSH_ATTEMPTS (3) 27 28 /* 29 * Time to wait between event queue polling attempts when waiting for Rx 30 * queue flush done or failed events. 31 */ 32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 33 34 /* 35 * Maximum number of event queue polling attempts when waiting for Rx queue 36 * flush done or failed events. It defines Rx queue flush attempt timeout 37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 38 */ 39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 40 41 void 42 sfc_rx_qflush_done(struct sfc_rxq *rxq) 43 { 44 rxq->state |= SFC_RXQ_FLUSHED; 45 rxq->state &= ~SFC_RXQ_FLUSHING; 46 } 47 48 void 49 sfc_rx_qflush_failed(struct sfc_rxq *rxq) 50 { 51 rxq->state |= SFC_RXQ_FLUSH_FAILED; 52 rxq->state &= ~SFC_RXQ_FLUSHING; 53 } 54 55 static void 56 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 57 { 58 unsigned int free_space; 59 unsigned int bulks; 60 void *objs[SFC_RX_REFILL_BULK]; 61 efsys_dma_addr_t addr[RTE_DIM(objs)]; 62 unsigned int added = rxq->added; 63 unsigned int id; 64 unsigned int i; 65 struct sfc_efx_rx_sw_desc *rxd; 66 struct rte_mbuf *m; 67 uint16_t port_id = rxq->dp.dpq.port_id; 68 69 free_space = rxq->max_fill_level - (added - rxq->completed); 70 71 if (free_space < rxq->refill_threshold) 72 return; 73 74 bulks = free_space / RTE_DIM(objs); 75 /* refill_threshold guarantees that bulks is positive */ 76 SFC_ASSERT(bulks > 0); 77 78 id = added & rxq->ptr_mask; 79 do { 80 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 81 RTE_DIM(objs)) < 0)) { 82 /* 83 * It is hardly a safe way to increment counter 84 * from different contexts, but all PMDs do it. 85 */ 86 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 87 RTE_DIM(objs); 88 /* Return if we have posted nothing yet */ 89 if (added == rxq->added) 90 return; 91 /* Push posted */ 92 break; 93 } 94 95 for (i = 0; i < RTE_DIM(objs); 96 ++i, id = (id + 1) & rxq->ptr_mask) { 97 m = objs[i]; 98 99 MBUF_RAW_ALLOC_CHECK(m); 100 101 rxd = &rxq->sw_desc[id]; 102 rxd->mbuf = m; 103 104 m->data_off = RTE_PKTMBUF_HEADROOM; 105 m->port = port_id; 106 107 addr[i] = rte_pktmbuf_iova(m); 108 } 109 110 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 111 RTE_DIM(objs), rxq->completed, added); 112 added += RTE_DIM(objs); 113 } while (--bulks > 0); 114 115 SFC_ASSERT(added != rxq->added); 116 rxq->added = added; 117 efx_rx_qpush(rxq->common, added, &rxq->pushed); 118 } 119 120 static uint64_t 121 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 122 { 123 uint64_t mbuf_flags = 0; 124 125 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 126 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 127 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; 128 break; 129 case EFX_PKT_IPV4: 130 mbuf_flags |= PKT_RX_IP_CKSUM_BAD; 131 break; 132 default: 133 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0); 134 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) == 135 PKT_RX_IP_CKSUM_UNKNOWN); 136 break; 137 } 138 139 switch ((desc_flags & 140 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 141 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 142 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 143 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; 144 break; 145 case EFX_PKT_TCP: 146 case EFX_PKT_UDP: 147 mbuf_flags |= PKT_RX_L4_CKSUM_BAD; 148 break; 149 default: 150 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0); 151 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) == 152 PKT_RX_L4_CKSUM_UNKNOWN); 153 break; 154 } 155 156 return mbuf_flags; 157 } 158 159 static uint32_t 160 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 161 { 162 return RTE_PTYPE_L2_ETHER | 163 ((desc_flags & EFX_PKT_IPV4) ? 164 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 165 ((desc_flags & EFX_PKT_IPV6) ? 166 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 167 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 168 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 169 } 170 171 static const uint32_t * 172 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps) 173 { 174 static const uint32_t ptypes[] = { 175 RTE_PTYPE_L2_ETHER, 176 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 177 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 178 RTE_PTYPE_L4_TCP, 179 RTE_PTYPE_L4_UDP, 180 RTE_PTYPE_UNKNOWN 181 }; 182 183 return ptypes; 184 } 185 186 static void 187 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 188 struct rte_mbuf *m) 189 { 190 uint8_t *mbuf_data; 191 192 193 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 194 return; 195 196 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 197 198 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 199 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 200 EFX_RX_HASHALG_TOEPLITZ, 201 mbuf_data); 202 203 m->ol_flags |= PKT_RX_RSS_HASH; 204 } 205 } 206 207 static uint16_t 208 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 209 { 210 struct sfc_dp_rxq *dp_rxq = rx_queue; 211 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 212 unsigned int completed; 213 unsigned int prefix_size = rxq->prefix_size; 214 unsigned int done_pkts = 0; 215 boolean_t discard_next = B_FALSE; 216 struct rte_mbuf *scatter_pkt = NULL; 217 218 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 219 return 0; 220 221 sfc_ev_qpoll(rxq->evq); 222 223 completed = rxq->completed; 224 while (completed != rxq->pending && done_pkts < nb_pkts) { 225 unsigned int id; 226 struct sfc_efx_rx_sw_desc *rxd; 227 struct rte_mbuf *m; 228 unsigned int seg_len; 229 unsigned int desc_flags; 230 231 id = completed++ & rxq->ptr_mask; 232 rxd = &rxq->sw_desc[id]; 233 m = rxd->mbuf; 234 desc_flags = rxd->flags; 235 236 if (discard_next) 237 goto discard; 238 239 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 240 goto discard; 241 242 if (desc_flags & EFX_PKT_PREFIX_LEN) { 243 uint16_t tmp_size; 244 int rc __rte_unused; 245 246 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 247 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 248 SFC_ASSERT(rc == 0); 249 seg_len = tmp_size; 250 } else { 251 seg_len = rxd->size - prefix_size; 252 } 253 254 rte_pktmbuf_data_len(m) = seg_len; 255 rte_pktmbuf_pkt_len(m) = seg_len; 256 257 if (scatter_pkt != NULL) { 258 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 259 rte_pktmbuf_free(scatter_pkt); 260 goto discard; 261 } 262 /* The packet to deliver */ 263 m = scatter_pkt; 264 } 265 266 if (desc_flags & EFX_PKT_CONT) { 267 /* The packet is scattered, more fragments to come */ 268 scatter_pkt = m; 269 /* Further fragments have no prefix */ 270 prefix_size = 0; 271 continue; 272 } 273 274 /* Scattered packet is done */ 275 scatter_pkt = NULL; 276 /* The first fragment of the packet has prefix */ 277 prefix_size = rxq->prefix_size; 278 279 m->ol_flags = 280 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 281 m->packet_type = 282 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 283 284 /* 285 * Extract RSS hash from the packet prefix and 286 * set the corresponding field (if needed and possible) 287 */ 288 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 289 290 m->data_off += prefix_size; 291 292 *rx_pkts++ = m; 293 done_pkts++; 294 continue; 295 296 discard: 297 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 298 rte_mbuf_raw_free(m); 299 rxd->mbuf = NULL; 300 } 301 302 /* pending is only moved when entire packet is received */ 303 SFC_ASSERT(scatter_pkt == NULL); 304 305 rxq->completed = completed; 306 307 sfc_efx_rx_qrefill(rxq); 308 309 return done_pkts; 310 } 311 312 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 313 static unsigned int 314 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 315 { 316 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 317 318 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 319 return 0; 320 321 sfc_ev_qpoll(rxq->evq); 322 323 return rxq->pending - rxq->completed; 324 } 325 326 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 327 static int 328 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 329 { 330 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 331 332 if (unlikely(offset > rxq->ptr_mask)) 333 return -EINVAL; 334 335 /* 336 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 337 * it is required for the queue to be running, but the 338 * check is omitted because API design assumes that it 339 * is the duty of the caller to satisfy all conditions 340 */ 341 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 342 SFC_EFX_RXQ_FLAG_RUNNING); 343 sfc_ev_qpoll(rxq->evq); 344 345 /* 346 * There is a handful of reserved entries in the ring, 347 * but an explicit check whether the offset points to 348 * a reserved entry is neglected since the two checks 349 * below rely on the figures which take the HW limits 350 * into account and thus if an entry is reserved, the 351 * checks will fail and UNAVAIL code will be returned 352 */ 353 354 if (offset < (rxq->pending - rxq->completed)) 355 return RTE_ETH_RX_DESC_DONE; 356 357 if (offset < (rxq->added - rxq->completed)) 358 return RTE_ETH_RX_DESC_AVAIL; 359 360 return RTE_ETH_RX_DESC_UNAVAIL; 361 } 362 363 struct sfc_rxq * 364 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 365 { 366 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 367 struct rte_eth_dev *eth_dev; 368 struct sfc_adapter *sa; 369 struct sfc_rxq *rxq; 370 371 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 372 eth_dev = &rte_eth_devices[dpq->port_id]; 373 374 sa = eth_dev->data->dev_private; 375 376 SFC_ASSERT(dpq->queue_id < sa->rxq_count); 377 rxq = sa->rxq_info[dpq->queue_id].rxq; 378 379 SFC_ASSERT(rxq != NULL); 380 return rxq; 381 } 382 383 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 384 static int 385 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 386 __rte_unused struct rte_mempool *mb_pool, 387 unsigned int *rxq_entries, 388 unsigned int *evq_entries, 389 unsigned int *rxq_max_fill_level) 390 { 391 *rxq_entries = nb_rx_desc; 392 *evq_entries = nb_rx_desc; 393 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 394 return 0; 395 } 396 397 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 398 static int 399 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 400 const struct rte_pci_addr *pci_addr, int socket_id, 401 const struct sfc_dp_rx_qcreate_info *info, 402 struct sfc_dp_rxq **dp_rxqp) 403 { 404 struct sfc_efx_rxq *rxq; 405 int rc; 406 407 rc = ENOMEM; 408 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 409 RTE_CACHE_LINE_SIZE, socket_id); 410 if (rxq == NULL) 411 goto fail_rxq_alloc; 412 413 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 414 415 rc = ENOMEM; 416 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 417 info->rxq_entries, 418 sizeof(*rxq->sw_desc), 419 RTE_CACHE_LINE_SIZE, socket_id); 420 if (rxq->sw_desc == NULL) 421 goto fail_desc_alloc; 422 423 /* efx datapath is bound to efx control path */ 424 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 425 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 426 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 427 rxq->ptr_mask = info->rxq_entries - 1; 428 rxq->batch_max = info->batch_max; 429 rxq->prefix_size = info->prefix_size; 430 rxq->max_fill_level = info->max_fill_level; 431 rxq->refill_threshold = info->refill_threshold; 432 rxq->buf_size = info->buf_size; 433 rxq->refill_mb_pool = info->refill_mb_pool; 434 435 *dp_rxqp = &rxq->dp; 436 return 0; 437 438 fail_desc_alloc: 439 rte_free(rxq); 440 441 fail_rxq_alloc: 442 return rc; 443 } 444 445 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 446 static void 447 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 448 { 449 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 450 451 rte_free(rxq->sw_desc); 452 rte_free(rxq); 453 } 454 455 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 456 static int 457 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 458 __rte_unused unsigned int evq_read_ptr) 459 { 460 /* libefx-based datapath is specific to libefx-based PMD */ 461 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 462 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 463 464 rxq->common = crxq->common; 465 466 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 467 468 sfc_efx_rx_qrefill(rxq); 469 470 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 471 472 return 0; 473 } 474 475 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 476 static void 477 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 478 __rte_unused unsigned int *evq_read_ptr) 479 { 480 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 481 482 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 483 484 /* libefx-based datapath is bound to libefx-based PMD and uses 485 * event queue structure directly. So, there is no necessity to 486 * return EvQ read pointer. 487 */ 488 } 489 490 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 491 static void 492 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 493 { 494 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 495 unsigned int i; 496 struct sfc_efx_rx_sw_desc *rxd; 497 498 for (i = rxq->completed; i != rxq->added; ++i) { 499 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 500 rte_mbuf_raw_free(rxd->mbuf); 501 rxd->mbuf = NULL; 502 /* Packed stream relies on 0 in inactive SW desc. 503 * Rx queue stop is not performance critical, so 504 * there is no harm to do it always. 505 */ 506 rxd->flags = 0; 507 rxd->size = 0; 508 } 509 510 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 511 } 512 513 struct sfc_dp_rx sfc_efx_rx = { 514 .dp = { 515 .name = SFC_KVARG_DATAPATH_EFX, 516 .type = SFC_DP_RX, 517 .hw_fw_caps = 0, 518 }, 519 .features = SFC_DP_RX_FEAT_SCATTER | 520 SFC_DP_RX_FEAT_CHECKSUM, 521 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 522 .qcreate = sfc_efx_rx_qcreate, 523 .qdestroy = sfc_efx_rx_qdestroy, 524 .qstart = sfc_efx_rx_qstart, 525 .qstop = sfc_efx_rx_qstop, 526 .qpurge = sfc_efx_rx_qpurge, 527 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 528 .qdesc_npending = sfc_efx_rx_qdesc_npending, 529 .qdesc_status = sfc_efx_rx_qdesc_status, 530 .pkt_burst = sfc_efx_recv_pkts, 531 }; 532 533 unsigned int 534 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index) 535 { 536 struct sfc_rxq *rxq; 537 538 SFC_ASSERT(sw_index < sa->rxq_count); 539 rxq = sa->rxq_info[sw_index].rxq; 540 541 if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0) 542 return 0; 543 544 return sa->dp_rx->qdesc_npending(rxq->dp); 545 } 546 547 int 548 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset) 549 { 550 struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq); 551 552 return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq); 553 } 554 555 static void 556 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index) 557 { 558 struct sfc_rxq *rxq; 559 unsigned int retry_count; 560 unsigned int wait_count; 561 int rc; 562 563 rxq = sa->rxq_info[sw_index].rxq; 564 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED); 565 566 /* 567 * Retry Rx queue flushing in the case of flush failed or 568 * timeout. In the worst case it can delay for 6 seconds. 569 */ 570 for (retry_count = 0; 571 ((rxq->state & SFC_RXQ_FLUSHED) == 0) && 572 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 573 ++retry_count) { 574 rc = efx_rx_qflush(rxq->common); 575 if (rc != 0) { 576 rxq->state |= (rc == EALREADY) ? 577 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 578 break; 579 } 580 rxq->state &= ~SFC_RXQ_FLUSH_FAILED; 581 rxq->state |= SFC_RXQ_FLUSHING; 582 583 /* 584 * Wait for Rx queue flush done or failed event at least 585 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 586 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 587 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 588 */ 589 wait_count = 0; 590 do { 591 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 592 sfc_ev_qpoll(rxq->evq); 593 } while ((rxq->state & SFC_RXQ_FLUSHING) && 594 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 595 596 if (rxq->state & SFC_RXQ_FLUSHING) 597 sfc_err(sa, "RxQ %u flush timed out", sw_index); 598 599 if (rxq->state & SFC_RXQ_FLUSH_FAILED) 600 sfc_err(sa, "RxQ %u flush failed", sw_index); 601 602 if (rxq->state & SFC_RXQ_FLUSHED) 603 sfc_notice(sa, "RxQ %u flushed", sw_index); 604 } 605 606 sa->dp_rx->qpurge(rxq->dp); 607 } 608 609 static int 610 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 611 { 612 struct sfc_rss *rss = &sa->rss; 613 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 614 struct sfc_port *port = &sa->port; 615 int rc; 616 617 /* 618 * If promiscuous or all-multicast mode has been requested, setting 619 * filter for the default Rx queue might fail, in particular, while 620 * running over PCI function which is not a member of corresponding 621 * privilege groups; if this occurs, few iterations will be made to 622 * repeat this step without promiscuous and all-multicast flags set 623 */ 624 retry: 625 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 626 if (rc == 0) 627 return 0; 628 else if (rc != EOPNOTSUPP) 629 return rc; 630 631 if (port->promisc) { 632 sfc_warn(sa, "promiscuous mode has been requested, " 633 "but the HW rejects it"); 634 sfc_warn(sa, "promiscuous mode will be disabled"); 635 636 port->promisc = B_FALSE; 637 rc = sfc_set_rx_mode(sa); 638 if (rc != 0) 639 return rc; 640 641 goto retry; 642 } 643 644 if (port->allmulti) { 645 sfc_warn(sa, "all-multicast mode has been requested, " 646 "but the HW rejects it"); 647 sfc_warn(sa, "all-multicast mode will be disabled"); 648 649 port->allmulti = B_FALSE; 650 rc = sfc_set_rx_mode(sa); 651 if (rc != 0) 652 return rc; 653 654 goto retry; 655 } 656 657 return rc; 658 } 659 660 int 661 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 662 { 663 struct sfc_port *port = &sa->port; 664 struct sfc_rxq_info *rxq_info; 665 struct sfc_rxq *rxq; 666 struct sfc_evq *evq; 667 int rc; 668 669 sfc_log_init(sa, "sw_index=%u", sw_index); 670 671 SFC_ASSERT(sw_index < sa->rxq_count); 672 673 rxq_info = &sa->rxq_info[sw_index]; 674 rxq = rxq_info->rxq; 675 SFC_ASSERT(rxq != NULL); 676 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED); 677 678 evq = rxq->evq; 679 680 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index)); 681 if (rc != 0) 682 goto fail_ev_qstart; 683 684 switch (rxq_info->type) { 685 case EFX_RXQ_TYPE_DEFAULT: 686 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 687 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 688 rxq_info->type_flags, evq->common, &rxq->common); 689 break; 690 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 691 struct rte_mempool *mp = rxq->refill_mb_pool; 692 struct rte_mempool_info mp_info; 693 694 rc = rte_mempool_ops_get_info(mp, &mp_info); 695 if (rc != 0) { 696 /* Positive errno is used in the driver */ 697 rc = -rc; 698 goto fail_mp_get_info; 699 } 700 if (mp_info.contig_block_size <= 0) { 701 rc = EINVAL; 702 goto fail_bad_contig_block_size; 703 } 704 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 705 mp_info.contig_block_size, rxq->buf_size, 706 mp->header_size + mp->elt_size + mp->trailer_size, 707 sa->rxd_wait_timeout_ns, 708 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 709 evq->common, &rxq->common); 710 break; 711 } 712 default: 713 rc = ENOTSUP; 714 } 715 if (rc != 0) 716 goto fail_rx_qcreate; 717 718 efx_rx_qenable(rxq->common); 719 720 rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr); 721 if (rc != 0) 722 goto fail_dp_qstart; 723 724 rxq->state |= SFC_RXQ_STARTED; 725 726 if ((sw_index == 0) && !port->isolated) { 727 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 728 if (rc != 0) 729 goto fail_mac_filter_default_rxq_set; 730 } 731 732 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 733 sa->eth_dev->data->rx_queue_state[sw_index] = 734 RTE_ETH_QUEUE_STATE_STARTED; 735 736 return 0; 737 738 fail_mac_filter_default_rxq_set: 739 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr); 740 741 fail_dp_qstart: 742 sfc_rx_qflush(sa, sw_index); 743 744 fail_rx_qcreate: 745 fail_bad_contig_block_size: 746 fail_mp_get_info: 747 sfc_ev_qstop(evq); 748 749 fail_ev_qstart: 750 return rc; 751 } 752 753 void 754 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 755 { 756 struct sfc_rxq_info *rxq_info; 757 struct sfc_rxq *rxq; 758 759 sfc_log_init(sa, "sw_index=%u", sw_index); 760 761 SFC_ASSERT(sw_index < sa->rxq_count); 762 763 rxq_info = &sa->rxq_info[sw_index]; 764 rxq = rxq_info->rxq; 765 766 if (rxq == NULL || rxq->state == SFC_RXQ_INITIALIZED) 767 return; 768 SFC_ASSERT(rxq->state & SFC_RXQ_STARTED); 769 770 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 771 sa->eth_dev->data->rx_queue_state[sw_index] = 772 RTE_ETH_QUEUE_STATE_STOPPED; 773 774 sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr); 775 776 if (sw_index == 0) 777 efx_mac_filter_default_rxq_clear(sa->nic); 778 779 sfc_rx_qflush(sa, sw_index); 780 781 rxq->state = SFC_RXQ_INITIALIZED; 782 783 efx_rx_qdestroy(rxq->common); 784 785 sfc_ev_qstop(rxq->evq); 786 } 787 788 uint64_t 789 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 790 { 791 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 792 uint64_t caps = 0; 793 794 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME; 795 796 if (sa->dp_rx->features & SFC_DP_RX_FEAT_CHECKSUM) { 797 caps |= DEV_RX_OFFLOAD_IPV4_CKSUM; 798 caps |= DEV_RX_OFFLOAD_UDP_CKSUM; 799 caps |= DEV_RX_OFFLOAD_TCP_CKSUM; 800 } 801 802 if (encp->enc_tunnel_encapsulations_supported && 803 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS)) 804 caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 805 806 return caps; 807 } 808 809 uint64_t 810 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 811 { 812 uint64_t caps = 0; 813 814 if (sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER) 815 caps |= DEV_RX_OFFLOAD_SCATTER; 816 817 return caps; 818 } 819 820 static int 821 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 822 const struct rte_eth_rxconf *rx_conf, 823 __rte_unused uint64_t offloads) 824 { 825 int rc = 0; 826 827 if (rx_conf->rx_thresh.pthresh != 0 || 828 rx_conf->rx_thresh.hthresh != 0 || 829 rx_conf->rx_thresh.wthresh != 0) { 830 sfc_warn(sa, 831 "RxQ prefetch/host/writeback thresholds are not supported"); 832 } 833 834 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 835 sfc_err(sa, 836 "RxQ free threshold too large: %u vs maximum %u", 837 rx_conf->rx_free_thresh, rxq_max_fill_level); 838 rc = EINVAL; 839 } 840 841 if (rx_conf->rx_drop_en == 0) { 842 sfc_err(sa, "RxQ drop disable is not supported"); 843 rc = EINVAL; 844 } 845 846 return rc; 847 } 848 849 static unsigned int 850 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 851 { 852 uint32_t data_off; 853 uint32_t order; 854 855 /* The mbuf object itself is always cache line aligned */ 856 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 857 858 /* Data offset from mbuf object start */ 859 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 860 RTE_PKTMBUF_HEADROOM; 861 862 order = MIN(order, rte_bsf32(data_off)); 863 864 return 1u << order; 865 } 866 867 static uint16_t 868 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 869 { 870 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 871 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 872 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 873 uint16_t buf_size; 874 unsigned int buf_aligned; 875 unsigned int start_alignment; 876 unsigned int end_padding_alignment; 877 878 /* Below it is assumed that both alignments are power of 2 */ 879 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 880 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 881 882 /* 883 * mbuf is always cache line aligned, double-check 884 * that it meets rx buffer start alignment requirements. 885 */ 886 887 /* Start from mbuf pool data room size */ 888 buf_size = rte_pktmbuf_data_room_size(mb_pool); 889 890 /* Remove headroom */ 891 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 892 sfc_err(sa, 893 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 894 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 895 return 0; 896 } 897 buf_size -= RTE_PKTMBUF_HEADROOM; 898 899 /* Calculate guaranteed data start alignment */ 900 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 901 902 /* Reserve space for start alignment */ 903 if (buf_aligned < nic_align_start) { 904 start_alignment = nic_align_start - buf_aligned; 905 if (buf_size <= start_alignment) { 906 sfc_err(sa, 907 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 908 mb_pool->name, 909 rte_pktmbuf_data_room_size(mb_pool), 910 RTE_PKTMBUF_HEADROOM, start_alignment); 911 return 0; 912 } 913 buf_aligned = nic_align_start; 914 buf_size -= start_alignment; 915 } else { 916 start_alignment = 0; 917 } 918 919 /* Make sure that end padding does not write beyond the buffer */ 920 if (buf_aligned < nic_align_end) { 921 /* 922 * Estimate space which can be lost. If guarnteed buffer 923 * size is odd, lost space is (nic_align_end - 1). More 924 * accurate formula is below. 925 */ 926 end_padding_alignment = nic_align_end - 927 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 928 if (buf_size <= end_padding_alignment) { 929 sfc_err(sa, 930 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 931 mb_pool->name, 932 rte_pktmbuf_data_room_size(mb_pool), 933 RTE_PKTMBUF_HEADROOM, start_alignment, 934 end_padding_alignment); 935 return 0; 936 } 937 buf_size -= end_padding_alignment; 938 } else { 939 /* 940 * Start is aligned the same or better than end, 941 * just align length. 942 */ 943 buf_size = P2ALIGN(buf_size, nic_align_end); 944 } 945 946 return buf_size; 947 } 948 949 int 950 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 951 uint16_t nb_rx_desc, unsigned int socket_id, 952 const struct rte_eth_rxconf *rx_conf, 953 struct rte_mempool *mb_pool) 954 { 955 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 956 struct sfc_rss *rss = &sa->rss; 957 int rc; 958 unsigned int rxq_entries; 959 unsigned int evq_entries; 960 unsigned int rxq_max_fill_level; 961 uint64_t offloads; 962 uint16_t buf_size; 963 struct sfc_rxq_info *rxq_info; 964 struct sfc_evq *evq; 965 struct sfc_rxq *rxq; 966 struct sfc_dp_rx_qcreate_info info; 967 968 rc = sa->dp_rx->qsize_up_rings(nb_rx_desc, mb_pool, &rxq_entries, 969 &evq_entries, &rxq_max_fill_level); 970 if (rc != 0) 971 goto fail_size_up_rings; 972 SFC_ASSERT(rxq_entries >= EFX_RXQ_MINNDESCS); 973 SFC_ASSERT(rxq_entries <= EFX_RXQ_MAXNDESCS); 974 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 975 976 offloads = rx_conf->offloads | 977 sa->eth_dev->data->dev_conf.rxmode.offloads; 978 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 979 if (rc != 0) 980 goto fail_bad_conf; 981 982 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 983 if (buf_size == 0) { 984 sfc_err(sa, "RxQ %u mbuf pool object size is too small", 985 sw_index); 986 rc = EINVAL; 987 goto fail_bad_conf; 988 } 989 990 if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) && 991 (~offloads & DEV_RX_OFFLOAD_SCATTER)) { 992 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool " 993 "object size is too small", sw_index); 994 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs " 995 "PDU size %u plus Rx prefix %u bytes", 996 sw_index, buf_size, (unsigned int)sa->port.pdu, 997 encp->enc_rx_prefix_size); 998 rc = EINVAL; 999 goto fail_bad_conf; 1000 } 1001 1002 SFC_ASSERT(sw_index < sa->rxq_count); 1003 rxq_info = &sa->rxq_info[sw_index]; 1004 1005 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1006 rxq_info->entries = rxq_entries; 1007 1008 if (sa->dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1009 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1010 else 1011 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1012 1013 rxq_info->type_flags = 1014 (offloads & DEV_RX_OFFLOAD_SCATTER) ? 1015 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1016 1017 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1018 (sa->dp_rx->features & SFC_DP_RX_FEAT_TUNNELS)) 1019 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1020 1021 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1022 evq_entries, socket_id, &evq); 1023 if (rc != 0) 1024 goto fail_ev_qinit; 1025 1026 rc = ENOMEM; 1027 rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE, 1028 socket_id); 1029 if (rxq == NULL) 1030 goto fail_rxq_alloc; 1031 1032 rxq_info->rxq = rxq; 1033 1034 rxq->evq = evq; 1035 rxq->hw_index = sw_index; 1036 rxq->refill_threshold = 1037 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK); 1038 rxq->refill_mb_pool = mb_pool; 1039 rxq->buf_size = buf_size; 1040 1041 rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries), 1042 socket_id, &rxq->mem); 1043 if (rc != 0) 1044 goto fail_dma_alloc; 1045 1046 memset(&info, 0, sizeof(info)); 1047 info.refill_mb_pool = rxq->refill_mb_pool; 1048 info.max_fill_level = rxq_max_fill_level; 1049 info.refill_threshold = rxq->refill_threshold; 1050 info.buf_size = buf_size; 1051 info.batch_max = encp->enc_rx_batch_max; 1052 info.prefix_size = encp->enc_rx_prefix_size; 1053 1054 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0) 1055 info.flags |= SFC_RXQ_FLAG_RSS_HASH; 1056 1057 info.rxq_entries = rxq_info->entries; 1058 info.rxq_hw_ring = rxq->mem.esm_base; 1059 info.evq_entries = evq_entries; 1060 info.evq_hw_ring = evq->mem.esm_base; 1061 info.hw_index = rxq->hw_index; 1062 info.mem_bar = sa->mem_bar.esb_base; 1063 info.vi_window_shift = encp->enc_vi_window_shift; 1064 1065 rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1066 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1067 socket_id, &info, &rxq->dp); 1068 if (rc != 0) 1069 goto fail_dp_rx_qcreate; 1070 1071 evq->dp_rxq = rxq->dp; 1072 1073 rxq->state = SFC_RXQ_INITIALIZED; 1074 1075 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1076 1077 return 0; 1078 1079 fail_dp_rx_qcreate: 1080 sfc_dma_free(sa, &rxq->mem); 1081 1082 fail_dma_alloc: 1083 rxq_info->rxq = NULL; 1084 rte_free(rxq); 1085 1086 fail_rxq_alloc: 1087 sfc_ev_qfini(evq); 1088 1089 fail_ev_qinit: 1090 rxq_info->entries = 0; 1091 1092 fail_bad_conf: 1093 fail_size_up_rings: 1094 sfc_log_init(sa, "failed %d", rc); 1095 return rc; 1096 } 1097 1098 void 1099 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 1100 { 1101 struct sfc_rxq_info *rxq_info; 1102 struct sfc_rxq *rxq; 1103 1104 SFC_ASSERT(sw_index < sa->rxq_count); 1105 sa->eth_dev->data->rx_queues[sw_index] = NULL; 1106 1107 rxq_info = &sa->rxq_info[sw_index]; 1108 1109 rxq = rxq_info->rxq; 1110 SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED); 1111 1112 sa->dp_rx->qdestroy(rxq->dp); 1113 rxq->dp = NULL; 1114 1115 rxq_info->rxq = NULL; 1116 rxq_info->entries = 0; 1117 1118 sfc_dma_free(sa, &rxq->mem); 1119 1120 sfc_ev_qfini(rxq->evq); 1121 rxq->evq = NULL; 1122 1123 rte_free(rxq); 1124 } 1125 1126 /* 1127 * Mapping between RTE RSS hash functions and their EFX counterparts. 1128 */ 1129 struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1130 { ETH_RSS_NONFRAG_IPV4_TCP, 1131 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1132 { ETH_RSS_NONFRAG_IPV4_UDP, 1133 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1134 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX, 1135 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1136 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX, 1137 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1138 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER, 1139 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1140 EFX_RX_HASH(IPV4, 2TUPLE) }, 1141 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER | 1142 ETH_RSS_IPV6_EX, 1143 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1144 EFX_RX_HASH(IPV6, 2TUPLE) } 1145 }; 1146 1147 static efx_rx_hash_type_t 1148 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1149 unsigned int *hash_type_flags_supported, 1150 unsigned int nb_hash_type_flags_supported) 1151 { 1152 efx_rx_hash_type_t hash_type_masked = 0; 1153 unsigned int i, j; 1154 1155 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1156 unsigned int class_tuple_lbn[] = { 1157 EFX_RX_CLASS_IPV4_TCP_LBN, 1158 EFX_RX_CLASS_IPV4_UDP_LBN, 1159 EFX_RX_CLASS_IPV4_LBN, 1160 EFX_RX_CLASS_IPV6_TCP_LBN, 1161 EFX_RX_CLASS_IPV6_UDP_LBN, 1162 EFX_RX_CLASS_IPV6_LBN 1163 }; 1164 1165 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1166 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1167 unsigned int flag; 1168 1169 tuple_mask <<= class_tuple_lbn[j]; 1170 flag = hash_type & tuple_mask; 1171 1172 if (flag == hash_type_flags_supported[i]) 1173 hash_type_masked |= flag; 1174 } 1175 } 1176 1177 return hash_type_masked; 1178 } 1179 1180 int 1181 sfc_rx_hash_init(struct sfc_adapter *sa) 1182 { 1183 struct sfc_rss *rss = &sa->rss; 1184 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1185 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1186 efx_rx_hash_alg_t alg; 1187 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1188 unsigned int nb_flags_supp; 1189 struct sfc_rss_hf_rte_to_efx *hf_map; 1190 struct sfc_rss_hf_rte_to_efx *entry; 1191 efx_rx_hash_type_t efx_hash_types; 1192 unsigned int i; 1193 int rc; 1194 1195 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1196 alg = EFX_RX_HASHALG_TOEPLITZ; 1197 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1198 alg = EFX_RX_HASHALG_PACKED_STREAM; 1199 else 1200 return EINVAL; 1201 1202 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1203 RTE_DIM(flags_supp), &nb_flags_supp); 1204 if (rc != 0) 1205 return rc; 1206 1207 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1208 RTE_DIM(sfc_rss_hf_map), 1209 sizeof(*hf_map), 0, sa->socket_id); 1210 if (hf_map == NULL) 1211 return ENOMEM; 1212 1213 entry = hf_map; 1214 efx_hash_types = 0; 1215 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1216 efx_rx_hash_type_t ht; 1217 1218 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1219 flags_supp, nb_flags_supp); 1220 if (ht != 0) { 1221 entry->rte = sfc_rss_hf_map[i].rte; 1222 entry->efx = ht; 1223 efx_hash_types |= ht; 1224 ++entry; 1225 } 1226 } 1227 1228 rss->hash_alg = alg; 1229 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1230 rss->hf_map = hf_map; 1231 rss->hash_types = efx_hash_types; 1232 1233 return 0; 1234 } 1235 1236 void 1237 sfc_rx_hash_fini(struct sfc_adapter *sa) 1238 { 1239 struct sfc_rss *rss = &sa->rss; 1240 1241 rte_free(rss->hf_map); 1242 } 1243 1244 int 1245 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1246 efx_rx_hash_type_t *efx) 1247 { 1248 struct sfc_rss *rss = &sa->rss; 1249 efx_rx_hash_type_t hash_types = 0; 1250 unsigned int i; 1251 1252 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1253 uint64_t rte_mask = rss->hf_map[i].rte; 1254 1255 if ((rte & rte_mask) != 0) { 1256 rte &= ~rte_mask; 1257 hash_types |= rss->hf_map[i].efx; 1258 } 1259 } 1260 1261 if (rte != 0) { 1262 sfc_err(sa, "unsupported hash functions requested"); 1263 return EINVAL; 1264 } 1265 1266 *efx = hash_types; 1267 1268 return 0; 1269 } 1270 1271 uint64_t 1272 sfc_rx_hf_efx_to_rte(struct sfc_adapter *sa, efx_rx_hash_type_t efx) 1273 { 1274 struct sfc_rss *rss = &sa->rss; 1275 uint64_t rte = 0; 1276 unsigned int i; 1277 1278 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1279 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1280 1281 if ((efx & hash_type) == hash_type) 1282 rte |= rss->hf_map[i].rte; 1283 } 1284 1285 return rte; 1286 } 1287 1288 static int 1289 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1290 struct rte_eth_rss_conf *conf) 1291 { 1292 struct sfc_rss *rss = &sa->rss; 1293 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1294 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(sa, efx_hash_types); 1295 int rc; 1296 1297 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1298 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1299 conf->rss_key != NULL) 1300 return EINVAL; 1301 } 1302 1303 if (conf->rss_hf != 0) { 1304 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1305 if (rc != 0) 1306 return rc; 1307 } 1308 1309 if (conf->rss_key != NULL) { 1310 if (conf->rss_key_len != sizeof(rss->key)) { 1311 sfc_err(sa, "RSS key size is wrong (should be %lu)", 1312 sizeof(rss->key)); 1313 return EINVAL; 1314 } 1315 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1316 } 1317 1318 rss->hash_types = efx_hash_types; 1319 1320 return 0; 1321 } 1322 1323 static int 1324 sfc_rx_rss_config(struct sfc_adapter *sa) 1325 { 1326 struct sfc_rss *rss = &sa->rss; 1327 int rc = 0; 1328 1329 if (rss->channels > 0) { 1330 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1331 rss->hash_alg, rss->hash_types, 1332 B_TRUE); 1333 if (rc != 0) 1334 goto finish; 1335 1336 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1337 rss->key, sizeof(rss->key)); 1338 if (rc != 0) 1339 goto finish; 1340 1341 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1342 rss->tbl, RTE_DIM(rss->tbl)); 1343 } 1344 1345 finish: 1346 return rc; 1347 } 1348 1349 int 1350 sfc_rx_start(struct sfc_adapter *sa) 1351 { 1352 unsigned int sw_index; 1353 int rc; 1354 1355 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count); 1356 1357 rc = efx_rx_init(sa->nic); 1358 if (rc != 0) 1359 goto fail_rx_init; 1360 1361 rc = sfc_rx_rss_config(sa); 1362 if (rc != 0) 1363 goto fail_rss_config; 1364 1365 for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) { 1366 if (sa->rxq_info[sw_index].rxq != NULL && 1367 (!sa->rxq_info[sw_index].deferred_start || 1368 sa->rxq_info[sw_index].deferred_started)) { 1369 rc = sfc_rx_qstart(sa, sw_index); 1370 if (rc != 0) 1371 goto fail_rx_qstart; 1372 } 1373 } 1374 1375 return 0; 1376 1377 fail_rx_qstart: 1378 while (sw_index-- > 0) 1379 sfc_rx_qstop(sa, sw_index); 1380 1381 fail_rss_config: 1382 efx_rx_fini(sa->nic); 1383 1384 fail_rx_init: 1385 sfc_log_init(sa, "failed %d", rc); 1386 return rc; 1387 } 1388 1389 void 1390 sfc_rx_stop(struct sfc_adapter *sa) 1391 { 1392 unsigned int sw_index; 1393 1394 sfc_log_init(sa, "rxq_count=%u", sa->rxq_count); 1395 1396 sw_index = sa->rxq_count; 1397 while (sw_index-- > 0) { 1398 if (sa->rxq_info[sw_index].rxq != NULL) 1399 sfc_rx_qstop(sa, sw_index); 1400 } 1401 1402 efx_rx_fini(sa->nic); 1403 } 1404 1405 static int 1406 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 1407 { 1408 struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index]; 1409 unsigned int max_entries; 1410 1411 max_entries = EFX_RXQ_MAXNDESCS; 1412 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1413 1414 rxq_info->max_entries = max_entries; 1415 1416 return 0; 1417 } 1418 1419 static int 1420 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1421 { 1422 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1423 sfc_rx_get_queue_offload_caps(sa); 1424 struct sfc_rss *rss = &sa->rss; 1425 int rc = 0; 1426 1427 switch (rxmode->mq_mode) { 1428 case ETH_MQ_RX_NONE: 1429 /* No special checks are required */ 1430 break; 1431 case ETH_MQ_RX_RSS: 1432 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1433 sfc_err(sa, "RSS is not available"); 1434 rc = EINVAL; 1435 } 1436 break; 1437 default: 1438 sfc_err(sa, "Rx multi-queue mode %u not supported", 1439 rxmode->mq_mode); 1440 rc = EINVAL; 1441 } 1442 1443 /* 1444 * Requested offloads are validated against supported by ethdev, 1445 * so unsupported offloads cannot be added as the result of 1446 * below check. 1447 */ 1448 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) != 1449 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) { 1450 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1451 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM; 1452 } 1453 1454 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1455 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1456 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1457 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1458 } 1459 1460 return rc; 1461 } 1462 1463 /** 1464 * Destroy excess queues that are no longer needed after reconfiguration 1465 * or complete close. 1466 */ 1467 static void 1468 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1469 { 1470 int sw_index; 1471 1472 SFC_ASSERT(nb_rx_queues <= sa->rxq_count); 1473 1474 sw_index = sa->rxq_count; 1475 while (--sw_index >= (int)nb_rx_queues) { 1476 if (sa->rxq_info[sw_index].rxq != NULL) 1477 sfc_rx_qfini(sa, sw_index); 1478 } 1479 1480 sa->rxq_count = nb_rx_queues; 1481 } 1482 1483 /** 1484 * Initialize Rx subsystem. 1485 * 1486 * Called at device (re)configuration stage when number of receive queues is 1487 * specified together with other device level receive configuration. 1488 * 1489 * It should be used to allocate NUMA-unaware resources. 1490 */ 1491 int 1492 sfc_rx_configure(struct sfc_adapter *sa) 1493 { 1494 struct sfc_rss *rss = &sa->rss; 1495 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1496 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1497 int rc; 1498 1499 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1500 nb_rx_queues, sa->rxq_count); 1501 1502 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1503 if (rc != 0) 1504 goto fail_check_mode; 1505 1506 if (nb_rx_queues == sa->rxq_count) 1507 goto configure_rss; 1508 1509 if (sa->rxq_info == NULL) { 1510 rc = ENOMEM; 1511 sa->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues, 1512 sizeof(sa->rxq_info[0]), 0, 1513 sa->socket_id); 1514 if (sa->rxq_info == NULL) 1515 goto fail_rxqs_alloc; 1516 } else { 1517 struct sfc_rxq_info *new_rxq_info; 1518 1519 if (nb_rx_queues < sa->rxq_count) 1520 sfc_rx_fini_queues(sa, nb_rx_queues); 1521 1522 rc = ENOMEM; 1523 new_rxq_info = 1524 rte_realloc(sa->rxq_info, 1525 nb_rx_queues * sizeof(sa->rxq_info[0]), 0); 1526 if (new_rxq_info == NULL && nb_rx_queues > 0) 1527 goto fail_rxqs_realloc; 1528 1529 sa->rxq_info = new_rxq_info; 1530 if (nb_rx_queues > sa->rxq_count) 1531 memset(&sa->rxq_info[sa->rxq_count], 0, 1532 (nb_rx_queues - sa->rxq_count) * 1533 sizeof(sa->rxq_info[0])); 1534 } 1535 1536 while (sa->rxq_count < nb_rx_queues) { 1537 rc = sfc_rx_qinit_info(sa, sa->rxq_count); 1538 if (rc != 0) 1539 goto fail_rx_qinit_info; 1540 1541 sa->rxq_count++; 1542 } 1543 1544 configure_rss: 1545 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ? 1546 MIN(sa->rxq_count, EFX_MAXRSS) : 0; 1547 1548 if (rss->channels > 0) { 1549 struct rte_eth_rss_conf *adv_conf_rss; 1550 unsigned int sw_index; 1551 1552 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1553 rss->tbl[sw_index] = sw_index % rss->channels; 1554 1555 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1556 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1557 if (rc != 0) 1558 goto fail_rx_process_adv_conf_rss; 1559 } 1560 1561 return 0; 1562 1563 fail_rx_process_adv_conf_rss: 1564 fail_rx_qinit_info: 1565 fail_rxqs_realloc: 1566 fail_rxqs_alloc: 1567 sfc_rx_close(sa); 1568 1569 fail_check_mode: 1570 sfc_log_init(sa, "failed %d", rc); 1571 return rc; 1572 } 1573 1574 /** 1575 * Shutdown Rx subsystem. 1576 * 1577 * Called at device close stage, for example, before device shutdown. 1578 */ 1579 void 1580 sfc_rx_close(struct sfc_adapter *sa) 1581 { 1582 struct sfc_rss *rss = &sa->rss; 1583 1584 sfc_rx_fini_queues(sa, 0); 1585 1586 rss->channels = 0; 1587 1588 rte_free(sa->rxq_info); 1589 sa->rxq_info = NULL; 1590 } 1591