1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016-2018 Solarflare Communications Inc. 4 * All rights reserved. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_log.h" 17 #include "sfc_ev.h" 18 #include "sfc_rx.h" 19 #include "sfc_kvargs.h" 20 #include "sfc_tweak.h" 21 22 /* 23 * Maximum number of Rx queue flush attempt in the case of failure or 24 * flush timeout 25 */ 26 #define SFC_RX_QFLUSH_ATTEMPTS (3) 27 28 /* 29 * Time to wait between event queue polling attempts when waiting for Rx 30 * queue flush done or failed events. 31 */ 32 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 33 34 /* 35 * Maximum number of event queue polling attempts when waiting for Rx queue 36 * flush done or failed events. It defines Rx queue flush attempt timeout 37 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 38 */ 39 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 40 41 void 42 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info) 43 { 44 rxq_info->state |= SFC_RXQ_FLUSHED; 45 rxq_info->state &= ~SFC_RXQ_FLUSHING; 46 } 47 48 void 49 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info) 50 { 51 rxq_info->state |= SFC_RXQ_FLUSH_FAILED; 52 rxq_info->state &= ~SFC_RXQ_FLUSHING; 53 } 54 55 static int 56 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq) 57 { 58 int rc = 0; 59 60 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) { 61 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr); 62 if (rc == 0) 63 rxq->evq->read_ptr_primed = rxq->evq->read_ptr; 64 } 65 return rc; 66 } 67 68 static void 69 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 70 { 71 unsigned int free_space; 72 unsigned int bulks; 73 void *objs[SFC_RX_REFILL_BULK]; 74 efsys_dma_addr_t addr[RTE_DIM(objs)]; 75 unsigned int added = rxq->added; 76 unsigned int id; 77 unsigned int i; 78 struct sfc_efx_rx_sw_desc *rxd; 79 struct rte_mbuf *m; 80 uint16_t port_id = rxq->dp.dpq.port_id; 81 82 free_space = rxq->max_fill_level - (added - rxq->completed); 83 84 if (free_space < rxq->refill_threshold) 85 return; 86 87 bulks = free_space / RTE_DIM(objs); 88 /* refill_threshold guarantees that bulks is positive */ 89 SFC_ASSERT(bulks > 0); 90 91 id = added & rxq->ptr_mask; 92 do { 93 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 94 RTE_DIM(objs)) < 0)) { 95 /* 96 * It is hardly a safe way to increment counter 97 * from different contexts, but all PMDs do it. 98 */ 99 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 100 RTE_DIM(objs); 101 /* Return if we have posted nothing yet */ 102 if (added == rxq->added) 103 return; 104 /* Push posted */ 105 break; 106 } 107 108 for (i = 0; i < RTE_DIM(objs); 109 ++i, id = (id + 1) & rxq->ptr_mask) { 110 m = objs[i]; 111 112 MBUF_RAW_ALLOC_CHECK(m); 113 114 rxd = &rxq->sw_desc[id]; 115 rxd->mbuf = m; 116 117 m->data_off = RTE_PKTMBUF_HEADROOM; 118 m->port = port_id; 119 120 addr[i] = rte_pktmbuf_iova(m); 121 } 122 123 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 124 RTE_DIM(objs), rxq->completed, added); 125 added += RTE_DIM(objs); 126 } while (--bulks > 0); 127 128 SFC_ASSERT(added != rxq->added); 129 rxq->added = added; 130 efx_rx_qpush(rxq->common, added, &rxq->pushed); 131 } 132 133 static uint64_t 134 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 135 { 136 uint64_t mbuf_flags = 0; 137 138 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 139 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 140 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; 141 break; 142 case EFX_PKT_IPV4: 143 mbuf_flags |= PKT_RX_IP_CKSUM_BAD; 144 break; 145 default: 146 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0); 147 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) == 148 PKT_RX_IP_CKSUM_UNKNOWN); 149 break; 150 } 151 152 switch ((desc_flags & 153 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 154 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 155 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 156 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; 157 break; 158 case EFX_PKT_TCP: 159 case EFX_PKT_UDP: 160 mbuf_flags |= PKT_RX_L4_CKSUM_BAD; 161 break; 162 default: 163 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0); 164 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) == 165 PKT_RX_L4_CKSUM_UNKNOWN); 166 break; 167 } 168 169 return mbuf_flags; 170 } 171 172 static uint32_t 173 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 174 { 175 return RTE_PTYPE_L2_ETHER | 176 ((desc_flags & EFX_PKT_IPV4) ? 177 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 178 ((desc_flags & EFX_PKT_IPV6) ? 179 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 180 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 181 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 182 } 183 184 static const uint32_t * 185 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps) 186 { 187 static const uint32_t ptypes[] = { 188 RTE_PTYPE_L2_ETHER, 189 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 190 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 191 RTE_PTYPE_L4_TCP, 192 RTE_PTYPE_L4_UDP, 193 RTE_PTYPE_UNKNOWN 194 }; 195 196 return ptypes; 197 } 198 199 static void 200 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 201 struct rte_mbuf *m) 202 { 203 uint8_t *mbuf_data; 204 205 206 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 207 return; 208 209 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 210 211 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 212 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 213 EFX_RX_HASHALG_TOEPLITZ, 214 mbuf_data); 215 216 m->ol_flags |= PKT_RX_RSS_HASH; 217 } 218 } 219 220 static uint16_t 221 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 222 { 223 struct sfc_dp_rxq *dp_rxq = rx_queue; 224 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 225 unsigned int completed; 226 unsigned int prefix_size = rxq->prefix_size; 227 unsigned int done_pkts = 0; 228 boolean_t discard_next = B_FALSE; 229 struct rte_mbuf *scatter_pkt = NULL; 230 231 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 232 return 0; 233 234 sfc_ev_qpoll(rxq->evq); 235 236 completed = rxq->completed; 237 while (completed != rxq->pending && done_pkts < nb_pkts) { 238 unsigned int id; 239 struct sfc_efx_rx_sw_desc *rxd; 240 struct rte_mbuf *m; 241 unsigned int seg_len; 242 unsigned int desc_flags; 243 244 id = completed++ & rxq->ptr_mask; 245 rxd = &rxq->sw_desc[id]; 246 m = rxd->mbuf; 247 desc_flags = rxd->flags; 248 249 if (discard_next) 250 goto discard; 251 252 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 253 goto discard; 254 255 if (desc_flags & EFX_PKT_PREFIX_LEN) { 256 uint16_t tmp_size; 257 int rc __rte_unused; 258 259 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 260 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 261 SFC_ASSERT(rc == 0); 262 seg_len = tmp_size; 263 } else { 264 seg_len = rxd->size - prefix_size; 265 } 266 267 rte_pktmbuf_data_len(m) = seg_len; 268 rte_pktmbuf_pkt_len(m) = seg_len; 269 270 if (scatter_pkt != NULL) { 271 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 272 rte_pktmbuf_free(scatter_pkt); 273 goto discard; 274 } 275 /* The packet to deliver */ 276 m = scatter_pkt; 277 } 278 279 if (desc_flags & EFX_PKT_CONT) { 280 /* The packet is scattered, more fragments to come */ 281 scatter_pkt = m; 282 /* Further fragments have no prefix */ 283 prefix_size = 0; 284 continue; 285 } 286 287 /* Scattered packet is done */ 288 scatter_pkt = NULL; 289 /* The first fragment of the packet has prefix */ 290 prefix_size = rxq->prefix_size; 291 292 m->ol_flags = 293 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 294 m->packet_type = 295 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 296 297 /* 298 * Extract RSS hash from the packet prefix and 299 * set the corresponding field (if needed and possible) 300 */ 301 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 302 303 m->data_off += prefix_size; 304 305 *rx_pkts++ = m; 306 done_pkts++; 307 continue; 308 309 discard: 310 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 311 rte_mbuf_raw_free(m); 312 rxd->mbuf = NULL; 313 } 314 315 /* pending is only moved when entire packet is received */ 316 SFC_ASSERT(scatter_pkt == NULL); 317 318 rxq->completed = completed; 319 320 sfc_efx_rx_qrefill(rxq); 321 322 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) 323 sfc_efx_rx_qprime(rxq); 324 325 return done_pkts; 326 } 327 328 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 329 static unsigned int 330 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 331 { 332 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 333 334 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 335 return 0; 336 337 sfc_ev_qpoll(rxq->evq); 338 339 return rxq->pending - rxq->completed; 340 } 341 342 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 343 static int 344 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 345 { 346 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 347 348 if (unlikely(offset > rxq->ptr_mask)) 349 return -EINVAL; 350 351 /* 352 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 353 * it is required for the queue to be running, but the 354 * check is omitted because API design assumes that it 355 * is the duty of the caller to satisfy all conditions 356 */ 357 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 358 SFC_EFX_RXQ_FLAG_RUNNING); 359 sfc_ev_qpoll(rxq->evq); 360 361 /* 362 * There is a handful of reserved entries in the ring, 363 * but an explicit check whether the offset points to 364 * a reserved entry is neglected since the two checks 365 * below rely on the figures which take the HW limits 366 * into account and thus if an entry is reserved, the 367 * checks will fail and UNAVAIL code will be returned 368 */ 369 370 if (offset < (rxq->pending - rxq->completed)) 371 return RTE_ETH_RX_DESC_DONE; 372 373 if (offset < (rxq->added - rxq->completed)) 374 return RTE_ETH_RX_DESC_AVAIL; 375 376 return RTE_ETH_RX_DESC_UNAVAIL; 377 } 378 379 boolean_t 380 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size, 381 boolean_t rx_scatter_enabled, const char **error) 382 { 383 if ((rx_buf_size < pdu + rx_prefix_size) && !rx_scatter_enabled) { 384 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small"; 385 return B_FALSE; 386 } 387 388 return B_TRUE; 389 } 390 391 /** Get Rx datapath ops by the datapath RxQ handle */ 392 const struct sfc_dp_rx * 393 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 394 { 395 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 396 struct rte_eth_dev *eth_dev; 397 struct sfc_adapter_priv *sap; 398 399 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 400 eth_dev = &rte_eth_devices[dpq->port_id]; 401 402 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 403 404 return sap->dp_rx; 405 } 406 407 struct sfc_rxq_info * 408 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 409 { 410 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 411 struct rte_eth_dev *eth_dev; 412 struct sfc_adapter_shared *sas; 413 414 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 415 eth_dev = &rte_eth_devices[dpq->port_id]; 416 417 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 418 419 SFC_ASSERT(dpq->queue_id < sas->rxq_count); 420 return &sas->rxq_info[dpq->queue_id]; 421 } 422 423 struct sfc_rxq * 424 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 425 { 426 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 427 struct rte_eth_dev *eth_dev; 428 struct sfc_adapter *sa; 429 430 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 431 eth_dev = &rte_eth_devices[dpq->port_id]; 432 433 sa = sfc_adapter_by_eth_dev(eth_dev); 434 435 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count); 436 return &sa->rxq_ctrl[dpq->queue_id]; 437 } 438 439 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 440 static int 441 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 442 __rte_unused struct sfc_dp_rx_hw_limits *limits, 443 __rte_unused struct rte_mempool *mb_pool, 444 unsigned int *rxq_entries, 445 unsigned int *evq_entries, 446 unsigned int *rxq_max_fill_level) 447 { 448 *rxq_entries = nb_rx_desc; 449 *evq_entries = nb_rx_desc; 450 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 451 return 0; 452 } 453 454 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 455 static int 456 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 457 const struct rte_pci_addr *pci_addr, int socket_id, 458 const struct sfc_dp_rx_qcreate_info *info, 459 struct sfc_dp_rxq **dp_rxqp) 460 { 461 struct sfc_efx_rxq *rxq; 462 int rc; 463 464 rc = ENOMEM; 465 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 466 RTE_CACHE_LINE_SIZE, socket_id); 467 if (rxq == NULL) 468 goto fail_rxq_alloc; 469 470 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 471 472 rc = ENOMEM; 473 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 474 info->rxq_entries, 475 sizeof(*rxq->sw_desc), 476 RTE_CACHE_LINE_SIZE, socket_id); 477 if (rxq->sw_desc == NULL) 478 goto fail_desc_alloc; 479 480 /* efx datapath is bound to efx control path */ 481 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 482 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 483 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 484 rxq->ptr_mask = info->rxq_entries - 1; 485 rxq->batch_max = info->batch_max; 486 rxq->prefix_size = info->prefix_size; 487 rxq->max_fill_level = info->max_fill_level; 488 rxq->refill_threshold = info->refill_threshold; 489 rxq->buf_size = info->buf_size; 490 rxq->refill_mb_pool = info->refill_mb_pool; 491 492 *dp_rxqp = &rxq->dp; 493 return 0; 494 495 fail_desc_alloc: 496 rte_free(rxq); 497 498 fail_rxq_alloc: 499 return rc; 500 } 501 502 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 503 static void 504 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 505 { 506 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 507 508 rte_free(rxq->sw_desc); 509 rte_free(rxq); 510 } 511 512 513 /* Use qstop and qstart functions in the case of qstart failure */ 514 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 515 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 516 517 518 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 519 static int 520 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 521 __rte_unused unsigned int evq_read_ptr) 522 { 523 /* libefx-based datapath is specific to libefx-based PMD */ 524 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 525 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 526 int rc; 527 528 rxq->common = crxq->common; 529 530 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 531 532 sfc_efx_rx_qrefill(rxq); 533 534 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 535 536 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) { 537 rc = sfc_efx_rx_qprime(rxq); 538 if (rc != 0) 539 goto fail_rx_qprime; 540 } 541 542 return 0; 543 544 fail_rx_qprime: 545 sfc_efx_rx_qstop(dp_rxq, NULL); 546 sfc_efx_rx_qpurge(dp_rxq); 547 return rc; 548 } 549 550 static void 551 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 552 __rte_unused unsigned int *evq_read_ptr) 553 { 554 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 555 556 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 557 558 /* libefx-based datapath is bound to libefx-based PMD and uses 559 * event queue structure directly. So, there is no necessity to 560 * return EvQ read pointer. 561 */ 562 } 563 564 static void 565 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 566 { 567 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 568 unsigned int i; 569 struct sfc_efx_rx_sw_desc *rxd; 570 571 for (i = rxq->completed; i != rxq->added; ++i) { 572 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 573 rte_mbuf_raw_free(rxd->mbuf); 574 rxd->mbuf = NULL; 575 /* Packed stream relies on 0 in inactive SW desc. 576 * Rx queue stop is not performance critical, so 577 * there is no harm to do it always. 578 */ 579 rxd->flags = 0; 580 rxd->size = 0; 581 } 582 583 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 584 } 585 586 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable; 587 static int 588 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq) 589 { 590 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 591 int rc = 0; 592 593 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN; 594 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) { 595 rc = sfc_efx_rx_qprime(rxq); 596 if (rc != 0) 597 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 598 } 599 return rc; 600 } 601 602 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable; 603 static int 604 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq) 605 { 606 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 607 608 /* Cannot disarm, just disable rearm */ 609 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 610 return 0; 611 } 612 613 struct sfc_dp_rx sfc_efx_rx = { 614 .dp = { 615 .name = SFC_KVARG_DATAPATH_EFX, 616 .type = SFC_DP_RX, 617 .hw_fw_caps = 0, 618 }, 619 .features = SFC_DP_RX_FEAT_INTR, 620 .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM, 621 .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER, 622 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 623 .qcreate = sfc_efx_rx_qcreate, 624 .qdestroy = sfc_efx_rx_qdestroy, 625 .qstart = sfc_efx_rx_qstart, 626 .qstop = sfc_efx_rx_qstop, 627 .qpurge = sfc_efx_rx_qpurge, 628 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 629 .qdesc_npending = sfc_efx_rx_qdesc_npending, 630 .qdesc_status = sfc_efx_rx_qdesc_status, 631 .intr_enable = sfc_efx_rx_intr_enable, 632 .intr_disable = sfc_efx_rx_intr_disable, 633 .pkt_burst = sfc_efx_recv_pkts, 634 }; 635 636 static void 637 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index) 638 { 639 struct sfc_rxq_info *rxq_info; 640 struct sfc_rxq *rxq; 641 unsigned int retry_count; 642 unsigned int wait_count; 643 int rc; 644 645 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 646 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 647 648 rxq = &sa->rxq_ctrl[sw_index]; 649 650 /* 651 * Retry Rx queue flushing in the case of flush failed or 652 * timeout. In the worst case it can delay for 6 seconds. 653 */ 654 for (retry_count = 0; 655 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) && 656 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 657 ++retry_count) { 658 rc = efx_rx_qflush(rxq->common); 659 if (rc != 0) { 660 rxq_info->state |= (rc == EALREADY) ? 661 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 662 break; 663 } 664 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED; 665 rxq_info->state |= SFC_RXQ_FLUSHING; 666 667 /* 668 * Wait for Rx queue flush done or failed event at least 669 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 670 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 671 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 672 */ 673 wait_count = 0; 674 do { 675 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 676 sfc_ev_qpoll(rxq->evq); 677 } while ((rxq_info->state & SFC_RXQ_FLUSHING) && 678 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 679 680 if (rxq_info->state & SFC_RXQ_FLUSHING) 681 sfc_err(sa, "RxQ %u flush timed out", sw_index); 682 683 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED) 684 sfc_err(sa, "RxQ %u flush failed", sw_index); 685 686 if (rxq_info->state & SFC_RXQ_FLUSHED) 687 sfc_notice(sa, "RxQ %u flushed", sw_index); 688 } 689 690 sa->priv.dp_rx->qpurge(rxq_info->dp); 691 } 692 693 static int 694 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 695 { 696 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 697 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 698 struct sfc_port *port = &sa->port; 699 int rc; 700 701 /* 702 * If promiscuous or all-multicast mode has been requested, setting 703 * filter for the default Rx queue might fail, in particular, while 704 * running over PCI function which is not a member of corresponding 705 * privilege groups; if this occurs, few iterations will be made to 706 * repeat this step without promiscuous and all-multicast flags set 707 */ 708 retry: 709 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 710 if (rc == 0) 711 return 0; 712 else if (rc != EOPNOTSUPP) 713 return rc; 714 715 if (port->promisc) { 716 sfc_warn(sa, "promiscuous mode has been requested, " 717 "but the HW rejects it"); 718 sfc_warn(sa, "promiscuous mode will be disabled"); 719 720 port->promisc = B_FALSE; 721 rc = sfc_set_rx_mode(sa); 722 if (rc != 0) 723 return rc; 724 725 goto retry; 726 } 727 728 if (port->allmulti) { 729 sfc_warn(sa, "all-multicast mode has been requested, " 730 "but the HW rejects it"); 731 sfc_warn(sa, "all-multicast mode will be disabled"); 732 733 port->allmulti = B_FALSE; 734 rc = sfc_set_rx_mode(sa); 735 if (rc != 0) 736 return rc; 737 738 goto retry; 739 } 740 741 return rc; 742 } 743 744 int 745 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index) 746 { 747 struct sfc_rxq_info *rxq_info; 748 struct sfc_rxq *rxq; 749 struct sfc_evq *evq; 750 int rc; 751 752 sfc_log_init(sa, "sw_index=%u", sw_index); 753 754 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 755 756 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 757 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 758 759 rxq = &sa->rxq_ctrl[sw_index]; 760 evq = rxq->evq; 761 762 rc = sfc_ev_qstart(evq, sfc_evq_index_by_rxq_sw_index(sa, sw_index)); 763 if (rc != 0) 764 goto fail_ev_qstart; 765 766 switch (rxq_info->type) { 767 case EFX_RXQ_TYPE_DEFAULT: 768 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 769 rxq->buf_size, 770 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 771 rxq_info->type_flags, evq->common, &rxq->common); 772 break; 773 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 774 struct rte_mempool *mp = rxq_info->refill_mb_pool; 775 struct rte_mempool_info mp_info; 776 777 rc = rte_mempool_ops_get_info(mp, &mp_info); 778 if (rc != 0) { 779 /* Positive errno is used in the driver */ 780 rc = -rc; 781 goto fail_mp_get_info; 782 } 783 if (mp_info.contig_block_size <= 0) { 784 rc = EINVAL; 785 goto fail_bad_contig_block_size; 786 } 787 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 788 mp_info.contig_block_size, rxq->buf_size, 789 mp->header_size + mp->elt_size + mp->trailer_size, 790 sa->rxd_wait_timeout_ns, 791 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 792 evq->common, &rxq->common); 793 break; 794 } 795 default: 796 rc = ENOTSUP; 797 } 798 if (rc != 0) 799 goto fail_rx_qcreate; 800 801 efx_rx_qenable(rxq->common); 802 803 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr); 804 if (rc != 0) 805 goto fail_dp_qstart; 806 807 rxq_info->state |= SFC_RXQ_STARTED; 808 809 if (sw_index == 0 && !sfc_sa2shared(sa)->isolated) { 810 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 811 if (rc != 0) 812 goto fail_mac_filter_default_rxq_set; 813 } 814 815 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 816 sa->eth_dev->data->rx_queue_state[sw_index] = 817 RTE_ETH_QUEUE_STATE_STARTED; 818 819 return 0; 820 821 fail_mac_filter_default_rxq_set: 822 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 823 824 fail_dp_qstart: 825 sfc_rx_qflush(sa, sw_index); 826 827 fail_rx_qcreate: 828 fail_bad_contig_block_size: 829 fail_mp_get_info: 830 sfc_ev_qstop(evq); 831 832 fail_ev_qstart: 833 return rc; 834 } 835 836 void 837 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index) 838 { 839 struct sfc_rxq_info *rxq_info; 840 struct sfc_rxq *rxq; 841 842 sfc_log_init(sa, "sw_index=%u", sw_index); 843 844 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 845 846 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 847 848 if (rxq_info->state == SFC_RXQ_INITIALIZED) 849 return; 850 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 851 852 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 853 sa->eth_dev->data->rx_queue_state[sw_index] = 854 RTE_ETH_QUEUE_STATE_STOPPED; 855 856 rxq = &sa->rxq_ctrl[sw_index]; 857 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 858 859 if (sw_index == 0) 860 efx_mac_filter_default_rxq_clear(sa->nic); 861 862 sfc_rx_qflush(sa, sw_index); 863 864 rxq_info->state = SFC_RXQ_INITIALIZED; 865 866 efx_rx_qdestroy(rxq->common); 867 868 sfc_ev_qstop(rxq->evq); 869 } 870 871 static uint64_t 872 sfc_rx_get_offload_mask(struct sfc_adapter *sa) 873 { 874 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 875 uint64_t no_caps = 0; 876 877 if (encp->enc_tunnel_encapsulations_supported == 0) 878 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 879 880 return ~no_caps; 881 } 882 883 uint64_t 884 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 885 { 886 uint64_t caps = sa->priv.dp_rx->dev_offload_capa; 887 888 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME; 889 890 return caps & sfc_rx_get_offload_mask(sa); 891 } 892 893 uint64_t 894 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 895 { 896 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa); 897 } 898 899 static int 900 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 901 const struct rte_eth_rxconf *rx_conf, 902 __rte_unused uint64_t offloads) 903 { 904 int rc = 0; 905 906 if (rx_conf->rx_thresh.pthresh != 0 || 907 rx_conf->rx_thresh.hthresh != 0 || 908 rx_conf->rx_thresh.wthresh != 0) { 909 sfc_warn(sa, 910 "RxQ prefetch/host/writeback thresholds are not supported"); 911 } 912 913 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 914 sfc_err(sa, 915 "RxQ free threshold too large: %u vs maximum %u", 916 rx_conf->rx_free_thresh, rxq_max_fill_level); 917 rc = EINVAL; 918 } 919 920 if (rx_conf->rx_drop_en == 0) { 921 sfc_err(sa, "RxQ drop disable is not supported"); 922 rc = EINVAL; 923 } 924 925 return rc; 926 } 927 928 static unsigned int 929 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 930 { 931 uint32_t data_off; 932 uint32_t order; 933 934 /* The mbuf object itself is always cache line aligned */ 935 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 936 937 /* Data offset from mbuf object start */ 938 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 939 RTE_PKTMBUF_HEADROOM; 940 941 order = MIN(order, rte_bsf32(data_off)); 942 943 return 1u << order; 944 } 945 946 static uint16_t 947 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 948 { 949 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 950 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 951 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 952 uint16_t buf_size; 953 unsigned int buf_aligned; 954 unsigned int start_alignment; 955 unsigned int end_padding_alignment; 956 957 /* Below it is assumed that both alignments are power of 2 */ 958 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 959 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 960 961 /* 962 * mbuf is always cache line aligned, double-check 963 * that it meets rx buffer start alignment requirements. 964 */ 965 966 /* Start from mbuf pool data room size */ 967 buf_size = rte_pktmbuf_data_room_size(mb_pool); 968 969 /* Remove headroom */ 970 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 971 sfc_err(sa, 972 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 973 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 974 return 0; 975 } 976 buf_size -= RTE_PKTMBUF_HEADROOM; 977 978 /* Calculate guaranteed data start alignment */ 979 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 980 981 /* Reserve space for start alignment */ 982 if (buf_aligned < nic_align_start) { 983 start_alignment = nic_align_start - buf_aligned; 984 if (buf_size <= start_alignment) { 985 sfc_err(sa, 986 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 987 mb_pool->name, 988 rte_pktmbuf_data_room_size(mb_pool), 989 RTE_PKTMBUF_HEADROOM, start_alignment); 990 return 0; 991 } 992 buf_aligned = nic_align_start; 993 buf_size -= start_alignment; 994 } else { 995 start_alignment = 0; 996 } 997 998 /* Make sure that end padding does not write beyond the buffer */ 999 if (buf_aligned < nic_align_end) { 1000 /* 1001 * Estimate space which can be lost. If guarnteed buffer 1002 * size is odd, lost space is (nic_align_end - 1). More 1003 * accurate formula is below. 1004 */ 1005 end_padding_alignment = nic_align_end - 1006 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 1007 if (buf_size <= end_padding_alignment) { 1008 sfc_err(sa, 1009 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 1010 mb_pool->name, 1011 rte_pktmbuf_data_room_size(mb_pool), 1012 RTE_PKTMBUF_HEADROOM, start_alignment, 1013 end_padding_alignment); 1014 return 0; 1015 } 1016 buf_size -= end_padding_alignment; 1017 } else { 1018 /* 1019 * Start is aligned the same or better than end, 1020 * just align length. 1021 */ 1022 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end); 1023 } 1024 1025 return buf_size; 1026 } 1027 1028 int 1029 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index, 1030 uint16_t nb_rx_desc, unsigned int socket_id, 1031 const struct rte_eth_rxconf *rx_conf, 1032 struct rte_mempool *mb_pool) 1033 { 1034 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1035 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1036 int rc; 1037 unsigned int rxq_entries; 1038 unsigned int evq_entries; 1039 unsigned int rxq_max_fill_level; 1040 uint64_t offloads; 1041 uint16_t buf_size; 1042 struct sfc_rxq_info *rxq_info; 1043 struct sfc_evq *evq; 1044 struct sfc_rxq *rxq; 1045 struct sfc_dp_rx_qcreate_info info; 1046 struct sfc_dp_rx_hw_limits hw_limits; 1047 uint16_t rx_free_thresh; 1048 const char *error; 1049 1050 memset(&hw_limits, 0, sizeof(hw_limits)); 1051 hw_limits.rxq_max_entries = sa->rxq_max_entries; 1052 hw_limits.rxq_min_entries = sa->rxq_min_entries; 1053 hw_limits.evq_max_entries = sa->evq_max_entries; 1054 hw_limits.evq_min_entries = sa->evq_min_entries; 1055 1056 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool, 1057 &rxq_entries, &evq_entries, 1058 &rxq_max_fill_level); 1059 if (rc != 0) 1060 goto fail_size_up_rings; 1061 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries); 1062 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries); 1063 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 1064 1065 offloads = rx_conf->offloads | 1066 sa->eth_dev->data->dev_conf.rxmode.offloads; 1067 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 1068 if (rc != 0) 1069 goto fail_bad_conf; 1070 1071 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 1072 if (buf_size == 0) { 1073 sfc_err(sa, "RxQ %u mbuf pool object size is too small", 1074 sw_index); 1075 rc = EINVAL; 1076 goto fail_bad_conf; 1077 } 1078 1079 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size, 1080 encp->enc_rx_prefix_size, 1081 (offloads & DEV_RX_OFFLOAD_SCATTER), 1082 &error)) { 1083 sfc_err(sa, "RxQ %u MTU check failed: %s", sw_index, error); 1084 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs " 1085 "PDU size %u plus Rx prefix %u bytes", 1086 sw_index, buf_size, (unsigned int)sa->port.pdu, 1087 encp->enc_rx_prefix_size); 1088 rc = EINVAL; 1089 goto fail_bad_conf; 1090 } 1091 1092 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1093 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1094 1095 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1096 rxq_info->entries = rxq_entries; 1097 1098 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1099 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1100 else 1101 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1102 1103 rxq_info->type_flags = 1104 (offloads & DEV_RX_OFFLOAD_SCATTER) ? 1105 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1106 1107 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1108 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) & 1109 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0) 1110 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1111 1112 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1113 evq_entries, socket_id, &evq); 1114 if (rc != 0) 1115 goto fail_ev_qinit; 1116 1117 rxq = &sa->rxq_ctrl[sw_index]; 1118 rxq->evq = evq; 1119 rxq->hw_index = sw_index; 1120 /* 1121 * If Rx refill threshold is specified (its value is non zero) in 1122 * Rx configuration, use specified value. Otherwise use 1/8 of 1123 * the Rx descriptors number as the default. It allows to keep 1124 * Rx ring full-enough and does not refill too aggressive if 1125 * packet rate is high. 1126 * 1127 * Since PMD refills in bulks waiting for full bulk may be 1128 * refilled (basically round down), it is better to round up 1129 * here to mitigate it a bit. 1130 */ 1131 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ? 1132 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8); 1133 /* Rx refill threshold cannot be smaller than refill bulk */ 1134 rxq_info->refill_threshold = 1135 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK); 1136 rxq_info->refill_mb_pool = mb_pool; 1137 rxq->buf_size = buf_size; 1138 1139 rc = sfc_dma_alloc(sa, "rxq", sw_index, 1140 efx_rxq_size(sa->nic, rxq_info->entries), 1141 socket_id, &rxq->mem); 1142 if (rc != 0) 1143 goto fail_dma_alloc; 1144 1145 memset(&info, 0, sizeof(info)); 1146 info.refill_mb_pool = rxq_info->refill_mb_pool; 1147 info.max_fill_level = rxq_max_fill_level; 1148 info.refill_threshold = rxq_info->refill_threshold; 1149 info.buf_size = buf_size; 1150 info.batch_max = encp->enc_rx_batch_max; 1151 info.prefix_size = encp->enc_rx_prefix_size; 1152 1153 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0) 1154 info.flags |= SFC_RXQ_FLAG_RSS_HASH; 1155 1156 info.rxq_entries = rxq_info->entries; 1157 info.rxq_hw_ring = rxq->mem.esm_base; 1158 info.evq_hw_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index); 1159 info.evq_entries = evq_entries; 1160 info.evq_hw_ring = evq->mem.esm_base; 1161 info.hw_index = rxq->hw_index; 1162 info.mem_bar = sa->mem_bar.esb_base; 1163 info.vi_window_shift = encp->enc_vi_window_shift; 1164 1165 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1166 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1167 socket_id, &info, &rxq_info->dp); 1168 if (rc != 0) 1169 goto fail_dp_rx_qcreate; 1170 1171 evq->dp_rxq = rxq_info->dp; 1172 1173 rxq_info->state = SFC_RXQ_INITIALIZED; 1174 1175 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1176 1177 return 0; 1178 1179 fail_dp_rx_qcreate: 1180 sfc_dma_free(sa, &rxq->mem); 1181 1182 fail_dma_alloc: 1183 sfc_ev_qfini(evq); 1184 1185 fail_ev_qinit: 1186 rxq_info->entries = 0; 1187 1188 fail_bad_conf: 1189 fail_size_up_rings: 1190 sfc_log_init(sa, "failed %d", rc); 1191 return rc; 1192 } 1193 1194 void 1195 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index) 1196 { 1197 struct sfc_rxq_info *rxq_info; 1198 struct sfc_rxq *rxq; 1199 1200 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1201 sa->eth_dev->data->rx_queues[sw_index] = NULL; 1202 1203 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1204 1205 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 1206 1207 sa->priv.dp_rx->qdestroy(rxq_info->dp); 1208 rxq_info->dp = NULL; 1209 1210 rxq_info->state &= ~SFC_RXQ_INITIALIZED; 1211 rxq_info->entries = 0; 1212 1213 rxq = &sa->rxq_ctrl[sw_index]; 1214 1215 sfc_dma_free(sa, &rxq->mem); 1216 1217 sfc_ev_qfini(rxq->evq); 1218 rxq->evq = NULL; 1219 } 1220 1221 /* 1222 * Mapping between RTE RSS hash functions and their EFX counterparts. 1223 */ 1224 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1225 { ETH_RSS_NONFRAG_IPV4_TCP, 1226 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1227 { ETH_RSS_NONFRAG_IPV4_UDP, 1228 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1229 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX, 1230 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1231 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX, 1232 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1233 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER, 1234 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1235 EFX_RX_HASH(IPV4, 2TUPLE) }, 1236 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER | 1237 ETH_RSS_IPV6_EX, 1238 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1239 EFX_RX_HASH(IPV6, 2TUPLE) } 1240 }; 1241 1242 static efx_rx_hash_type_t 1243 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1244 unsigned int *hash_type_flags_supported, 1245 unsigned int nb_hash_type_flags_supported) 1246 { 1247 efx_rx_hash_type_t hash_type_masked = 0; 1248 unsigned int i, j; 1249 1250 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1251 unsigned int class_tuple_lbn[] = { 1252 EFX_RX_CLASS_IPV4_TCP_LBN, 1253 EFX_RX_CLASS_IPV4_UDP_LBN, 1254 EFX_RX_CLASS_IPV4_LBN, 1255 EFX_RX_CLASS_IPV6_TCP_LBN, 1256 EFX_RX_CLASS_IPV6_UDP_LBN, 1257 EFX_RX_CLASS_IPV6_LBN 1258 }; 1259 1260 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1261 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1262 unsigned int flag; 1263 1264 tuple_mask <<= class_tuple_lbn[j]; 1265 flag = hash_type & tuple_mask; 1266 1267 if (flag == hash_type_flags_supported[i]) 1268 hash_type_masked |= flag; 1269 } 1270 } 1271 1272 return hash_type_masked; 1273 } 1274 1275 int 1276 sfc_rx_hash_init(struct sfc_adapter *sa) 1277 { 1278 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1279 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1280 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1281 efx_rx_hash_alg_t alg; 1282 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1283 unsigned int nb_flags_supp; 1284 struct sfc_rss_hf_rte_to_efx *hf_map; 1285 struct sfc_rss_hf_rte_to_efx *entry; 1286 efx_rx_hash_type_t efx_hash_types; 1287 unsigned int i; 1288 int rc; 1289 1290 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1291 alg = EFX_RX_HASHALG_TOEPLITZ; 1292 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1293 alg = EFX_RX_HASHALG_PACKED_STREAM; 1294 else 1295 return EINVAL; 1296 1297 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1298 RTE_DIM(flags_supp), &nb_flags_supp); 1299 if (rc != 0) 1300 return rc; 1301 1302 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1303 RTE_DIM(sfc_rss_hf_map), 1304 sizeof(*hf_map), 0, sa->socket_id); 1305 if (hf_map == NULL) 1306 return ENOMEM; 1307 1308 entry = hf_map; 1309 efx_hash_types = 0; 1310 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1311 efx_rx_hash_type_t ht; 1312 1313 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1314 flags_supp, nb_flags_supp); 1315 if (ht != 0) { 1316 entry->rte = sfc_rss_hf_map[i].rte; 1317 entry->efx = ht; 1318 efx_hash_types |= ht; 1319 ++entry; 1320 } 1321 } 1322 1323 rss->hash_alg = alg; 1324 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1325 rss->hf_map = hf_map; 1326 rss->hash_types = efx_hash_types; 1327 1328 return 0; 1329 } 1330 1331 void 1332 sfc_rx_hash_fini(struct sfc_adapter *sa) 1333 { 1334 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1335 1336 rte_free(rss->hf_map); 1337 } 1338 1339 int 1340 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1341 efx_rx_hash_type_t *efx) 1342 { 1343 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1344 efx_rx_hash_type_t hash_types = 0; 1345 unsigned int i; 1346 1347 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1348 uint64_t rte_mask = rss->hf_map[i].rte; 1349 1350 if ((rte & rte_mask) != 0) { 1351 rte &= ~rte_mask; 1352 hash_types |= rss->hf_map[i].efx; 1353 } 1354 } 1355 1356 if (rte != 0) { 1357 sfc_err(sa, "unsupported hash functions requested"); 1358 return EINVAL; 1359 } 1360 1361 *efx = hash_types; 1362 1363 return 0; 1364 } 1365 1366 uint64_t 1367 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx) 1368 { 1369 uint64_t rte = 0; 1370 unsigned int i; 1371 1372 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1373 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1374 1375 if ((efx & hash_type) == hash_type) 1376 rte |= rss->hf_map[i].rte; 1377 } 1378 1379 return rte; 1380 } 1381 1382 static int 1383 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1384 struct rte_eth_rss_conf *conf) 1385 { 1386 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1387 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1388 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types); 1389 int rc; 1390 1391 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1392 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1393 conf->rss_key != NULL) 1394 return EINVAL; 1395 } 1396 1397 if (conf->rss_hf != 0) { 1398 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1399 if (rc != 0) 1400 return rc; 1401 } 1402 1403 if (conf->rss_key != NULL) { 1404 if (conf->rss_key_len != sizeof(rss->key)) { 1405 sfc_err(sa, "RSS key size is wrong (should be %lu)", 1406 sizeof(rss->key)); 1407 return EINVAL; 1408 } 1409 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1410 } 1411 1412 rss->hash_types = efx_hash_types; 1413 1414 return 0; 1415 } 1416 1417 static int 1418 sfc_rx_rss_config(struct sfc_adapter *sa) 1419 { 1420 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1421 int rc = 0; 1422 1423 if (rss->channels > 0) { 1424 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1425 rss->hash_alg, rss->hash_types, 1426 B_TRUE); 1427 if (rc != 0) 1428 goto finish; 1429 1430 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1431 rss->key, sizeof(rss->key)); 1432 if (rc != 0) 1433 goto finish; 1434 1435 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1436 rss->tbl, RTE_DIM(rss->tbl)); 1437 } 1438 1439 finish: 1440 return rc; 1441 } 1442 1443 int 1444 sfc_rx_start(struct sfc_adapter *sa) 1445 { 1446 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1447 unsigned int sw_index; 1448 int rc; 1449 1450 sfc_log_init(sa, "rxq_count=%u", sas->rxq_count); 1451 1452 rc = efx_rx_init(sa->nic); 1453 if (rc != 0) 1454 goto fail_rx_init; 1455 1456 rc = sfc_rx_rss_config(sa); 1457 if (rc != 0) 1458 goto fail_rss_config; 1459 1460 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) { 1461 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED && 1462 (!sas->rxq_info[sw_index].deferred_start || 1463 sas->rxq_info[sw_index].deferred_started)) { 1464 rc = sfc_rx_qstart(sa, sw_index); 1465 if (rc != 0) 1466 goto fail_rx_qstart; 1467 } 1468 } 1469 1470 return 0; 1471 1472 fail_rx_qstart: 1473 while (sw_index-- > 0) 1474 sfc_rx_qstop(sa, sw_index); 1475 1476 fail_rss_config: 1477 efx_rx_fini(sa->nic); 1478 1479 fail_rx_init: 1480 sfc_log_init(sa, "failed %d", rc); 1481 return rc; 1482 } 1483 1484 void 1485 sfc_rx_stop(struct sfc_adapter *sa) 1486 { 1487 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1488 unsigned int sw_index; 1489 1490 sfc_log_init(sa, "rxq_count=%u", sas->rxq_count); 1491 1492 sw_index = sas->rxq_count; 1493 while (sw_index-- > 0) { 1494 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED) 1495 sfc_rx_qstop(sa, sw_index); 1496 } 1497 1498 efx_rx_fini(sa->nic); 1499 } 1500 1501 static int 1502 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index) 1503 { 1504 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1505 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index]; 1506 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1507 unsigned int max_entries; 1508 1509 max_entries = encp->enc_rxq_max_ndescs; 1510 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1511 1512 rxq_info->max_entries = max_entries; 1513 1514 return 0; 1515 } 1516 1517 static int 1518 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1519 { 1520 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1521 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1522 sfc_rx_get_queue_offload_caps(sa); 1523 struct sfc_rss *rss = &sas->rss; 1524 int rc = 0; 1525 1526 switch (rxmode->mq_mode) { 1527 case ETH_MQ_RX_NONE: 1528 /* No special checks are required */ 1529 break; 1530 case ETH_MQ_RX_RSS: 1531 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1532 sfc_err(sa, "RSS is not available"); 1533 rc = EINVAL; 1534 } 1535 break; 1536 default: 1537 sfc_err(sa, "Rx multi-queue mode %u not supported", 1538 rxmode->mq_mode); 1539 rc = EINVAL; 1540 } 1541 1542 /* 1543 * Requested offloads are validated against supported by ethdev, 1544 * so unsupported offloads cannot be added as the result of 1545 * below check. 1546 */ 1547 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) != 1548 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) { 1549 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1550 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM; 1551 } 1552 1553 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1554 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1555 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1556 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1557 } 1558 1559 return rc; 1560 } 1561 1562 /** 1563 * Destroy excess queues that are no longer needed after reconfiguration 1564 * or complete close. 1565 */ 1566 static void 1567 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1568 { 1569 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1570 int sw_index; 1571 1572 SFC_ASSERT(nb_rx_queues <= sas->rxq_count); 1573 1574 sw_index = sas->rxq_count; 1575 while (--sw_index >= (int)nb_rx_queues) { 1576 if (sas->rxq_info[sw_index].state & SFC_RXQ_INITIALIZED) 1577 sfc_rx_qfini(sa, sw_index); 1578 } 1579 1580 sas->rxq_count = nb_rx_queues; 1581 } 1582 1583 /** 1584 * Initialize Rx subsystem. 1585 * 1586 * Called at device (re)configuration stage when number of receive queues is 1587 * specified together with other device level receive configuration. 1588 * 1589 * It should be used to allocate NUMA-unaware resources. 1590 */ 1591 int 1592 sfc_rx_configure(struct sfc_adapter *sa) 1593 { 1594 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1595 struct sfc_rss *rss = &sas->rss; 1596 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1597 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1598 int rc; 1599 1600 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1601 nb_rx_queues, sas->rxq_count); 1602 1603 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1604 if (rc != 0) 1605 goto fail_check_mode; 1606 1607 if (nb_rx_queues == sas->rxq_count) 1608 goto configure_rss; 1609 1610 if (sas->rxq_info == NULL) { 1611 rc = ENOMEM; 1612 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rx_queues, 1613 sizeof(sas->rxq_info[0]), 0, 1614 sa->socket_id); 1615 if (sas->rxq_info == NULL) 1616 goto fail_rxqs_alloc; 1617 1618 /* 1619 * Allocate primary process only RxQ control from heap 1620 * since it should not be shared. 1621 */ 1622 rc = ENOMEM; 1623 sa->rxq_ctrl = calloc(nb_rx_queues, sizeof(sa->rxq_ctrl[0])); 1624 if (sa->rxq_ctrl == NULL) 1625 goto fail_rxqs_ctrl_alloc; 1626 } else { 1627 struct sfc_rxq_info *new_rxq_info; 1628 struct sfc_rxq *new_rxq_ctrl; 1629 1630 if (nb_rx_queues < sas->rxq_count) 1631 sfc_rx_fini_queues(sa, nb_rx_queues); 1632 1633 rc = ENOMEM; 1634 new_rxq_info = 1635 rte_realloc(sas->rxq_info, 1636 nb_rx_queues * sizeof(sas->rxq_info[0]), 0); 1637 if (new_rxq_info == NULL && nb_rx_queues > 0) 1638 goto fail_rxqs_realloc; 1639 1640 rc = ENOMEM; 1641 new_rxq_ctrl = realloc(sa->rxq_ctrl, 1642 nb_rx_queues * sizeof(sa->rxq_ctrl[0])); 1643 if (new_rxq_ctrl == NULL && nb_rx_queues > 0) 1644 goto fail_rxqs_ctrl_realloc; 1645 1646 sas->rxq_info = new_rxq_info; 1647 sa->rxq_ctrl = new_rxq_ctrl; 1648 if (nb_rx_queues > sas->rxq_count) { 1649 memset(&sas->rxq_info[sas->rxq_count], 0, 1650 (nb_rx_queues - sas->rxq_count) * 1651 sizeof(sas->rxq_info[0])); 1652 memset(&sa->rxq_ctrl[sas->rxq_count], 0, 1653 (nb_rx_queues - sas->rxq_count) * 1654 sizeof(sa->rxq_ctrl[0])); 1655 } 1656 } 1657 1658 while (sas->rxq_count < nb_rx_queues) { 1659 rc = sfc_rx_qinit_info(sa, sas->rxq_count); 1660 if (rc != 0) 1661 goto fail_rx_qinit_info; 1662 1663 sas->rxq_count++; 1664 } 1665 1666 configure_rss: 1667 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ? 1668 MIN(sas->rxq_count, EFX_MAXRSS) : 0; 1669 1670 if (rss->channels > 0) { 1671 struct rte_eth_rss_conf *adv_conf_rss; 1672 unsigned int sw_index; 1673 1674 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1675 rss->tbl[sw_index] = sw_index % rss->channels; 1676 1677 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1678 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1679 if (rc != 0) 1680 goto fail_rx_process_adv_conf_rss; 1681 } 1682 1683 return 0; 1684 1685 fail_rx_process_adv_conf_rss: 1686 fail_rx_qinit_info: 1687 fail_rxqs_ctrl_realloc: 1688 fail_rxqs_realloc: 1689 fail_rxqs_ctrl_alloc: 1690 fail_rxqs_alloc: 1691 sfc_rx_close(sa); 1692 1693 fail_check_mode: 1694 sfc_log_init(sa, "failed %d", rc); 1695 return rc; 1696 } 1697 1698 /** 1699 * Shutdown Rx subsystem. 1700 * 1701 * Called at device close stage, for example, before device shutdown. 1702 */ 1703 void 1704 sfc_rx_close(struct sfc_adapter *sa) 1705 { 1706 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1707 1708 sfc_rx_fini_queues(sa, 0); 1709 1710 rss->channels = 0; 1711 1712 free(sa->rxq_ctrl); 1713 sa->rxq_ctrl = NULL; 1714 1715 rte_free(sfc_sa2shared(sa)->rxq_info); 1716 sfc_sa2shared(sa)->rxq_info = NULL; 1717 } 1718