1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2016-2019 Solarflare Communications Inc. 5 * 6 * This software was jointly developed between OKTET Labs (under contract 7 * for Solarflare) and Solarflare Communications, Inc. 8 */ 9 10 #include <rte_mempool.h> 11 12 #include "efx.h" 13 14 #include "sfc.h" 15 #include "sfc_debug.h" 16 #include "sfc_flow_tunnel.h" 17 #include "sfc_log.h" 18 #include "sfc_ev.h" 19 #include "sfc_rx.h" 20 #include "sfc_mae_counter.h" 21 #include "sfc_kvargs.h" 22 #include "sfc_tweak.h" 23 24 /* 25 * Maximum number of Rx queue flush attempt in the case of failure or 26 * flush timeout 27 */ 28 #define SFC_RX_QFLUSH_ATTEMPTS (3) 29 30 /* 31 * Time to wait between event queue polling attempts when waiting for Rx 32 * queue flush done or failed events. 33 */ 34 #define SFC_RX_QFLUSH_POLL_WAIT_MS (1) 35 36 /* 37 * Maximum number of event queue polling attempts when waiting for Rx queue 38 * flush done or failed events. It defines Rx queue flush attempt timeout 39 * together with SFC_RX_QFLUSH_POLL_WAIT_MS. 40 */ 41 #define SFC_RX_QFLUSH_POLL_ATTEMPTS (2000) 42 43 void 44 sfc_rx_qflush_done(struct sfc_rxq_info *rxq_info) 45 { 46 rxq_info->state |= SFC_RXQ_FLUSHED; 47 rxq_info->state &= ~SFC_RXQ_FLUSHING; 48 } 49 50 void 51 sfc_rx_qflush_failed(struct sfc_rxq_info *rxq_info) 52 { 53 rxq_info->state |= SFC_RXQ_FLUSH_FAILED; 54 rxq_info->state &= ~SFC_RXQ_FLUSHING; 55 } 56 57 /* This returns the running counter, which is not bounded by ring size */ 58 unsigned int 59 sfc_rx_get_pushed(struct sfc_adapter *sa, struct sfc_dp_rxq *dp_rxq) 60 { 61 SFC_ASSERT(sa->priv.dp_rx->get_pushed != NULL); 62 63 return sa->priv.dp_rx->get_pushed(dp_rxq); 64 } 65 66 static int 67 sfc_efx_rx_qprime(struct sfc_efx_rxq *rxq) 68 { 69 int rc = 0; 70 71 if (rxq->evq->read_ptr_primed != rxq->evq->read_ptr) { 72 rc = efx_ev_qprime(rxq->evq->common, rxq->evq->read_ptr); 73 if (rc == 0) 74 rxq->evq->read_ptr_primed = rxq->evq->read_ptr; 75 } 76 return rc; 77 } 78 79 static void 80 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq) 81 { 82 unsigned int free_space; 83 unsigned int bulks; 84 void *objs[SFC_RX_REFILL_BULK]; 85 efsys_dma_addr_t addr[RTE_DIM(objs)]; 86 unsigned int added = rxq->added; 87 unsigned int id; 88 unsigned int i; 89 struct sfc_efx_rx_sw_desc *rxd; 90 struct rte_mbuf *m; 91 uint16_t port_id = rxq->dp.dpq.port_id; 92 93 free_space = rxq->max_fill_level - (added - rxq->completed); 94 95 if (free_space < rxq->refill_threshold) 96 return; 97 98 bulks = free_space / RTE_DIM(objs); 99 /* refill_threshold guarantees that bulks is positive */ 100 SFC_ASSERT(bulks > 0); 101 102 id = added & rxq->ptr_mask; 103 do { 104 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs, 105 RTE_DIM(objs)) < 0)) { 106 /* 107 * It is hardly a safe way to increment counter 108 * from different contexts, but all PMDs do it. 109 */ 110 rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed += 111 RTE_DIM(objs); 112 /* Return if we have posted nothing yet */ 113 if (added == rxq->added) 114 return; 115 /* Push posted */ 116 break; 117 } 118 119 for (i = 0; i < RTE_DIM(objs); 120 ++i, id = (id + 1) & rxq->ptr_mask) { 121 m = objs[i]; 122 123 __rte_mbuf_raw_sanity_check(m); 124 125 rxd = &rxq->sw_desc[id]; 126 rxd->mbuf = m; 127 128 m->data_off = RTE_PKTMBUF_HEADROOM; 129 m->port = port_id; 130 131 addr[i] = rte_pktmbuf_iova(m); 132 } 133 134 efx_rx_qpost(rxq->common, addr, rxq->buf_size, 135 RTE_DIM(objs), rxq->completed, added); 136 added += RTE_DIM(objs); 137 } while (--bulks > 0); 138 139 SFC_ASSERT(added != rxq->added); 140 rxq->added = added; 141 efx_rx_qpush(rxq->common, added, &rxq->pushed); 142 rxq->dp.dpq.rx_dbells++; 143 } 144 145 static uint64_t 146 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags) 147 { 148 uint64_t mbuf_flags = 0; 149 150 switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) { 151 case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4): 152 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; 153 break; 154 case EFX_PKT_IPV4: 155 mbuf_flags |= PKT_RX_IP_CKSUM_BAD; 156 break; 157 default: 158 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0); 159 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) == 160 PKT_RX_IP_CKSUM_UNKNOWN); 161 break; 162 } 163 164 switch ((desc_flags & 165 (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) { 166 case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP): 167 case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP): 168 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; 169 break; 170 case EFX_PKT_TCP: 171 case EFX_PKT_UDP: 172 mbuf_flags |= PKT_RX_L4_CKSUM_BAD; 173 break; 174 default: 175 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0); 176 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) == 177 PKT_RX_L4_CKSUM_UNKNOWN); 178 break; 179 } 180 181 return mbuf_flags; 182 } 183 184 static uint32_t 185 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags) 186 { 187 return RTE_PTYPE_L2_ETHER | 188 ((desc_flags & EFX_PKT_IPV4) ? 189 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) | 190 ((desc_flags & EFX_PKT_IPV6) ? 191 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) | 192 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) | 193 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0); 194 } 195 196 static const uint32_t * 197 sfc_efx_supported_ptypes_get(__rte_unused uint32_t tunnel_encaps) 198 { 199 static const uint32_t ptypes[] = { 200 RTE_PTYPE_L2_ETHER, 201 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 202 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 203 RTE_PTYPE_L4_TCP, 204 RTE_PTYPE_L4_UDP, 205 RTE_PTYPE_UNKNOWN 206 }; 207 208 return ptypes; 209 } 210 211 static void 212 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags, 213 struct rte_mbuf *m) 214 { 215 uint8_t *mbuf_data; 216 217 218 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0) 219 return; 220 221 mbuf_data = rte_pktmbuf_mtod(m, uint8_t *); 222 223 if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) { 224 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common, 225 EFX_RX_HASHALG_TOEPLITZ, 226 mbuf_data); 227 228 m->ol_flags |= PKT_RX_RSS_HASH; 229 } 230 } 231 232 static uint16_t 233 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 234 { 235 struct sfc_dp_rxq *dp_rxq = rx_queue; 236 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 237 unsigned int completed; 238 unsigned int prefix_size = rxq->prefix_size; 239 unsigned int done_pkts = 0; 240 boolean_t discard_next = B_FALSE; 241 struct rte_mbuf *scatter_pkt = NULL; 242 243 if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)) 244 return 0; 245 246 sfc_ev_qpoll(rxq->evq); 247 248 completed = rxq->completed; 249 while (completed != rxq->pending && done_pkts < nb_pkts) { 250 unsigned int id; 251 struct sfc_efx_rx_sw_desc *rxd; 252 struct rte_mbuf *m; 253 unsigned int seg_len; 254 unsigned int desc_flags; 255 256 id = completed++ & rxq->ptr_mask; 257 rxd = &rxq->sw_desc[id]; 258 m = rxd->mbuf; 259 desc_flags = rxd->flags; 260 261 if (discard_next) 262 goto discard; 263 264 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD)) 265 goto discard; 266 267 if (desc_flags & EFX_PKT_PREFIX_LEN) { 268 uint16_t tmp_size; 269 int rc __rte_unused; 270 271 rc = efx_pseudo_hdr_pkt_length_get(rxq->common, 272 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size); 273 SFC_ASSERT(rc == 0); 274 seg_len = tmp_size; 275 } else { 276 seg_len = rxd->size - prefix_size; 277 } 278 279 rte_pktmbuf_data_len(m) = seg_len; 280 rte_pktmbuf_pkt_len(m) = seg_len; 281 282 if (scatter_pkt != NULL) { 283 if (rte_pktmbuf_chain(scatter_pkt, m) != 0) { 284 rte_pktmbuf_free(scatter_pkt); 285 goto discard; 286 } 287 /* The packet to deliver */ 288 m = scatter_pkt; 289 } 290 291 if (desc_flags & EFX_PKT_CONT) { 292 /* The packet is scattered, more fragments to come */ 293 scatter_pkt = m; 294 /* Further fragments have no prefix */ 295 prefix_size = 0; 296 continue; 297 } 298 299 /* Scattered packet is done */ 300 scatter_pkt = NULL; 301 /* The first fragment of the packet has prefix */ 302 prefix_size = rxq->prefix_size; 303 304 m->ol_flags = 305 sfc_efx_rx_desc_flags_to_offload_flags(desc_flags); 306 m->packet_type = 307 sfc_efx_rx_desc_flags_to_packet_type(desc_flags); 308 309 /* 310 * Extract RSS hash from the packet prefix and 311 * set the corresponding field (if needed and possible) 312 */ 313 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m); 314 315 m->data_off += prefix_size; 316 317 *rx_pkts++ = m; 318 done_pkts++; 319 continue; 320 321 discard: 322 discard_next = ((desc_flags & EFX_PKT_CONT) != 0); 323 rte_mbuf_raw_free(m); 324 rxd->mbuf = NULL; 325 } 326 327 /* pending is only moved when entire packet is received */ 328 SFC_ASSERT(scatter_pkt == NULL); 329 330 rxq->completed = completed; 331 332 sfc_efx_rx_qrefill(rxq); 333 334 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) 335 sfc_efx_rx_qprime(rxq); 336 337 return done_pkts; 338 } 339 340 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending; 341 static unsigned int 342 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq) 343 { 344 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 345 346 if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0) 347 return 0; 348 349 sfc_ev_qpoll(rxq->evq); 350 351 return rxq->pending - rxq->completed; 352 } 353 354 static sfc_dp_rx_qdesc_status_t sfc_efx_rx_qdesc_status; 355 static int 356 sfc_efx_rx_qdesc_status(struct sfc_dp_rxq *dp_rxq, uint16_t offset) 357 { 358 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 359 360 if (unlikely(offset > rxq->ptr_mask)) 361 return -EINVAL; 362 363 /* 364 * Poll EvQ to derive up-to-date 'rxq->pending' figure; 365 * it is required for the queue to be running, but the 366 * check is omitted because API design assumes that it 367 * is the duty of the caller to satisfy all conditions 368 */ 369 SFC_ASSERT((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 370 SFC_EFX_RXQ_FLAG_RUNNING); 371 sfc_ev_qpoll(rxq->evq); 372 373 /* 374 * There is a handful of reserved entries in the ring, 375 * but an explicit check whether the offset points to 376 * a reserved entry is neglected since the two checks 377 * below rely on the figures which take the HW limits 378 * into account and thus if an entry is reserved, the 379 * checks will fail and UNAVAIL code will be returned 380 */ 381 382 if (offset < (rxq->pending - rxq->completed)) 383 return RTE_ETH_RX_DESC_DONE; 384 385 if (offset < (rxq->added - rxq->completed)) 386 return RTE_ETH_RX_DESC_AVAIL; 387 388 return RTE_ETH_RX_DESC_UNAVAIL; 389 } 390 391 boolean_t 392 sfc_rx_check_scatter(size_t pdu, size_t rx_buf_size, uint32_t rx_prefix_size, 393 boolean_t rx_scatter_enabled, uint32_t rx_scatter_max, 394 const char **error) 395 { 396 uint32_t effective_rx_scatter_max; 397 uint32_t rx_scatter_bufs; 398 399 effective_rx_scatter_max = rx_scatter_enabled ? rx_scatter_max : 1; 400 rx_scatter_bufs = EFX_DIV_ROUND_UP(pdu + rx_prefix_size, rx_buf_size); 401 402 if (rx_scatter_bufs > effective_rx_scatter_max) { 403 if (rx_scatter_enabled) 404 *error = "Possible number of Rx scatter buffers exceeds maximum number"; 405 else 406 *error = "Rx scatter is disabled and RxQ mbuf pool object size is too small"; 407 return B_FALSE; 408 } 409 410 return B_TRUE; 411 } 412 413 /** Get Rx datapath ops by the datapath RxQ handle */ 414 const struct sfc_dp_rx * 415 sfc_dp_rx_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 416 { 417 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 418 struct rte_eth_dev *eth_dev; 419 struct sfc_adapter_priv *sap; 420 421 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 422 eth_dev = &rte_eth_devices[dpq->port_id]; 423 424 sap = sfc_adapter_priv_by_eth_dev(eth_dev); 425 426 return sap->dp_rx; 427 } 428 429 struct sfc_rxq_info * 430 sfc_rxq_info_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 431 { 432 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 433 struct rte_eth_dev *eth_dev; 434 struct sfc_adapter_shared *sas; 435 436 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 437 eth_dev = &rte_eth_devices[dpq->port_id]; 438 439 sas = sfc_adapter_shared_by_eth_dev(eth_dev); 440 441 SFC_ASSERT(dpq->queue_id < sas->rxq_count); 442 return &sas->rxq_info[dpq->queue_id]; 443 } 444 445 struct sfc_rxq * 446 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq) 447 { 448 const struct sfc_dp_queue *dpq = &dp_rxq->dpq; 449 struct rte_eth_dev *eth_dev; 450 struct sfc_adapter *sa; 451 452 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id)); 453 eth_dev = &rte_eth_devices[dpq->port_id]; 454 455 sa = sfc_adapter_by_eth_dev(eth_dev); 456 457 SFC_ASSERT(dpq->queue_id < sfc_sa2shared(sa)->rxq_count); 458 return &sa->rxq_ctrl[dpq->queue_id]; 459 } 460 461 static sfc_dp_rx_qsize_up_rings_t sfc_efx_rx_qsize_up_rings; 462 static int 463 sfc_efx_rx_qsize_up_rings(uint16_t nb_rx_desc, 464 __rte_unused struct sfc_dp_rx_hw_limits *limits, 465 __rte_unused struct rte_mempool *mb_pool, 466 unsigned int *rxq_entries, 467 unsigned int *evq_entries, 468 unsigned int *rxq_max_fill_level) 469 { 470 *rxq_entries = nb_rx_desc; 471 *evq_entries = nb_rx_desc; 472 *rxq_max_fill_level = EFX_RXQ_LIMIT(*rxq_entries); 473 return 0; 474 } 475 476 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate; 477 static int 478 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id, 479 const struct rte_pci_addr *pci_addr, int socket_id, 480 const struct sfc_dp_rx_qcreate_info *info, 481 struct sfc_dp_rxq **dp_rxqp) 482 { 483 struct sfc_efx_rxq *rxq; 484 int rc; 485 486 rc = ENOMEM; 487 rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq), 488 RTE_CACHE_LINE_SIZE, socket_id); 489 if (rxq == NULL) 490 goto fail_rxq_alloc; 491 492 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr); 493 494 rc = ENOMEM; 495 rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc", 496 info->rxq_entries, 497 sizeof(*rxq->sw_desc), 498 RTE_CACHE_LINE_SIZE, socket_id); 499 if (rxq->sw_desc == NULL) 500 goto fail_desc_alloc; 501 502 /* efx datapath is bound to efx control path */ 503 rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq; 504 if (info->flags & SFC_RXQ_FLAG_RSS_HASH) 505 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH; 506 rxq->ptr_mask = info->rxq_entries - 1; 507 rxq->batch_max = info->batch_max; 508 rxq->prefix_size = info->prefix_size; 509 rxq->max_fill_level = info->max_fill_level; 510 rxq->refill_threshold = info->refill_threshold; 511 rxq->buf_size = info->buf_size; 512 rxq->refill_mb_pool = info->refill_mb_pool; 513 514 *dp_rxqp = &rxq->dp; 515 return 0; 516 517 fail_desc_alloc: 518 rte_free(rxq); 519 520 fail_rxq_alloc: 521 return rc; 522 } 523 524 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy; 525 static void 526 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq) 527 { 528 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 529 530 rte_free(rxq->sw_desc); 531 rte_free(rxq); 532 } 533 534 535 /* Use qstop and qstart functions in the case of qstart failure */ 536 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop; 537 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge; 538 539 540 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart; 541 static int 542 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq, 543 __rte_unused unsigned int evq_read_ptr, 544 const efx_rx_prefix_layout_t *pinfo) 545 { 546 /* libefx-based datapath is specific to libefx-based PMD */ 547 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 548 struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq); 549 int rc; 550 551 /* 552 * libefx API is used to extract information from Rx prefix and 553 * it guarantees consistency. Just do length check to ensure 554 * that we reserved space in Rx buffers correctly. 555 */ 556 if (rxq->prefix_size != pinfo->erpl_length) 557 return ENOTSUP; 558 559 rxq->common = crxq->common; 560 561 rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0; 562 563 sfc_efx_rx_qrefill(rxq); 564 565 rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING); 566 567 if (rxq->flags & SFC_EFX_RXQ_FLAG_INTR_EN) { 568 rc = sfc_efx_rx_qprime(rxq); 569 if (rc != 0) 570 goto fail_rx_qprime; 571 } 572 573 return 0; 574 575 fail_rx_qprime: 576 sfc_efx_rx_qstop(dp_rxq, NULL); 577 sfc_efx_rx_qpurge(dp_rxq); 578 return rc; 579 } 580 581 static void 582 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq, 583 __rte_unused unsigned int *evq_read_ptr) 584 { 585 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 586 587 rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING; 588 589 /* libefx-based datapath is bound to libefx-based PMD and uses 590 * event queue structure directly. So, there is no necessity to 591 * return EvQ read pointer. 592 */ 593 } 594 595 static void 596 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq) 597 { 598 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 599 unsigned int i; 600 struct sfc_efx_rx_sw_desc *rxd; 601 602 for (i = rxq->completed; i != rxq->added; ++i) { 603 rxd = &rxq->sw_desc[i & rxq->ptr_mask]; 604 rte_mbuf_raw_free(rxd->mbuf); 605 rxd->mbuf = NULL; 606 /* Packed stream relies on 0 in inactive SW desc. 607 * Rx queue stop is not performance critical, so 608 * there is no harm to do it always. 609 */ 610 rxd->flags = 0; 611 rxd->size = 0; 612 } 613 614 rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED; 615 } 616 617 static sfc_dp_rx_intr_enable_t sfc_efx_rx_intr_enable; 618 static int 619 sfc_efx_rx_intr_enable(struct sfc_dp_rxq *dp_rxq) 620 { 621 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 622 int rc = 0; 623 624 rxq->flags |= SFC_EFX_RXQ_FLAG_INTR_EN; 625 if (rxq->flags & SFC_EFX_RXQ_FLAG_STARTED) { 626 rc = sfc_efx_rx_qprime(rxq); 627 if (rc != 0) 628 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 629 } 630 return rc; 631 } 632 633 static sfc_dp_rx_intr_disable_t sfc_efx_rx_intr_disable; 634 static int 635 sfc_efx_rx_intr_disable(struct sfc_dp_rxq *dp_rxq) 636 { 637 struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq); 638 639 /* Cannot disarm, just disable rearm */ 640 rxq->flags &= ~SFC_EFX_RXQ_FLAG_INTR_EN; 641 return 0; 642 } 643 644 struct sfc_dp_rx sfc_efx_rx = { 645 .dp = { 646 .name = SFC_KVARG_DATAPATH_EFX, 647 .type = SFC_DP_RX, 648 .hw_fw_caps = SFC_DP_HW_FW_CAP_RX_EFX, 649 }, 650 .features = SFC_DP_RX_FEAT_INTR, 651 .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM | 652 DEV_RX_OFFLOAD_RSS_HASH, 653 .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER, 654 .qsize_up_rings = sfc_efx_rx_qsize_up_rings, 655 .qcreate = sfc_efx_rx_qcreate, 656 .qdestroy = sfc_efx_rx_qdestroy, 657 .qstart = sfc_efx_rx_qstart, 658 .qstop = sfc_efx_rx_qstop, 659 .qpurge = sfc_efx_rx_qpurge, 660 .supported_ptypes_get = sfc_efx_supported_ptypes_get, 661 .qdesc_npending = sfc_efx_rx_qdesc_npending, 662 .qdesc_status = sfc_efx_rx_qdesc_status, 663 .intr_enable = sfc_efx_rx_intr_enable, 664 .intr_disable = sfc_efx_rx_intr_disable, 665 .pkt_burst = sfc_efx_recv_pkts, 666 }; 667 668 static void 669 sfc_rx_qflush(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 670 { 671 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 672 sfc_ethdev_qid_t ethdev_qid; 673 struct sfc_rxq_info *rxq_info; 674 struct sfc_rxq *rxq; 675 unsigned int retry_count; 676 unsigned int wait_count; 677 int rc; 678 679 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 680 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 681 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 682 683 rxq = &sa->rxq_ctrl[sw_index]; 684 685 /* 686 * Retry Rx queue flushing in the case of flush failed or 687 * timeout. In the worst case it can delay for 6 seconds. 688 */ 689 for (retry_count = 0; 690 ((rxq_info->state & SFC_RXQ_FLUSHED) == 0) && 691 (retry_count < SFC_RX_QFLUSH_ATTEMPTS); 692 ++retry_count) { 693 rc = efx_rx_qflush(rxq->common); 694 if (rc != 0) { 695 rxq_info->state |= (rc == EALREADY) ? 696 SFC_RXQ_FLUSHED : SFC_RXQ_FLUSH_FAILED; 697 break; 698 } 699 rxq_info->state &= ~SFC_RXQ_FLUSH_FAILED; 700 rxq_info->state |= SFC_RXQ_FLUSHING; 701 702 /* 703 * Wait for Rx queue flush done or failed event at least 704 * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more 705 * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied 706 * by SFC_RX_QFLUSH_POLL_ATTEMPTS). 707 */ 708 wait_count = 0; 709 do { 710 rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS); 711 sfc_ev_qpoll(rxq->evq); 712 } while ((rxq_info->state & SFC_RXQ_FLUSHING) && 713 (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS)); 714 715 if (rxq_info->state & SFC_RXQ_FLUSHING) 716 sfc_err(sa, "RxQ %d (internal %u) flush timed out", 717 ethdev_qid, sw_index); 718 719 if (rxq_info->state & SFC_RXQ_FLUSH_FAILED) 720 sfc_err(sa, "RxQ %d (internal %u) flush failed", 721 ethdev_qid, sw_index); 722 723 if (rxq_info->state & SFC_RXQ_FLUSHED) 724 sfc_notice(sa, "RxQ %d (internal %u) flushed", 725 ethdev_qid, sw_index); 726 } 727 728 sa->priv.dp_rx->qpurge(rxq_info->dp); 729 } 730 731 static int 732 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq) 733 { 734 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 735 boolean_t need_rss = (rss->channels > 0) ? B_TRUE : B_FALSE; 736 struct sfc_port *port = &sa->port; 737 int rc; 738 739 /* 740 * If promiscuous or all-multicast mode has been requested, setting 741 * filter for the default Rx queue might fail, in particular, while 742 * running over PCI function which is not a member of corresponding 743 * privilege groups; if this occurs, few iterations will be made to 744 * repeat this step without promiscuous and all-multicast flags set 745 */ 746 retry: 747 rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, need_rss); 748 if (rc == 0) 749 return 0; 750 else if (rc != EOPNOTSUPP) 751 return rc; 752 753 if (port->promisc) { 754 sfc_warn(sa, "promiscuous mode has been requested, " 755 "but the HW rejects it"); 756 sfc_warn(sa, "promiscuous mode will be disabled"); 757 758 port->promisc = B_FALSE; 759 sa->eth_dev->data->promiscuous = 0; 760 rc = sfc_set_rx_mode_unchecked(sa); 761 if (rc != 0) 762 return rc; 763 764 goto retry; 765 } 766 767 if (port->allmulti) { 768 sfc_warn(sa, "all-multicast mode has been requested, " 769 "but the HW rejects it"); 770 sfc_warn(sa, "all-multicast mode will be disabled"); 771 772 port->allmulti = B_FALSE; 773 sa->eth_dev->data->all_multicast = 0; 774 rc = sfc_set_rx_mode_unchecked(sa); 775 if (rc != 0) 776 return rc; 777 778 goto retry; 779 } 780 781 return rc; 782 } 783 784 int 785 sfc_rx_qstart(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 786 { 787 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 788 sfc_ethdev_qid_t ethdev_qid; 789 struct sfc_rxq_info *rxq_info; 790 struct sfc_rxq *rxq; 791 struct sfc_evq *evq; 792 efx_rx_prefix_layout_t pinfo; 793 int rc; 794 795 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 796 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 797 798 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index); 799 800 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 801 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 802 803 rxq = &sa->rxq_ctrl[sw_index]; 804 evq = rxq->evq; 805 806 rc = sfc_ev_qstart(evq, sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index)); 807 if (rc != 0) 808 goto fail_ev_qstart; 809 810 switch (rxq_info->type) { 811 case EFX_RXQ_TYPE_DEFAULT: 812 rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type, 813 rxq->buf_size, 814 &rxq->mem, rxq_info->entries, 0 /* not used on EF10 */, 815 rxq_info->type_flags, evq->common, &rxq->common); 816 break; 817 case EFX_RXQ_TYPE_ES_SUPER_BUFFER: { 818 struct rte_mempool *mp = rxq_info->refill_mb_pool; 819 struct rte_mempool_info mp_info; 820 821 rc = rte_mempool_ops_get_info(mp, &mp_info); 822 if (rc != 0) { 823 /* Positive errno is used in the driver */ 824 rc = -rc; 825 goto fail_mp_get_info; 826 } 827 if (mp_info.contig_block_size <= 0) { 828 rc = EINVAL; 829 goto fail_bad_contig_block_size; 830 } 831 rc = efx_rx_qcreate_es_super_buffer(sa->nic, rxq->hw_index, 0, 832 mp_info.contig_block_size, rxq->buf_size, 833 mp->header_size + mp->elt_size + mp->trailer_size, 834 sa->rxd_wait_timeout_ns, 835 &rxq->mem, rxq_info->entries, rxq_info->type_flags, 836 evq->common, &rxq->common); 837 break; 838 } 839 default: 840 rc = ENOTSUP; 841 } 842 if (rc != 0) 843 goto fail_rx_qcreate; 844 845 rc = efx_rx_prefix_get_layout(rxq->common, &pinfo); 846 if (rc != 0) 847 goto fail_prefix_get_layout; 848 849 efx_rx_qenable(rxq->common); 850 851 rc = sa->priv.dp_rx->qstart(rxq_info->dp, evq->read_ptr, &pinfo); 852 if (rc != 0) 853 goto fail_dp_qstart; 854 855 rxq_info->state |= SFC_RXQ_STARTED; 856 857 if (ethdev_qid == 0 && !sfc_sa2shared(sa)->isolated) { 858 rc = sfc_rx_default_rxq_set_filter(sa, rxq); 859 if (rc != 0) 860 goto fail_mac_filter_default_rxq_set; 861 } 862 863 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 864 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 865 sa->eth_dev->data->rx_queue_state[ethdev_qid] = 866 RTE_ETH_QUEUE_STATE_STARTED; 867 868 return 0; 869 870 fail_mac_filter_default_rxq_set: 871 sfc_rx_qflush(sa, sw_index); 872 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 873 rxq_info->state = SFC_RXQ_INITIALIZED; 874 875 fail_dp_qstart: 876 efx_rx_qdestroy(rxq->common); 877 878 fail_prefix_get_layout: 879 fail_rx_qcreate: 880 fail_bad_contig_block_size: 881 fail_mp_get_info: 882 sfc_ev_qstop(evq); 883 884 fail_ev_qstart: 885 return rc; 886 } 887 888 void 889 sfc_rx_qstop(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 890 { 891 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 892 sfc_ethdev_qid_t ethdev_qid; 893 struct sfc_rxq_info *rxq_info; 894 struct sfc_rxq *rxq; 895 896 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 897 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 898 899 sfc_log_init(sa, "RxQ %d (internal %u)", ethdev_qid, sw_index); 900 901 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 902 903 if (rxq_info->state == SFC_RXQ_INITIALIZED) 904 return; 905 SFC_ASSERT(rxq_info->state & SFC_RXQ_STARTED); 906 907 /* It seems to be used by DPDK for debug purposes only ('rte_ether') */ 908 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 909 sa->eth_dev->data->rx_queue_state[ethdev_qid] = 910 RTE_ETH_QUEUE_STATE_STOPPED; 911 912 rxq = &sa->rxq_ctrl[sw_index]; 913 sa->priv.dp_rx->qstop(rxq_info->dp, &rxq->evq->read_ptr); 914 915 if (ethdev_qid == 0) 916 efx_mac_filter_default_rxq_clear(sa->nic); 917 918 sfc_rx_qflush(sa, sw_index); 919 920 rxq_info->state = SFC_RXQ_INITIALIZED; 921 922 efx_rx_qdestroy(rxq->common); 923 924 sfc_ev_qstop(rxq->evq); 925 } 926 927 static uint64_t 928 sfc_rx_get_offload_mask(struct sfc_adapter *sa) 929 { 930 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 931 uint64_t no_caps = 0; 932 933 if (encp->enc_tunnel_encapsulations_supported == 0) 934 no_caps |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 935 936 return ~no_caps; 937 } 938 939 uint64_t 940 sfc_rx_get_dev_offload_caps(struct sfc_adapter *sa) 941 { 942 uint64_t caps = sa->priv.dp_rx->dev_offload_capa; 943 944 caps |= DEV_RX_OFFLOAD_JUMBO_FRAME; 945 946 return caps & sfc_rx_get_offload_mask(sa); 947 } 948 949 uint64_t 950 sfc_rx_get_queue_offload_caps(struct sfc_adapter *sa) 951 { 952 return sa->priv.dp_rx->queue_offload_capa & sfc_rx_get_offload_mask(sa); 953 } 954 955 static int 956 sfc_rx_qcheck_conf(struct sfc_adapter *sa, unsigned int rxq_max_fill_level, 957 const struct rte_eth_rxconf *rx_conf, 958 __rte_unused uint64_t offloads) 959 { 960 int rc = 0; 961 962 if (rx_conf->rx_thresh.pthresh != 0 || 963 rx_conf->rx_thresh.hthresh != 0 || 964 rx_conf->rx_thresh.wthresh != 0) { 965 sfc_warn(sa, 966 "RxQ prefetch/host/writeback thresholds are not supported"); 967 } 968 969 if (rx_conf->rx_free_thresh > rxq_max_fill_level) { 970 sfc_err(sa, 971 "RxQ free threshold too large: %u vs maximum %u", 972 rx_conf->rx_free_thresh, rxq_max_fill_level); 973 rc = EINVAL; 974 } 975 976 if (rx_conf->rx_drop_en == 0) { 977 sfc_err(sa, "RxQ drop disable is not supported"); 978 rc = EINVAL; 979 } 980 981 return rc; 982 } 983 984 static unsigned int 985 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool) 986 { 987 uint32_t data_off; 988 uint32_t order; 989 990 /* The mbuf object itself is always cache line aligned */ 991 order = rte_bsf32(RTE_CACHE_LINE_SIZE); 992 993 /* Data offset from mbuf object start */ 994 data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) + 995 RTE_PKTMBUF_HEADROOM; 996 997 order = MIN(order, rte_bsf32(data_off)); 998 999 return 1u << order; 1000 } 1001 1002 static uint16_t 1003 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool) 1004 { 1005 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1006 const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start); 1007 const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end); 1008 uint16_t buf_size; 1009 unsigned int buf_aligned; 1010 unsigned int start_alignment; 1011 unsigned int end_padding_alignment; 1012 1013 /* Below it is assumed that both alignments are power of 2 */ 1014 SFC_ASSERT(rte_is_power_of_2(nic_align_start)); 1015 SFC_ASSERT(rte_is_power_of_2(nic_align_end)); 1016 1017 /* 1018 * mbuf is always cache line aligned, double-check 1019 * that it meets rx buffer start alignment requirements. 1020 */ 1021 1022 /* Start from mbuf pool data room size */ 1023 buf_size = rte_pktmbuf_data_room_size(mb_pool); 1024 1025 /* Remove headroom */ 1026 if (buf_size <= RTE_PKTMBUF_HEADROOM) { 1027 sfc_err(sa, 1028 "RxQ mbuf pool %s object data room size %u is smaller than headroom %u", 1029 mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM); 1030 return 0; 1031 } 1032 buf_size -= RTE_PKTMBUF_HEADROOM; 1033 1034 /* Calculate guaranteed data start alignment */ 1035 buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool); 1036 1037 /* Reserve space for start alignment */ 1038 if (buf_aligned < nic_align_start) { 1039 start_alignment = nic_align_start - buf_aligned; 1040 if (buf_size <= start_alignment) { 1041 sfc_err(sa, 1042 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC", 1043 mb_pool->name, 1044 rte_pktmbuf_data_room_size(mb_pool), 1045 RTE_PKTMBUF_HEADROOM, start_alignment); 1046 return 0; 1047 } 1048 buf_aligned = nic_align_start; 1049 buf_size -= start_alignment; 1050 } else { 1051 start_alignment = 0; 1052 } 1053 1054 /* Make sure that end padding does not write beyond the buffer */ 1055 if (buf_aligned < nic_align_end) { 1056 /* 1057 * Estimate space which can be lost. If guarnteed buffer 1058 * size is odd, lost space is (nic_align_end - 1). More 1059 * accurate formula is below. 1060 */ 1061 end_padding_alignment = nic_align_end - 1062 MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1)); 1063 if (buf_size <= end_padding_alignment) { 1064 sfc_err(sa, 1065 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC", 1066 mb_pool->name, 1067 rte_pktmbuf_data_room_size(mb_pool), 1068 RTE_PKTMBUF_HEADROOM, start_alignment, 1069 end_padding_alignment); 1070 return 0; 1071 } 1072 buf_size -= end_padding_alignment; 1073 } else { 1074 /* 1075 * Start is aligned the same or better than end, 1076 * just align length. 1077 */ 1078 buf_size = EFX_P2ALIGN(uint32_t, buf_size, nic_align_end); 1079 } 1080 1081 return buf_size; 1082 } 1083 1084 int 1085 sfc_rx_qinit(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 1086 uint16_t nb_rx_desc, unsigned int socket_id, 1087 const struct rte_eth_rxconf *rx_conf, 1088 struct rte_mempool *mb_pool) 1089 { 1090 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1091 sfc_ethdev_qid_t ethdev_qid; 1092 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1093 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1094 int rc; 1095 unsigned int rxq_entries; 1096 unsigned int evq_entries; 1097 unsigned int rxq_max_fill_level; 1098 uint64_t offloads; 1099 uint16_t buf_size; 1100 struct sfc_rxq_info *rxq_info; 1101 struct sfc_evq *evq; 1102 struct sfc_rxq *rxq; 1103 struct sfc_dp_rx_qcreate_info info; 1104 struct sfc_dp_rx_hw_limits hw_limits; 1105 uint16_t rx_free_thresh; 1106 const char *error; 1107 1108 memset(&hw_limits, 0, sizeof(hw_limits)); 1109 hw_limits.rxq_max_entries = sa->rxq_max_entries; 1110 hw_limits.rxq_min_entries = sa->rxq_min_entries; 1111 hw_limits.evq_max_entries = sa->evq_max_entries; 1112 hw_limits.evq_min_entries = sa->evq_min_entries; 1113 1114 rc = sa->priv.dp_rx->qsize_up_rings(nb_rx_desc, &hw_limits, mb_pool, 1115 &rxq_entries, &evq_entries, 1116 &rxq_max_fill_level); 1117 if (rc != 0) 1118 goto fail_size_up_rings; 1119 SFC_ASSERT(rxq_entries >= sa->rxq_min_entries); 1120 SFC_ASSERT(rxq_entries <= sa->rxq_max_entries); 1121 SFC_ASSERT(rxq_max_fill_level <= nb_rx_desc); 1122 1123 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 1124 1125 offloads = rx_conf->offloads; 1126 /* Add device level Rx offloads if the queue is an ethdev Rx queue */ 1127 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 1128 offloads |= sa->eth_dev->data->dev_conf.rxmode.offloads; 1129 1130 rc = sfc_rx_qcheck_conf(sa, rxq_max_fill_level, rx_conf, offloads); 1131 if (rc != 0) 1132 goto fail_bad_conf; 1133 1134 buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool); 1135 if (buf_size == 0) { 1136 sfc_err(sa, 1137 "RxQ %d (internal %u) mbuf pool object size is too small", 1138 ethdev_qid, sw_index); 1139 rc = EINVAL; 1140 goto fail_bad_conf; 1141 } 1142 1143 if (!sfc_rx_check_scatter(sa->port.pdu, buf_size, 1144 encp->enc_rx_prefix_size, 1145 (offloads & DEV_RX_OFFLOAD_SCATTER), 1146 encp->enc_rx_scatter_max, 1147 &error)) { 1148 sfc_err(sa, "RxQ %d (internal %u) MTU check failed: %s", 1149 ethdev_qid, sw_index, error); 1150 sfc_err(sa, 1151 "RxQ %d (internal %u) calculated Rx buffer size is %u vs " 1152 "PDU size %u plus Rx prefix %u bytes", 1153 ethdev_qid, sw_index, buf_size, 1154 (unsigned int)sa->port.pdu, encp->enc_rx_prefix_size); 1155 rc = EINVAL; 1156 goto fail_bad_conf; 1157 } 1158 1159 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1160 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1161 1162 SFC_ASSERT(rxq_entries <= rxq_info->max_entries); 1163 rxq_info->entries = rxq_entries; 1164 1165 if (sa->priv.dp_rx->dp.hw_fw_caps & SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER) 1166 rxq_info->type = EFX_RXQ_TYPE_ES_SUPER_BUFFER; 1167 else 1168 rxq_info->type = EFX_RXQ_TYPE_DEFAULT; 1169 1170 rxq_info->type_flags |= 1171 (offloads & DEV_RX_OFFLOAD_SCATTER) ? 1172 EFX_RXQ_FLAG_SCATTER : EFX_RXQ_FLAG_NONE; 1173 1174 if ((encp->enc_tunnel_encapsulations_supported != 0) && 1175 (sfc_dp_rx_offload_capa(sa->priv.dp_rx) & 1176 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) != 0) 1177 rxq_info->type_flags |= EFX_RXQ_FLAG_INNER_CLASSES; 1178 1179 if (offloads & DEV_RX_OFFLOAD_RSS_HASH) 1180 rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH; 1181 1182 if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_FLAG) != 0) 1183 rxq_info->type_flags |= EFX_RXQ_FLAG_USER_FLAG; 1184 1185 if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_MARK) != 0 || 1186 sfc_flow_tunnel_is_active(sa)) 1187 rxq_info->type_flags |= EFX_RXQ_FLAG_USER_MARK; 1188 1189 rc = sfc_ev_qinit(sa, SFC_EVQ_TYPE_RX, sw_index, 1190 evq_entries, socket_id, &evq); 1191 if (rc != 0) 1192 goto fail_ev_qinit; 1193 1194 rxq = &sa->rxq_ctrl[sw_index]; 1195 rxq->evq = evq; 1196 rxq->hw_index = sw_index; 1197 /* 1198 * If Rx refill threshold is specified (its value is non zero) in 1199 * Rx configuration, use specified value. Otherwise use 1/8 of 1200 * the Rx descriptors number as the default. It allows to keep 1201 * Rx ring full-enough and does not refill too aggressive if 1202 * packet rate is high. 1203 * 1204 * Since PMD refills in bulks waiting for full bulk may be 1205 * refilled (basically round down), it is better to round up 1206 * here to mitigate it a bit. 1207 */ 1208 rx_free_thresh = (rx_conf->rx_free_thresh != 0) ? 1209 rx_conf->rx_free_thresh : EFX_DIV_ROUND_UP(nb_rx_desc, 8); 1210 /* Rx refill threshold cannot be smaller than refill bulk */ 1211 rxq_info->refill_threshold = 1212 RTE_MAX(rx_free_thresh, SFC_RX_REFILL_BULK); 1213 rxq_info->refill_mb_pool = mb_pool; 1214 1215 if (rss->hash_support == EFX_RX_HASH_AVAILABLE && rss->channels > 0 && 1216 (offloads & DEV_RX_OFFLOAD_RSS_HASH)) 1217 rxq_info->rxq_flags = SFC_RXQ_FLAG_RSS_HASH; 1218 else 1219 rxq_info->rxq_flags = 0; 1220 1221 rxq->buf_size = buf_size; 1222 1223 rc = sfc_dma_alloc(sa, "rxq", sw_index, 1224 efx_rxq_size(sa->nic, rxq_info->entries), 1225 socket_id, &rxq->mem); 1226 if (rc != 0) 1227 goto fail_dma_alloc; 1228 1229 memset(&info, 0, sizeof(info)); 1230 info.refill_mb_pool = rxq_info->refill_mb_pool; 1231 info.max_fill_level = rxq_max_fill_level; 1232 info.refill_threshold = rxq_info->refill_threshold; 1233 info.buf_size = buf_size; 1234 info.batch_max = encp->enc_rx_batch_max; 1235 info.prefix_size = encp->enc_rx_prefix_size; 1236 1237 if (sfc_flow_tunnel_is_active(sa)) 1238 info.user_mark_mask = SFC_FT_USER_MARK_MASK; 1239 else 1240 info.user_mark_mask = UINT32_MAX; 1241 1242 info.flags = rxq_info->rxq_flags; 1243 info.rxq_entries = rxq_info->entries; 1244 info.rxq_hw_ring = rxq->mem.esm_base; 1245 info.evq_hw_index = sfc_evq_sw_index_by_rxq_sw_index(sa, sw_index); 1246 info.evq_entries = evq_entries; 1247 info.evq_hw_ring = evq->mem.esm_base; 1248 info.hw_index = rxq->hw_index; 1249 info.mem_bar = sa->mem_bar.esb_base; 1250 info.vi_window_shift = encp->enc_vi_window_shift; 1251 info.fcw_offset = sa->fcw_offset; 1252 1253 rc = sa->priv.dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index, 1254 &RTE_ETH_DEV_TO_PCI(sa->eth_dev)->addr, 1255 socket_id, &info, &rxq_info->dp); 1256 if (rc != 0) 1257 goto fail_dp_rx_qcreate; 1258 1259 evq->dp_rxq = rxq_info->dp; 1260 1261 rxq_info->state = SFC_RXQ_INITIALIZED; 1262 1263 rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0); 1264 1265 return 0; 1266 1267 fail_dp_rx_qcreate: 1268 sfc_dma_free(sa, &rxq->mem); 1269 1270 fail_dma_alloc: 1271 sfc_ev_qfini(evq); 1272 1273 fail_ev_qinit: 1274 rxq_info->entries = 0; 1275 1276 fail_bad_conf: 1277 fail_size_up_rings: 1278 sfc_log_init(sa, "failed %d", rc); 1279 return rc; 1280 } 1281 1282 void 1283 sfc_rx_qfini(struct sfc_adapter *sa, sfc_sw_index_t sw_index) 1284 { 1285 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1286 sfc_ethdev_qid_t ethdev_qid; 1287 struct sfc_rxq_info *rxq_info; 1288 struct sfc_rxq *rxq; 1289 1290 SFC_ASSERT(sw_index < sfc_sa2shared(sa)->rxq_count); 1291 ethdev_qid = sfc_ethdev_rx_qid_by_rxq_sw_index(sas, sw_index); 1292 1293 if (ethdev_qid != SFC_ETHDEV_QID_INVALID) 1294 sa->eth_dev->data->rx_queues[ethdev_qid] = NULL; 1295 1296 rxq_info = &sfc_sa2shared(sa)->rxq_info[sw_index]; 1297 1298 SFC_ASSERT(rxq_info->state == SFC_RXQ_INITIALIZED); 1299 1300 sa->priv.dp_rx->qdestroy(rxq_info->dp); 1301 rxq_info->dp = NULL; 1302 1303 rxq_info->state &= ~SFC_RXQ_INITIALIZED; 1304 rxq_info->entries = 0; 1305 1306 rxq = &sa->rxq_ctrl[sw_index]; 1307 1308 sfc_dma_free(sa, &rxq->mem); 1309 1310 sfc_ev_qfini(rxq->evq); 1311 rxq->evq = NULL; 1312 } 1313 1314 /* 1315 * Mapping between RTE RSS hash functions and their EFX counterparts. 1316 */ 1317 static const struct sfc_rss_hf_rte_to_efx sfc_rss_hf_map[] = { 1318 { ETH_RSS_NONFRAG_IPV4_TCP, 1319 EFX_RX_HASH(IPV4_TCP, 4TUPLE) }, 1320 { ETH_RSS_NONFRAG_IPV4_UDP, 1321 EFX_RX_HASH(IPV4_UDP, 4TUPLE) }, 1322 { ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX, 1323 EFX_RX_HASH(IPV6_TCP, 4TUPLE) }, 1324 { ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_UDP_EX, 1325 EFX_RX_HASH(IPV6_UDP, 4TUPLE) }, 1326 { ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER, 1327 EFX_RX_HASH(IPV4_TCP, 2TUPLE) | EFX_RX_HASH(IPV4_UDP, 2TUPLE) | 1328 EFX_RX_HASH(IPV4, 2TUPLE) }, 1329 { ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER | 1330 ETH_RSS_IPV6_EX, 1331 EFX_RX_HASH(IPV6_TCP, 2TUPLE) | EFX_RX_HASH(IPV6_UDP, 2TUPLE) | 1332 EFX_RX_HASH(IPV6, 2TUPLE) } 1333 }; 1334 1335 static efx_rx_hash_type_t 1336 sfc_rx_hash_types_mask_supp(efx_rx_hash_type_t hash_type, 1337 unsigned int *hash_type_flags_supported, 1338 unsigned int nb_hash_type_flags_supported) 1339 { 1340 efx_rx_hash_type_t hash_type_masked = 0; 1341 unsigned int i, j; 1342 1343 for (i = 0; i < nb_hash_type_flags_supported; ++i) { 1344 unsigned int class_tuple_lbn[] = { 1345 EFX_RX_CLASS_IPV4_TCP_LBN, 1346 EFX_RX_CLASS_IPV4_UDP_LBN, 1347 EFX_RX_CLASS_IPV4_LBN, 1348 EFX_RX_CLASS_IPV6_TCP_LBN, 1349 EFX_RX_CLASS_IPV6_UDP_LBN, 1350 EFX_RX_CLASS_IPV6_LBN 1351 }; 1352 1353 for (j = 0; j < RTE_DIM(class_tuple_lbn); ++j) { 1354 unsigned int tuple_mask = EFX_RX_CLASS_HASH_4TUPLE; 1355 unsigned int flag; 1356 1357 tuple_mask <<= class_tuple_lbn[j]; 1358 flag = hash_type & tuple_mask; 1359 1360 if (flag == hash_type_flags_supported[i]) 1361 hash_type_masked |= flag; 1362 } 1363 } 1364 1365 return hash_type_masked; 1366 } 1367 1368 int 1369 sfc_rx_hash_init(struct sfc_adapter *sa) 1370 { 1371 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1372 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1373 uint32_t alg_mask = encp->enc_rx_scale_hash_alg_mask; 1374 efx_rx_hash_alg_t alg; 1375 unsigned int flags_supp[EFX_RX_HASH_NFLAGS]; 1376 unsigned int nb_flags_supp; 1377 struct sfc_rss_hf_rte_to_efx *hf_map; 1378 struct sfc_rss_hf_rte_to_efx *entry; 1379 efx_rx_hash_type_t efx_hash_types; 1380 unsigned int i; 1381 int rc; 1382 1383 if (alg_mask & (1U << EFX_RX_HASHALG_TOEPLITZ)) 1384 alg = EFX_RX_HASHALG_TOEPLITZ; 1385 else if (alg_mask & (1U << EFX_RX_HASHALG_PACKED_STREAM)) 1386 alg = EFX_RX_HASHALG_PACKED_STREAM; 1387 else 1388 return EINVAL; 1389 1390 rc = efx_rx_scale_hash_flags_get(sa->nic, alg, flags_supp, 1391 RTE_DIM(flags_supp), &nb_flags_supp); 1392 if (rc != 0) 1393 return rc; 1394 1395 hf_map = rte_calloc_socket("sfc-rss-hf-map", 1396 RTE_DIM(sfc_rss_hf_map), 1397 sizeof(*hf_map), 0, sa->socket_id); 1398 if (hf_map == NULL) 1399 return ENOMEM; 1400 1401 entry = hf_map; 1402 efx_hash_types = 0; 1403 for (i = 0; i < RTE_DIM(sfc_rss_hf_map); ++i) { 1404 efx_rx_hash_type_t ht; 1405 1406 ht = sfc_rx_hash_types_mask_supp(sfc_rss_hf_map[i].efx, 1407 flags_supp, nb_flags_supp); 1408 if (ht != 0) { 1409 entry->rte = sfc_rss_hf_map[i].rte; 1410 entry->efx = ht; 1411 efx_hash_types |= ht; 1412 ++entry; 1413 } 1414 } 1415 1416 rss->hash_alg = alg; 1417 rss->hf_map_nb_entries = (unsigned int)(entry - hf_map); 1418 rss->hf_map = hf_map; 1419 rss->hash_types = efx_hash_types; 1420 1421 return 0; 1422 } 1423 1424 void 1425 sfc_rx_hash_fini(struct sfc_adapter *sa) 1426 { 1427 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1428 1429 rte_free(rss->hf_map); 1430 } 1431 1432 int 1433 sfc_rx_hf_rte_to_efx(struct sfc_adapter *sa, uint64_t rte, 1434 efx_rx_hash_type_t *efx) 1435 { 1436 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1437 efx_rx_hash_type_t hash_types = 0; 1438 unsigned int i; 1439 1440 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1441 uint64_t rte_mask = rss->hf_map[i].rte; 1442 1443 if ((rte & rte_mask) != 0) { 1444 rte &= ~rte_mask; 1445 hash_types |= rss->hf_map[i].efx; 1446 } 1447 } 1448 1449 if (rte != 0) { 1450 sfc_err(sa, "unsupported hash functions requested"); 1451 return EINVAL; 1452 } 1453 1454 *efx = hash_types; 1455 1456 return 0; 1457 } 1458 1459 uint64_t 1460 sfc_rx_hf_efx_to_rte(struct sfc_rss *rss, efx_rx_hash_type_t efx) 1461 { 1462 uint64_t rte = 0; 1463 unsigned int i; 1464 1465 for (i = 0; i < rss->hf_map_nb_entries; ++i) { 1466 efx_rx_hash_type_t hash_type = rss->hf_map[i].efx; 1467 1468 if ((efx & hash_type) == hash_type) 1469 rte |= rss->hf_map[i].rte; 1470 } 1471 1472 return rte; 1473 } 1474 1475 static int 1476 sfc_rx_process_adv_conf_rss(struct sfc_adapter *sa, 1477 struct rte_eth_rss_conf *conf) 1478 { 1479 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1480 efx_rx_hash_type_t efx_hash_types = rss->hash_types; 1481 uint64_t rss_hf = sfc_rx_hf_efx_to_rte(rss, efx_hash_types); 1482 int rc; 1483 1484 if (rss->context_type != EFX_RX_SCALE_EXCLUSIVE) { 1485 if ((conf->rss_hf != 0 && conf->rss_hf != rss_hf) || 1486 conf->rss_key != NULL) 1487 return EINVAL; 1488 } 1489 1490 if (conf->rss_hf != 0) { 1491 rc = sfc_rx_hf_rte_to_efx(sa, conf->rss_hf, &efx_hash_types); 1492 if (rc != 0) 1493 return rc; 1494 } 1495 1496 if (conf->rss_key != NULL) { 1497 if (conf->rss_key_len != sizeof(rss->key)) { 1498 sfc_err(sa, "RSS key size is wrong (should be %zu)", 1499 sizeof(rss->key)); 1500 return EINVAL; 1501 } 1502 rte_memcpy(rss->key, conf->rss_key, sizeof(rss->key)); 1503 } 1504 1505 rss->hash_types = efx_hash_types; 1506 1507 return 0; 1508 } 1509 1510 static int 1511 sfc_rx_rss_config(struct sfc_adapter *sa) 1512 { 1513 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1514 int rc = 0; 1515 1516 if (rss->channels > 0) { 1517 rc = efx_rx_scale_mode_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1518 rss->hash_alg, rss->hash_types, 1519 B_TRUE); 1520 if (rc != 0) 1521 goto finish; 1522 1523 rc = efx_rx_scale_key_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1524 rss->key, sizeof(rss->key)); 1525 if (rc != 0) 1526 goto finish; 1527 1528 rc = efx_rx_scale_tbl_set(sa->nic, EFX_RSS_CONTEXT_DEFAULT, 1529 rss->tbl, RTE_DIM(rss->tbl)); 1530 } 1531 1532 finish: 1533 return rc; 1534 } 1535 1536 struct sfc_rxq_info * 1537 sfc_rxq_info_by_ethdev_qid(struct sfc_adapter_shared *sas, 1538 sfc_ethdev_qid_t ethdev_qid) 1539 { 1540 sfc_sw_index_t sw_index; 1541 1542 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count); 1543 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 1544 1545 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid); 1546 return &sas->rxq_info[sw_index]; 1547 } 1548 1549 struct sfc_rxq * 1550 sfc_rxq_ctrl_by_ethdev_qid(struct sfc_adapter *sa, sfc_ethdev_qid_t ethdev_qid) 1551 { 1552 struct sfc_adapter_shared *sas = sfc_sa2shared(sa); 1553 sfc_sw_index_t sw_index; 1554 1555 SFC_ASSERT((unsigned int)ethdev_qid < sas->ethdev_rxq_count); 1556 SFC_ASSERT(ethdev_qid != SFC_ETHDEV_QID_INVALID); 1557 1558 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, ethdev_qid); 1559 return &sa->rxq_ctrl[sw_index]; 1560 } 1561 1562 int 1563 sfc_rx_start(struct sfc_adapter *sa) 1564 { 1565 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1566 sfc_sw_index_t sw_index; 1567 int rc; 1568 1569 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count, 1570 sas->rxq_count); 1571 1572 rc = efx_rx_init(sa->nic); 1573 if (rc != 0) 1574 goto fail_rx_init; 1575 1576 rc = sfc_rx_rss_config(sa); 1577 if (rc != 0) 1578 goto fail_rss_config; 1579 1580 for (sw_index = 0; sw_index < sas->rxq_count; ++sw_index) { 1581 if (sas->rxq_info[sw_index].state == SFC_RXQ_INITIALIZED && 1582 (!sas->rxq_info[sw_index].deferred_start || 1583 sas->rxq_info[sw_index].deferred_started)) { 1584 rc = sfc_rx_qstart(sa, sw_index); 1585 if (rc != 0) 1586 goto fail_rx_qstart; 1587 } 1588 } 1589 1590 return 0; 1591 1592 fail_rx_qstart: 1593 while (sw_index-- > 0) 1594 sfc_rx_qstop(sa, sw_index); 1595 1596 fail_rss_config: 1597 efx_rx_fini(sa->nic); 1598 1599 fail_rx_init: 1600 sfc_log_init(sa, "failed %d", rc); 1601 return rc; 1602 } 1603 1604 void 1605 sfc_rx_stop(struct sfc_adapter *sa) 1606 { 1607 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1608 sfc_sw_index_t sw_index; 1609 1610 sfc_log_init(sa, "rxq_count=%u (internal %u)", sas->ethdev_rxq_count, 1611 sas->rxq_count); 1612 1613 sw_index = sas->rxq_count; 1614 while (sw_index-- > 0) { 1615 if (sas->rxq_info[sw_index].state & SFC_RXQ_STARTED) 1616 sfc_rx_qstop(sa, sw_index); 1617 } 1618 1619 efx_rx_fini(sa->nic); 1620 } 1621 1622 int 1623 sfc_rx_qinit_info(struct sfc_adapter *sa, sfc_sw_index_t sw_index, 1624 unsigned int extra_efx_type_flags) 1625 { 1626 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1627 struct sfc_rxq_info *rxq_info = &sas->rxq_info[sw_index]; 1628 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); 1629 unsigned int max_entries; 1630 1631 max_entries = encp->enc_rxq_max_ndescs; 1632 SFC_ASSERT(rte_is_power_of_2(max_entries)); 1633 1634 rxq_info->max_entries = max_entries; 1635 rxq_info->type_flags = extra_efx_type_flags; 1636 1637 return 0; 1638 } 1639 1640 static int 1641 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode) 1642 { 1643 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1644 uint64_t offloads_supported = sfc_rx_get_dev_offload_caps(sa) | 1645 sfc_rx_get_queue_offload_caps(sa); 1646 struct sfc_rss *rss = &sas->rss; 1647 int rc = 0; 1648 1649 switch (rxmode->mq_mode) { 1650 case ETH_MQ_RX_NONE: 1651 /* No special checks are required */ 1652 break; 1653 case ETH_MQ_RX_RSS: 1654 if (rss->context_type == EFX_RX_SCALE_UNAVAILABLE) { 1655 sfc_err(sa, "RSS is not available"); 1656 rc = EINVAL; 1657 } 1658 break; 1659 default: 1660 sfc_err(sa, "Rx multi-queue mode %u not supported", 1661 rxmode->mq_mode); 1662 rc = EINVAL; 1663 } 1664 1665 /* 1666 * Requested offloads are validated against supported by ethdev, 1667 * so unsupported offloads cannot be added as the result of 1668 * below check. 1669 */ 1670 if ((rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM) != 1671 (offloads_supported & DEV_RX_OFFLOAD_CHECKSUM)) { 1672 sfc_warn(sa, "Rx checksum offloads cannot be disabled - always on (IPv4/TCP/UDP)"); 1673 rxmode->offloads |= DEV_RX_OFFLOAD_CHECKSUM; 1674 } 1675 1676 if ((offloads_supported & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM) && 1677 (~rxmode->offloads & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) { 1678 sfc_warn(sa, "Rx outer IPv4 checksum offload cannot be disabled - always on"); 1679 rxmode->offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 1680 } 1681 1682 return rc; 1683 } 1684 1685 /** 1686 * Destroy excess queues that are no longer needed after reconfiguration 1687 * or complete close. 1688 */ 1689 static void 1690 sfc_rx_fini_queues(struct sfc_adapter *sa, unsigned int nb_rx_queues) 1691 { 1692 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1693 sfc_sw_index_t sw_index; 1694 sfc_ethdev_qid_t ethdev_qid; 1695 1696 SFC_ASSERT(nb_rx_queues <= sas->ethdev_rxq_count); 1697 1698 /* 1699 * Finalize only ethdev queues since other ones are finalized only 1700 * on device close and they may require additional deinitializaton. 1701 */ 1702 ethdev_qid = sas->ethdev_rxq_count; 1703 while (--ethdev_qid >= (int)nb_rx_queues) { 1704 struct sfc_rxq_info *rxq_info; 1705 1706 rxq_info = sfc_rxq_info_by_ethdev_qid(sas, ethdev_qid); 1707 if (rxq_info->state & SFC_RXQ_INITIALIZED) { 1708 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, 1709 ethdev_qid); 1710 sfc_rx_qfini(sa, sw_index); 1711 } 1712 1713 } 1714 1715 sas->ethdev_rxq_count = nb_rx_queues; 1716 } 1717 1718 /** 1719 * Initialize Rx subsystem. 1720 * 1721 * Called at device (re)configuration stage when number of receive queues is 1722 * specified together with other device level receive configuration. 1723 * 1724 * It should be used to allocate NUMA-unaware resources. 1725 */ 1726 int 1727 sfc_rx_configure(struct sfc_adapter *sa) 1728 { 1729 struct sfc_adapter_shared * const sas = sfc_sa2shared(sa); 1730 struct sfc_rss *rss = &sas->rss; 1731 struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf; 1732 const unsigned int nb_rx_queues = sa->eth_dev->data->nb_rx_queues; 1733 const unsigned int nb_rsrv_rx_queues = sfc_nb_reserved_rxq(sas); 1734 const unsigned int nb_rxq_total = nb_rx_queues + nb_rsrv_rx_queues; 1735 bool reconfigure; 1736 int rc; 1737 1738 sfc_log_init(sa, "nb_rx_queues=%u (old %u)", 1739 nb_rx_queues, sas->ethdev_rxq_count); 1740 1741 rc = sfc_rx_check_mode(sa, &dev_conf->rxmode); 1742 if (rc != 0) 1743 goto fail_check_mode; 1744 1745 if (nb_rxq_total == sas->rxq_count) { 1746 reconfigure = true; 1747 goto configure_rss; 1748 } 1749 1750 if (sas->rxq_info == NULL) { 1751 reconfigure = false; 1752 rc = ENOMEM; 1753 sas->rxq_info = rte_calloc_socket("sfc-rxqs", nb_rxq_total, 1754 sizeof(sas->rxq_info[0]), 0, 1755 sa->socket_id); 1756 if (sas->rxq_info == NULL) 1757 goto fail_rxqs_alloc; 1758 1759 /* 1760 * Allocate primary process only RxQ control from heap 1761 * since it should not be shared. 1762 */ 1763 rc = ENOMEM; 1764 sa->rxq_ctrl = calloc(nb_rxq_total, sizeof(sa->rxq_ctrl[0])); 1765 if (sa->rxq_ctrl == NULL) 1766 goto fail_rxqs_ctrl_alloc; 1767 } else { 1768 struct sfc_rxq_info *new_rxq_info; 1769 struct sfc_rxq *new_rxq_ctrl; 1770 1771 reconfigure = true; 1772 1773 /* Do not ununitialize reserved queues */ 1774 if (nb_rx_queues < sas->ethdev_rxq_count) 1775 sfc_rx_fini_queues(sa, nb_rx_queues); 1776 1777 rc = ENOMEM; 1778 new_rxq_info = 1779 rte_realloc(sas->rxq_info, 1780 nb_rxq_total * sizeof(sas->rxq_info[0]), 0); 1781 if (new_rxq_info == NULL && nb_rxq_total > 0) 1782 goto fail_rxqs_realloc; 1783 1784 rc = ENOMEM; 1785 new_rxq_ctrl = realloc(sa->rxq_ctrl, 1786 nb_rxq_total * sizeof(sa->rxq_ctrl[0])); 1787 if (new_rxq_ctrl == NULL && nb_rxq_total > 0) 1788 goto fail_rxqs_ctrl_realloc; 1789 1790 sas->rxq_info = new_rxq_info; 1791 sa->rxq_ctrl = new_rxq_ctrl; 1792 if (nb_rxq_total > sas->rxq_count) { 1793 unsigned int rxq_count = sas->rxq_count; 1794 1795 memset(&sas->rxq_info[rxq_count], 0, 1796 (nb_rxq_total - rxq_count) * 1797 sizeof(sas->rxq_info[0])); 1798 memset(&sa->rxq_ctrl[rxq_count], 0, 1799 (nb_rxq_total - rxq_count) * 1800 sizeof(sa->rxq_ctrl[0])); 1801 } 1802 } 1803 1804 while (sas->ethdev_rxq_count < nb_rx_queues) { 1805 sfc_sw_index_t sw_index; 1806 1807 sw_index = sfc_rxq_sw_index_by_ethdev_rx_qid(sas, 1808 sas->ethdev_rxq_count); 1809 rc = sfc_rx_qinit_info(sa, sw_index, 0); 1810 if (rc != 0) 1811 goto fail_rx_qinit_info; 1812 1813 sas->ethdev_rxq_count++; 1814 } 1815 1816 sas->rxq_count = sas->ethdev_rxq_count + nb_rsrv_rx_queues; 1817 1818 if (!reconfigure) { 1819 rc = sfc_mae_counter_rxq_init(sa); 1820 if (rc != 0) 1821 goto fail_count_rxq_init; 1822 } 1823 1824 configure_rss: 1825 rss->channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ? 1826 MIN(sas->ethdev_rxq_count, EFX_MAXRSS) : 0; 1827 1828 if (rss->channels > 0) { 1829 struct rte_eth_rss_conf *adv_conf_rss; 1830 sfc_sw_index_t sw_index; 1831 1832 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index) 1833 rss->tbl[sw_index] = sw_index % rss->channels; 1834 1835 adv_conf_rss = &dev_conf->rx_adv_conf.rss_conf; 1836 rc = sfc_rx_process_adv_conf_rss(sa, adv_conf_rss); 1837 if (rc != 0) 1838 goto fail_rx_process_adv_conf_rss; 1839 } 1840 1841 return 0; 1842 1843 fail_rx_process_adv_conf_rss: 1844 if (!reconfigure) 1845 sfc_mae_counter_rxq_fini(sa); 1846 1847 fail_count_rxq_init: 1848 fail_rx_qinit_info: 1849 fail_rxqs_ctrl_realloc: 1850 fail_rxqs_realloc: 1851 fail_rxqs_ctrl_alloc: 1852 fail_rxqs_alloc: 1853 sfc_rx_close(sa); 1854 1855 fail_check_mode: 1856 sfc_log_init(sa, "failed %d", rc); 1857 return rc; 1858 } 1859 1860 /** 1861 * Shutdown Rx subsystem. 1862 * 1863 * Called at device close stage, for example, before device shutdown. 1864 */ 1865 void 1866 sfc_rx_close(struct sfc_adapter *sa) 1867 { 1868 struct sfc_rss *rss = &sfc_sa2shared(sa)->rss; 1869 1870 sfc_rx_fini_queues(sa, 0); 1871 sfc_mae_counter_rxq_fini(sa); 1872 1873 rss->channels = 0; 1874 1875 free(sa->rxq_ctrl); 1876 sa->rxq_ctrl = NULL; 1877 1878 rte_free(sfc_sa2shared(sa)->rxq_info); 1879 sfc_sa2shared(sa)->rxq_info = NULL; 1880 } 1881