1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2021 Xilinx, Inc. 3 */ 4 5 #ifndef _SFC_NIC_DMA_DP_H 6 #define _SFC_NIC_DMA_DP_H 7 8 #include <rte_common.h> 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define SFC_NIC_DMA_REGIONS_MAX 2 15 16 struct sfc_nic_dma_region { 17 rte_iova_t nic_base; 18 rte_iova_t trgt_base; 19 rte_iova_t trgt_end; 20 }; 21 22 /** Driver cache for NIC DMA regions */ 23 struct sfc_nic_dma_info { 24 struct sfc_nic_dma_region regions[SFC_NIC_DMA_REGIONS_MAX]; 25 unsigned int nb_regions; 26 }; 27 28 static inline rte_iova_t sfc_nic_dma_map(const struct sfc_nic_dma_info * nic_dma_info,rte_iova_t trgt_addr,size_t len)29sfc_nic_dma_map(const struct sfc_nic_dma_info *nic_dma_info, 30 rte_iova_t trgt_addr, size_t len) 31 { 32 unsigned int i; 33 34 for (i = 0; i < nic_dma_info->nb_regions; i++) { 35 const struct sfc_nic_dma_region *region; 36 37 region = &nic_dma_info->regions[i]; 38 /* 39 * Do not sum trgt_addr and len to avoid overflow 40 * checking. 41 */ 42 if (region->trgt_base <= trgt_addr && 43 trgt_addr <= region->trgt_end && 44 len <= region->trgt_end - trgt_addr) { 45 return region->nic_base + 46 (trgt_addr - region->trgt_base); 47 } 48 } 49 50 return RTE_BAD_IOVA; 51 } 52 53 #ifdef __cplusplus 54 } 55 #endif 56 57 #endif /* _SFC_NIC_DMA_DP_H */ 58