1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2024 Realtek Corporation. All rights reserved 3 */ 4 5 #ifndef R8169_HW_H 6 #define R8169_HW_H 7 8 #include <stdint.h> 9 10 #include <bus_pci_driver.h> 11 #include <rte_ethdev.h> 12 #include <rte_ethdev_core.h> 13 14 #include "r8169_compat.h" 15 #include "r8169_ethdev.h" 16 #include "r8169_phy.h" 17 18 u16 rtl_mac_ocp_read(struct rtl_hw *hw, u16 addr); 19 void rtl_mac_ocp_write(struct rtl_hw *hw, u16 addr, u16 value); 20 21 u32 rtl_ocp_read(struct rtl_hw *hw, u16 addr, u8 len); 22 void rtl_ocp_write(struct rtl_hw *hw, u16 addr, u8 len, u32 value); 23 24 u32 rtl_csi_read(struct rtl_hw *hw, u32 addr); 25 void rtl_csi_write(struct rtl_hw *hw, u32 addr, u32 value); 26 27 void rtl_hw_config(struct rtl_hw *hw); 28 void rtl_nic_reset(struct rtl_hw *hw); 29 30 void rtl_enable_cfg9346_write(struct rtl_hw *hw); 31 void rtl_disable_cfg9346_write(struct rtl_hw *hw); 32 33 void rtl8125_oob_mutex_lock(struct rtl_hw *hw); 34 void rtl8125_oob_mutex_unlock(struct rtl_hw *hw); 35 36 void rtl_disable_rxdvgate(struct rtl_hw *hw); 37 38 int rtl_set_hw_ops(struct rtl_hw *hw); 39 40 void rtl_hw_disable_mac_mcu_bps(struct rtl_hw *hw); 41 42 void rtl_write_mac_mcu_ram_code(struct rtl_hw *hw, const u16 *entry, 43 u16 entry_cnt); 44 45 void rtl_hw_initialize(struct rtl_hw *hw); 46 47 bool rtl_is_speed_mode_valid(u32 speed); 48 49 void rtl_get_mac_version(struct rtl_hw *hw, struct rte_pci_device *pci_dev); 50 int rtl_get_mac_address(struct rtl_hw *hw, struct rte_ether_addr *ea); 51 52 void rtl_rar_set(struct rtl_hw *hw, uint8_t *addr); 53 54 void rtl_set_link_option(struct rtl_hw *hw, u8 autoneg, u32 speed, u8 duplex, 55 enum rtl_fc_mode fc); 56 57 void rtl_get_tally_stats(struct rtl_hw *hw, struct rte_eth_stats *rte_stats); 58 void rtl_clear_tally_stats(struct rtl_hw *hw); 59 60 int rtl_tally_init(struct rte_eth_dev *dev); 61 void rtl_tally_free(struct rte_eth_dev *dev); 62 63 extern const struct rtl_hw_ops rtl8125a_ops; 64 extern const struct rtl_hw_ops rtl8125b_ops; 65 extern const struct rtl_hw_ops rtl8125bp_ops; 66 extern const struct rtl_hw_ops rtl8125d_ops; 67 extern const struct rtl_hw_ops rtl8126a_ops; 68 69 #define NO_BASE_ADDRESS 0x00000000 70 71 /* Channel wait count */ 72 #define RTL_CHANNEL_WAIT_COUNT 20000 73 #define RTL_CHANNEL_WAIT_TIME 1 /* 1 us */ 74 #define RTL_CHANNEL_EXIT_DELAY_TIME 20 /* 20 us */ 75 76 #define ARRAY_SIZE(arr) RTE_DIM(arr) 77 78 #define HW_SUPPORT_MAC_MCU(_M) ((_M)->HwSuppMacMcuVer > 0) 79 #define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) ((_M)->HwHasWrRamCodeToMicroP ? 1 : 0) 80 81 /* Tx NO CLOSE */ 82 #define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000 83 #define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2 0xFFFF 84 #define MAX_TX_NO_CLOSE_DESC_PTR_V3 0x100000000 85 #define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3 0xFFFFFFFF 86 #define MAX_TX_NO_CLOSE_DESC_PTR_V4 0x80000000 87 #define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4 0x7FFFFFFF 88 #define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF 89 90 /* Ram code version */ 91 #define NIC_RAMCODE_VERSION_CFG_METHOD_48 (0x0b11) 92 #define NIC_RAMCODE_VERSION_CFG_METHOD_49 (0x0b33) 93 #define NIC_RAMCODE_VERSION_CFG_METHOD_50 (0x0b17) 94 #define NIC_RAMCODE_VERSION_CFG_METHOD_51 (0x0b99) 95 #define NIC_RAMCODE_VERSION_CFG_METHOD_54 (0x0013) 96 #define NIC_RAMCODE_VERSION_CFG_METHOD_55 (0x0001) 97 #define NIC_RAMCODE_VERSION_CFG_METHOD_56 (0x0016) 98 #define NIC_RAMCODE_VERSION_CFG_METHOD_57 (0x0001) 99 #define NIC_RAMCODE_VERSION_CFG_METHOD_69 (0x0023) 100 #define NIC_RAMCODE_VERSION_CFG_METHOD_70 (0x0033) 101 #define NIC_RAMCODE_VERSION_CFG_METHOD_71 (0x0051) 102 103 #define RTL_MAC_MCU_PAGE_SIZE 256 104 #define RTL_DEFAULT_MTU 1500 105 106 enum effuse { 107 EFUSE_NOT_SUPPORT = 0, 108 EFUSE_SUPPORT_V1, 109 EFUSE_SUPPORT_V2, 110 EFUSE_SUPPORT_V3, 111 EFUSE_SUPPORT_V4, 112 }; 113 114 #endif /* R8169_HW_H */ 115