1 /* 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 /**************************************************************************** 10 * 11 * Name: mcp_public.h 12 * 13 * Description: MCP public data 14 * 15 * Created: 13/01/2013 yanivr 16 * 17 ****************************************************************************/ 18 19 #ifndef MCP_PUBLIC_H 20 #define MCP_PUBLIC_H 21 22 #define VF_MAX_STATIC 192 /* In case of AH */ 23 24 #define MCP_GLOB_PATH_MAX 2 25 #define MCP_PORT_MAX 2 /* Global */ 26 #define MCP_GLOB_PORT_MAX 4 /* Global */ 27 #define MCP_GLOB_FUNC_MAX 16 /* Global */ 28 29 typedef u32 offsize_t; /* In DWORDS !!! */ 30 /* Offset from the beginning of the MCP scratchpad */ 31 #define OFFSIZE_OFFSET_OFFSET 0 32 #define OFFSIZE_OFFSET_MASK 0x0000ffff 33 /* Size of specific element (not the whole array if any) */ 34 #define OFFSIZE_SIZE_OFFSET 16 35 #define OFFSIZE_SIZE_MASK 0xffff0000 36 37 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 38 #define SECTION_OFFSET(_offsize) \ 39 ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) 40 41 /* SECTION_SIZE is calculating the size in bytes out of offsize */ 42 #define SECTION_SIZE(_offsize) \ 43 (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) 44 45 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index 46 * within section 47 */ 48 #define SECTION_ADDR(_offsize, idx) \ 49 (MCP_REG_SCRATCH + \ 50 SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 51 52 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use 53 * offsetof, since the OFFSETUP collide with the firmware definition 54 */ 55 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 56 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 57 /* PHY configuration */ 58 struct eth_phy_cfg { 59 /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 60 u32 speed; 61 #define ETH_SPEED_AUTONEG 0 62 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ 63 64 u32 pause; /* bitmask */ 65 #define ETH_PAUSE_NONE 0x0 66 #define ETH_PAUSE_AUTONEG 0x1 67 #define ETH_PAUSE_RX 0x2 68 #define ETH_PAUSE_TX 0x4 69 70 u32 adv_speed; /* Default should be the speed_cap_mask */ 71 u32 loopback_mode; 72 #define ETH_LOOPBACK_NONE (0) 73 /* Serdes loopback. In AH, it refers to Near End */ 74 #define ETH_LOOPBACK_INT_PHY (1) 75 #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 76 /* External Loopback (Require loopback plug) */ 77 #define ETH_LOOPBACK_EXT (3) 78 #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 79 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 80 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 81 #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 82 /* Loop RX packet from PCS to TX */ 83 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) 84 /* Remote Serdes Loopback (RX to TX) */ 85 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) 86 87 u32 eee_cfg; 88 /* EEE is enabled (configuration). Refer to eee_status->active for negotiated 89 * status 90 */ 91 #define EEE_CFG_EEE_ENABLED (1 << 0) 92 #define EEE_CFG_TX_LPI (1 << 1) 93 #define EEE_CFG_ADV_SPEED_1G (1 << 2) 94 #define EEE_CFG_ADV_SPEED_10G (1 << 3) 95 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 96 #define EEE_TX_TIMER_USEC_OFFSET 4 97 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 98 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 99 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 100 101 u32 link_modes; /* Additional link modes */ 102 #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ 103 }; 104 105 struct port_mf_cfg { 106 u32 dynamic_cfg; /* device control channel */ 107 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 108 #define PORT_MF_CFG_OV_TAG_OFFSET 0 109 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 110 111 u32 reserved[1]; 112 }; 113 114 /* DO NOT add new fields in the middle 115 * MUST be synced with struct pmm_stats_map 116 */ 117 struct eth_stats { 118 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 119 u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 120 u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 121 u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 122 u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 123 /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 124 u64 r1518; 125 union { 126 struct { /* bb */ 127 /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 128 u64 r1522; 129 /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 130 u64 r2047; 131 /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 132 u64 r4095; 133 /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 134 u64 r9216; 135 /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 136 u64 r16383; 137 } bb0; 138 struct { /* ah */ 139 u64 unused1; 140 /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ 141 u64 r1519_to_max; 142 u64 unused2; 143 u64 unused3; 144 u64 unused4; 145 } ah0; 146 } u0; 147 u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 148 u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 149 u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 150 u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 151 u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 152 u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 153 u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 154 u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 155 u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 156 u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 157 u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 158 u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 159 u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 160 u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 161 u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 162 /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 163 u64 t1518; 164 union { 165 struct { /* bb */ 166 /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 167 u64 t2047; 168 /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 169 u64 t4095; 170 /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 171 u64 t9216; 172 /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 173 u64 t16383; 174 } bb1; 175 struct { /* ah */ 176 /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ 177 u64 t1519_to_max; 178 u64 unused6; 179 u64 unused7; 180 u64 unused8; 181 } ah1; 182 } u1; 183 u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 184 u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 185 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 186 union { 187 struct { /* bb */ 188 /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 189 u64 tlpiec; 190 /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 191 u64 tncl; 192 } bb2; 193 struct { /* ah */ 194 u64 unused9; 195 u64 unused10; 196 } ah2; 197 } u2; 198 u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 199 u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 200 u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 201 u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 202 /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 203 u64 rxpok; 204 u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 205 u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 206 u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 207 u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 208 u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 209 /* HSI - Cannot add more stats to this struct. If needed, then need to open new 210 * struct 211 */ 212 213 }; 214 215 struct brb_stats { 216 u64 brb_truncate[8]; 217 u64 brb_discard[8]; 218 }; 219 220 struct port_stats { 221 struct brb_stats brb; 222 struct eth_stats eth; 223 }; 224 225 /*----+------------------------------------------------------------------------ 226 * C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 227 * h | rate of | team #1 | team #2 |are used|per path | (paths) 228 * i | physical | | | | | enabled 229 * p | ports | | | | | 230 *====+============+=========+=========+========+==========+=================== 231 * BB | 1x100G | This is special mode, where there are actually 2 HW func 232 * BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1 233 * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 234 * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 235 * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 236 * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 237 * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 238 * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 239 * AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA 240 * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 241 * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 242 * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 243 * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 244 *====+============+=========+=========+========+==========+=================== 245 */ 246 247 #define CMT_TEAM0 0 248 #define CMT_TEAM1 1 249 #define CMT_TEAM_MAX 2 250 251 struct couple_mode_teaming { 252 u8 port_cmt[MCP_GLOB_PORT_MAX]; 253 #define PORT_CMT_IN_TEAM (1 << 0) 254 255 #define PORT_CMT_PORT_ROLE (1 << 1) 256 #define PORT_CMT_PORT_INACTIVE (0 << 1) 257 #define PORT_CMT_PORT_ACTIVE (1 << 1) 258 259 #define PORT_CMT_TEAM_MASK (1 << 2) 260 #define PORT_CMT_TEAM0 (0 << 2) 261 #define PORT_CMT_TEAM1 (1 << 2) 262 }; 263 264 /************************************** 265 * LLDP and DCBX HSI structures 266 **************************************/ 267 #define LLDP_CHASSIS_ID_STAT_LEN 4 268 #define LLDP_PORT_ID_STAT_LEN 4 269 #define DCBX_MAX_APP_PROTOCOL 32 270 #define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ 271 #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ 272 typedef enum _lldp_agent_e { 273 LLDP_NEAREST_BRIDGE = 0, 274 LLDP_NEAREST_NON_TPMR_BRIDGE, 275 LLDP_NEAREST_CUSTOMER_BRIDGE, 276 LLDP_MAX_LLDP_AGENTS 277 } lldp_agent_e; 278 279 struct lldp_config_params_s { 280 u32 config; 281 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 282 #define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 283 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 284 #define LLDP_CONFIG_HOLD_OFFSET 8 285 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 286 #define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 287 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 288 #define LLDP_CONFIG_ENABLE_RX_OFFSET 30 289 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 290 #define LLDP_CONFIG_ENABLE_TX_OFFSET 31 291 /* Holds local Chassis ID TLV header, subtype and 9B of payload. 292 * If firtst byte is 0, then we will use default chassis ID 293 */ 294 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 295 /* Holds local Port ID TLV header, subtype and 9B of payload. 296 * If firtst byte is 0, then we will use default port ID 297 */ 298 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 299 }; 300 301 struct lldp_status_params_s { 302 u32 prefix_seq_num; 303 u32 status; /* TBD */ 304 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 305 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 306 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 307 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 308 u32 suffix_seq_num; 309 }; 310 311 struct dcbx_ets_feature { 312 u32 flags; 313 #define DCBX_ETS_ENABLED_MASK 0x00000001 314 #define DCBX_ETS_ENABLED_OFFSET 0 315 #define DCBX_ETS_WILLING_MASK 0x00000002 316 #define DCBX_ETS_WILLING_OFFSET 1 317 #define DCBX_ETS_ERROR_MASK 0x00000004 318 #define DCBX_ETS_ERROR_OFFSET 2 319 #define DCBX_ETS_CBS_MASK 0x00000008 320 #define DCBX_ETS_CBS_OFFSET 3 321 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 322 #define DCBX_ETS_MAX_TCS_OFFSET 4 323 #define DCBX_OOO_TC_MASK 0x00000f00 324 #define DCBX_OOO_TC_OFFSET 8 325 /* Entries in tc table are orginized that the left most is pri 0, right most is 326 * prio 7 327 */ 328 329 u32 pri_tc_tbl[1]; 330 /* Fixed TCP OOO TC usage is deprecated and used only for driver backward 331 * compatibility 332 */ 333 #define DCBX_TCP_OOO_TC (4) 334 #define DCBX_TCP_OOO_K2_4PORT_TC (3) 335 336 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 337 #define DCBX_CEE_STRICT_PRIORITY 0xf 338 /* Entries in tc table are orginized that the left most is pri 0, right most is 339 * prio 7 340 */ 341 342 u32 tc_bw_tbl[2]; 343 /* Entries in tc table are orginized that the left most is pri 0, right most is 344 * prio 7 345 */ 346 347 u32 tc_tsa_tbl[2]; 348 #define DCBX_ETS_TSA_STRICT 0 349 #define DCBX_ETS_TSA_CBS 1 350 #define DCBX_ETS_TSA_ETS 2 351 }; 352 353 struct dcbx_app_priority_entry { 354 u32 entry; 355 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 356 #define DCBX_APP_PRI_MAP_OFFSET 0 357 #define DCBX_APP_PRI_0 0x01 358 #define DCBX_APP_PRI_1 0x02 359 #define DCBX_APP_PRI_2 0x04 360 #define DCBX_APP_PRI_3 0x08 361 #define DCBX_APP_PRI_4 0x10 362 #define DCBX_APP_PRI_5 0x20 363 #define DCBX_APP_PRI_6 0x40 364 #define DCBX_APP_PRI_7 0x80 365 #define DCBX_APP_SF_MASK 0x00000300 366 #define DCBX_APP_SF_OFFSET 8 367 #define DCBX_APP_SF_ETHTYPE 0 368 #define DCBX_APP_SF_PORT 1 369 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 370 #define DCBX_APP_SF_IEEE_OFFSET 12 371 #define DCBX_APP_SF_IEEE_RESERVED 0 372 #define DCBX_APP_SF_IEEE_ETHTYPE 1 373 #define DCBX_APP_SF_IEEE_TCP_PORT 2 374 #define DCBX_APP_SF_IEEE_UDP_PORT 3 375 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 376 377 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 378 #define DCBX_APP_PROTOCOL_ID_OFFSET 16 379 }; 380 381 382 /* FW structure in BE */ 383 struct dcbx_app_priority_feature { 384 u32 flags; 385 #define DCBX_APP_ENABLED_MASK 0x00000001 386 #define DCBX_APP_ENABLED_OFFSET 0 387 #define DCBX_APP_WILLING_MASK 0x00000002 388 #define DCBX_APP_WILLING_OFFSET 1 389 #define DCBX_APP_ERROR_MASK 0x00000004 390 #define DCBX_APP_ERROR_OFFSET 2 391 /* Not in use 392 #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 393 #define DCBX_APP_DEFAULT_PRI_OFFSET 8 394 */ 395 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 396 #define DCBX_APP_MAX_TCS_OFFSET 12 397 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 398 #define DCBX_APP_NUM_ENTRIES_OFFSET 16 399 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 400 }; 401 402 /* FW structure in BE */ 403 struct dcbx_features { 404 /* PG feature */ 405 struct dcbx_ets_feature ets; 406 /* PFC feature */ 407 u32 pfc; 408 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 409 #define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 410 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 411 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 412 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 413 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 414 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 415 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 416 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 417 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 418 419 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 420 #define DCBX_PFC_FLAGS_OFFSET 8 421 #define DCBX_PFC_CAPS_MASK 0x00000f00 422 #define DCBX_PFC_CAPS_OFFSET 8 423 #define DCBX_PFC_MBC_MASK 0x00004000 424 #define DCBX_PFC_MBC_OFFSET 14 425 #define DCBX_PFC_WILLING_MASK 0x00008000 426 #define DCBX_PFC_WILLING_OFFSET 15 427 #define DCBX_PFC_ENABLED_MASK 0x00010000 428 #define DCBX_PFC_ENABLED_OFFSET 16 429 #define DCBX_PFC_ERROR_MASK 0x00020000 430 #define DCBX_PFC_ERROR_OFFSET 17 431 432 /* APP feature */ 433 struct dcbx_app_priority_feature app; 434 }; 435 436 struct dcbx_local_params { 437 u32 config; 438 #define DCBX_CONFIG_VERSION_MASK 0x00000007 439 #define DCBX_CONFIG_VERSION_OFFSET 0 440 #define DCBX_CONFIG_VERSION_DISABLED 0 441 #define DCBX_CONFIG_VERSION_IEEE 1 442 #define DCBX_CONFIG_VERSION_CEE 2 443 #define DCBX_CONFIG_VERSION_DYNAMIC \ 444 (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) 445 #define DCBX_CONFIG_VERSION_STATIC 4 446 447 u32 flags; 448 struct dcbx_features features; 449 }; 450 451 struct dcbx_mib { 452 u32 prefix_seq_num; 453 u32 flags; 454 /* 455 #define DCBX_CONFIG_VERSION_MASK 0x00000007 456 #define DCBX_CONFIG_VERSION_OFFSET 0 457 #define DCBX_CONFIG_VERSION_DISABLED 0 458 #define DCBX_CONFIG_VERSION_IEEE 1 459 #define DCBX_CONFIG_VERSION_CEE 2 460 #define DCBX_CONFIG_VERSION_STATIC 4 461 */ 462 struct dcbx_features features; 463 u32 suffix_seq_num; 464 }; 465 466 struct lldp_system_tlvs_buffer_s { 467 u32 flags; 468 #define LLDP_SYSTEM_TLV_VALID_MASK 0x1 469 #define LLDP_SYSTEM_TLV_VALID_OFFSET 0 470 /* This bit defines if system TLVs are instead of mandatory TLVS or in 471 * addition to them. Set 1 for replacing mandatory TLVs 472 */ 473 #define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 474 #define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 475 #define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 476 #define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 477 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 478 }; 479 480 /* Since this struct is written by MFW and read by driver need to add 481 * sequence guards (as in case of DCBX MIB) 482 */ 483 struct lldp_received_tlvs_s { 484 u32 prefix_seq_num; 485 u32 length; 486 u32 tlvs_buffer[MAX_TLV_BUFFER]; 487 u32 suffix_seq_num; 488 }; 489 490 struct dcb_dscp_map { 491 u32 flags; 492 #define DCB_DSCP_ENABLE_MASK 0x1 493 #define DCB_DSCP_ENABLE_OFFSET 0 494 #define DCB_DSCP_ENABLE 1 495 u32 dscp_pri_map[8]; 496 }; 497 498 /************************************** 499 * Attributes commands 500 **************************************/ 501 502 enum _attribute_commands_e { 503 ATTRIBUTE_CMD_READ = 0, 504 ATTRIBUTE_CMD_WRITE, 505 ATTRIBUTE_CMD_READ_CLEAR, 506 ATTRIBUTE_CMD_CLEAR, 507 ATTRIBUTE_NUM_OF_COMMANDS 508 }; 509 510 /**************************************/ 511 /* */ 512 /* P U B L I C G L O B A L */ 513 /* */ 514 /**************************************/ 515 struct public_global { 516 u32 max_path; /* 32bit is wasty, but this will be used often */ 517 /* (Global) 32bit is wasty, but this will be used often */ 518 u32 max_ports; 519 #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 520 #define MODE_2P 2 521 #define MODE_3P 3 522 #define MODE_4P 4 523 u32 debug_mb_offset; 524 u32 phymod_dbg_mb_offset; 525 struct couple_mode_teaming cmt; 526 /* Temperature in Celcius (-255C / +255C), measured every second. */ 527 s32 internal_temperature; 528 u32 mfw_ver; 529 u32 running_bundle_id; 530 s32 external_temperature; 531 u32 mdump_reason; 532 #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 533 #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 534 #define MDUMP_REASON_DUMP_AGED (1 << 2) 535 u32 ext_phy_upgrade_fw; 536 #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 537 #define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) 538 #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 539 #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 540 #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 541 #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 542 #define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) 543 }; 544 545 /**************************************/ 546 /* */ 547 /* P U B L I C P A T H */ 548 /* */ 549 /**************************************/ 550 551 /**************************************************************************** 552 * Shared Memory 2 Region * 553 ****************************************************************************/ 554 /* The fw_flr_ack is actually built in the following way: */ 555 /* 8 bit: PF ack */ 556 /* 128 bit: VF ack */ 557 /* 8 bit: ios_dis_ack */ 558 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 559 /* u32. The fw must have the VF right after the PF since this is how it */ 560 /* access arrays(it expects always the VF to reside after the PF, and that */ 561 /* makes the calculation much easier for it. ) */ 562 /* In order to answer both limitations, and keep the struct small, the code */ 563 /* will abuse the structure defined here to achieve the actual partition */ 564 /* above */ 565 /****************************************************************************/ 566 struct fw_flr_mb { 567 u32 aggint; 568 u32 opgen_addr; 569 u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 570 #define ACCUM_ACK_PF_BASE 0 571 #define ACCUM_ACK_PF_SHIFT 0 572 573 #define ACCUM_ACK_VF_BASE 8 574 #define ACCUM_ACK_VF_SHIFT 3 575 576 #define ACCUM_ACK_IOV_DIS_BASE 256 577 #define ACCUM_ACK_IOV_DIS_SHIFT 8 578 579 }; 580 581 struct public_path { 582 struct fw_flr_mb flr_mb; 583 /* 584 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 585 * which were disabled/flred 586 */ 587 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 588 589 /* Reset on mcp reset, and incremented for eveny process kill event. */ 590 u32 process_kill; 591 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 592 #define PROCESS_KILL_COUNTER_OFFSET 0 593 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 594 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 595 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 596 }; 597 598 /**************************************/ 599 /* */ 600 /* P U B L I C P O R T */ 601 /* */ 602 /**************************************/ 603 #define FC_NPIV_WWPN_SIZE 8 604 #define FC_NPIV_WWNN_SIZE 8 605 struct dci_npiv_settings { 606 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 607 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 608 }; 609 610 struct dci_fc_npiv_cfg { 611 /* hdr used internally by the MFW */ 612 u32 hdr; 613 u32 num_of_npiv; 614 }; 615 616 #define MAX_NUMBER_NPIV 64 617 struct dci_fc_npiv_tbl { 618 struct dci_fc_npiv_cfg fc_npiv_cfg; 619 struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 620 }; 621 622 /**************************************************************************** 623 * Driver <-> FW Mailbox * 624 ****************************************************************************/ 625 626 struct public_port { 627 u32 validity_map; /* 0x0 (4*2 = 0x8) */ 628 629 /* validity bits */ 630 #define MCP_VALIDITY_PCI_CFG 0x00100000 631 #define MCP_VALIDITY_MB 0x00200000 632 #define MCP_VALIDITY_DEV_INFO 0x00400000 633 #define MCP_VALIDITY_RESERVED 0x00000007 634 635 /* One licensing bit should be set */ 636 /* yaniv - tbd ? license */ 637 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 638 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 639 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 640 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 641 642 /* Active MFW */ 643 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 644 #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 645 #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 646 #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 647 648 u32 link_status; 649 #define LINK_STATUS_LINK_UP 0x00000001 650 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 651 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 652 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 653 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 654 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 655 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 656 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 657 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 658 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 659 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 660 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 661 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 662 #define LINK_STATUS_PFC_ENABLED 0x00000100 663 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 664 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 665 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 666 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 667 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 668 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 669 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 670 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 671 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 672 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 673 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 674 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 675 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 676 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 677 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 678 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 679 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 680 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 681 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 682 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 683 #define LINK_STATUS_FEC_MODE_MASK 0x38000000 684 #define LINK_STATUS_FEC_MODE_NONE (0 << 27) 685 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27) 686 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27) 687 #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 688 689 u32 link_status1; 690 u32 ext_phy_fw_version; 691 /* Points to struct eth_phy_cfg (For READ-ONLY) */ 692 u32 drv_phy_cfg_addr; 693 694 u32 port_stx; 695 696 u32 stat_nig_timer; 697 698 struct port_mf_cfg port_mf_config; 699 struct port_stats stats; 700 701 u32 media_type; 702 #define MEDIA_UNSPECIFIED 0x0 703 #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 704 #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 705 #define MEDIA_DA_TWINAX 0x3 706 #define MEDIA_BASE_T 0x4 707 #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 708 #define MEDIA_MODULE_FIBER 0x6 709 #define MEDIA_KR 0xf0 710 #define MEDIA_NOT_PRESENT 0xff 711 712 u32 lfa_status; 713 #define LFA_LINK_FLAP_REASON_OFFSET 0 714 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 715 #define LFA_NO_REASON (0 << 0) 716 #define LFA_LINK_DOWN (1 << 0) 717 #define LFA_FORCE_INIT (1 << 1) 718 #define LFA_LOOPBACK_MISMATCH (1 << 2) 719 #define LFA_SPEED_MISMATCH (1 << 3) 720 #define LFA_FLOW_CTRL_MISMATCH (1 << 4) 721 #define LFA_ADV_SPEED_MISMATCH (1 << 5) 722 #define LFA_EEE_MISMATCH (1 << 6) 723 #define LFA_LINK_MODES_MISMATCH (1 << 7) 724 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 725 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 726 #define LINK_FLAP_COUNT_OFFSET 16 727 #define LINK_FLAP_COUNT_MASK 0x00ff0000 728 729 u32 link_change_count; 730 731 /* LLDP params */ 732 /* offset: 536 bytes? */ 733 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 734 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 735 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 736 737 /* DCBX related MIB */ 738 struct dcbx_local_params local_admin_dcbx_mib; 739 struct dcbx_mib remote_dcbx_mib; 740 struct dcbx_mib operational_dcbx_mib; 741 742 /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 743 744 u32 fc_npiv_nvram_tbl_addr; 745 u32 fc_npiv_nvram_tbl_size; 746 u32 transceiver_data; 747 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 748 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 749 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 750 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 751 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 752 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 753 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 754 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x00000008 755 #define ETH_TRANSCEIVER_TYPE_NONE 0x00000000 756 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0x000000FF 757 /* 1G Passive copper cable */ 758 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 759 /* 1G Active copper cable */ 760 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 761 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 762 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 763 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 764 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 765 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 766 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 767 /* 10G Passive copper cable */ 768 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 769 /* 10G Active copper cable */ 770 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 771 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 772 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 773 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 774 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 775 /* Active optical cable */ 776 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 777 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 778 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 779 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 780 /* Active copper cable */ 781 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 782 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 783 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 784 /* 25G Passive copper cable - short */ 785 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 786 /* 25G Active copper cable - short */ 787 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 788 /* 25G Passive copper cable - medium */ 789 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 790 /* 25G Active copper cable - medium */ 791 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 792 /* 25G Passive copper cable - long */ 793 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 794 /* 25G Active copper cable - long */ 795 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 796 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 797 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 798 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 799 800 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 801 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 802 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 803 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 804 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 805 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 806 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 807 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 808 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 809 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 810 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 811 u32 wol_info; 812 u32 wol_pkt_len; 813 u32 wol_pkt_details; 814 struct dcb_dscp_map dcb_dscp_map; 815 816 u32 eee_status; 817 /* Set when EEE negotiation is complete. */ 818 #define EEE_ACTIVE_BIT (1 << 0) 819 820 /* Shows the Local Device EEE capabilities */ 821 #define EEE_LD_ADV_STATUS_MASK 0x000000f0 822 #define EEE_LD_ADV_STATUS_OFFSET 4 823 #define EEE_1G_ADV (1 << 1) 824 #define EEE_10G_ADV (1 << 2) 825 /* Same values as in EEE_LD_ADV, but for Link Parter */ 826 #define EEE_LP_ADV_STATUS_MASK 0x00000f00 827 #define EEE_LP_ADV_STATUS_OFFSET 8 828 829 /* Supported speeds for EEE */ 830 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 831 #define EEE_SUPPORTED_SPEED_OFFSET 12 832 #define EEE_1G_SUPPORTED (1 << 1) 833 #define EEE_10G_SUPPORTED (1 << 2) 834 835 u32 eee_remote; /* Used for EEE in LLDP */ 836 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 837 #define EEE_REMOTE_TW_TX_OFFSET 0 838 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 839 #define EEE_REMOTE_TW_RX_OFFSET 16 840 841 u32 module_info; 842 #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF 843 #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 844 #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) 845 #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) 846 #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) 847 #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) 848 #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) 849 #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 850 #define ETH_TRANSCEIVER_IDENT_OFFSET 8 851 852 u32 oem_cfg_port; 853 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 854 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 855 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 856 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 857 858 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 859 #define OEM_CFG_SCHED_TYPE_OFFSET 2 860 #define OEM_CFG_SCHED_TYPE_ETS 0x1 861 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 862 863 struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; 864 u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; 865 }; 866 867 /**************************************/ 868 /* */ 869 /* P U B L I C F U N C */ 870 /* */ 871 /**************************************/ 872 873 struct public_func { 874 u32 iscsi_boot_signature; 875 u32 iscsi_boot_block_offset; 876 877 /* MTU size per funciton is needed for the OV feature */ 878 u32 mtu_size; 879 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 880 881 /* For PCP values 0-3 use the map lower */ 882 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 883 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 884 */ 885 u32 c2s_pcp_map_lower; 886 /* For PCP values 4-7 use the map upper */ 887 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 888 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 889 */ 890 u32 c2s_pcp_map_upper; 891 892 /* For PCP default value get the MSB byte of the map default */ 893 u32 c2s_pcp_map_default; 894 895 u32 reserved[4]; 896 897 /* replace old mf_cfg */ 898 u32 config; 899 /* E/R/I/D */ 900 /* function 0 of each port cannot be hidden */ 901 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 902 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 903 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 904 905 906 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 907 #define FUNC_MF_CFG_PROTOCOL_OFFSET 4 908 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 909 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 910 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 911 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 912 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 913 914 /* MINBW, MAXBW */ 915 /* value range - 0..100, increments in 1 % */ 916 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 917 #define FUNC_MF_CFG_MIN_BW_OFFSET 8 918 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 919 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 920 #define FUNC_MF_CFG_MAX_BW_OFFSET 16 921 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 922 923 u32 status; 924 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 925 #define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 926 #define FUNC_STATUS_FORCED_LINK 0x00000004 927 928 u32 mac_upper; /* MAC */ 929 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 930 #define FUNC_MF_CFG_UPPERMAC_OFFSET 0 931 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 932 u32 mac_lower; 933 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 934 935 u32 fcoe_wwn_port_name_upper; 936 u32 fcoe_wwn_port_name_lower; 937 938 u32 fcoe_wwn_node_name_upper; 939 u32 fcoe_wwn_node_name_lower; 940 941 u32 ovlan_stag; /* tags */ 942 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 943 #define FUNC_MF_CFG_OV_STAG_OFFSET 0 944 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 945 946 u32 pf_allocation; /* vf per pf */ 947 948 u32 preserve_data; /* Will be used bt CCM */ 949 950 u32 driver_last_activity_ts; 951 952 /* 953 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 954 * VFs 955 */ 956 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 957 958 u32 drv_id; 959 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 960 #define DRV_ID_PDA_COMP_VER_OFFSET 0 961 962 #define LOAD_REQ_HSI_VERSION 2 963 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 964 #define DRV_ID_MCP_HSI_VER_OFFSET 16 965 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 966 DRV_ID_MCP_HSI_VER_OFFSET) 967 968 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 969 #define DRV_ID_DRV_TYPE_OFFSET 24 970 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) 971 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) 972 #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) 973 #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) 974 #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) 975 #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) 976 #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) 977 #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) 978 #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) 979 980 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 981 #define DRV_ID_DRV_INIT_HW_OFFSET 31 982 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) 983 984 u32 oem_cfg_func; 985 #define OEM_CFG_FUNC_TC_MASK 0x0000000F 986 #define OEM_CFG_FUNC_TC_OFFSET 0 987 #define OEM_CFG_FUNC_TC_0 0x0 988 #define OEM_CFG_FUNC_TC_1 0x1 989 #define OEM_CFG_FUNC_TC_2 0x2 990 #define OEM_CFG_FUNC_TC_3 0x3 991 #define OEM_CFG_FUNC_TC_4 0x4 992 #define OEM_CFG_FUNC_TC_5 0x5 993 #define OEM_CFG_FUNC_TC_6 0x6 994 #define OEM_CFG_FUNC_TC_7 0x7 995 996 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 997 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 998 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 999 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 1000 }; 1001 1002 /**************************************/ 1003 /* */ 1004 /* P U B L I C M B */ 1005 /* */ 1006 /**************************************/ 1007 /* This is the only section that the driver can write to, and each */ 1008 /* Basically each driver request to set feature parameters, 1009 * will be done using a different command, which will be linked 1010 * to a specific data structure from the union below. 1011 * For huge strucuture, the common blank structure should be used. 1012 */ 1013 1014 struct mcp_mac { 1015 u32 mac_upper; /* Upper 16 bits are always zeroes */ 1016 u32 mac_lower; 1017 }; 1018 1019 struct mcp_val64 { 1020 u32 lo; 1021 u32 hi; 1022 }; 1023 1024 struct mcp_file_att { 1025 u32 nvm_start_addr; 1026 u32 len; 1027 }; 1028 1029 struct bist_nvm_image_att { 1030 u32 return_code; 1031 u32 image_type; /* Image type */ 1032 u32 nvm_start_addr; /* NVM address of the image */ 1033 u32 len; /* Include CRC */ 1034 }; 1035 1036 #define MCP_DRV_VER_STR_SIZE 16 1037 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 1038 #define MCP_DRV_NVM_BUF_LEN 32 1039 struct drv_version_stc { 1040 u32 version; 1041 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 1042 }; 1043 1044 /* statistics for ncsi */ 1045 struct lan_stats_stc { 1046 u64 ucast_rx_pkts; 1047 u64 ucast_tx_pkts; 1048 u32 fcs_err; 1049 u32 rserved; 1050 }; 1051 1052 struct fcoe_stats_stc { 1053 u64 rx_pkts; 1054 u64 tx_pkts; 1055 u32 fcs_err; 1056 u32 login_failure; 1057 }; 1058 1059 struct iscsi_stats_stc { 1060 u64 rx_pdus; 1061 u64 tx_pdus; 1062 u64 rx_bytes; 1063 u64 tx_bytes; 1064 }; 1065 1066 struct rdma_stats_stc { 1067 u64 rx_pkts; 1068 u64 tx_pkts; 1069 u64 rx_bytes; 1070 u64 tx_bytes; 1071 }; 1072 1073 struct ocbb_data_stc { 1074 u32 ocbb_host_addr; 1075 u32 ocsd_host_addr; 1076 u32 ocsd_req_update_interval; 1077 }; 1078 1079 #define MAX_NUM_OF_SENSORS 7 1080 #define MFW_SENSOR_LOCATION_INTERNAL 1 1081 #define MFW_SENSOR_LOCATION_EXTERNAL 2 1082 #define MFW_SENSOR_LOCATION_SFP 3 1083 1084 #define SENSOR_LOCATION_OFFSET 0 1085 #define SENSOR_LOCATION_MASK 0x000000ff 1086 #define THRESHOLD_HIGH_OFFSET 8 1087 #define THRESHOLD_HIGH_MASK 0x0000ff00 1088 #define CRITICAL_TEMPERATURE_OFFSET 16 1089 #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 1090 #define CURRENT_TEMP_OFFSET 24 1091 #define CURRENT_TEMP_MASK 0xff000000 1092 struct temperature_status_stc { 1093 u32 num_of_sensors; 1094 u32 sensor[MAX_NUM_OF_SENSORS]; 1095 }; 1096 1097 /* crash dump configuration header */ 1098 struct mdump_config_stc { 1099 u32 version; 1100 u32 config; 1101 u32 epoc; 1102 u32 num_of_logs; 1103 u32 valid_logs; 1104 }; 1105 1106 enum resource_id_enum { 1107 RESOURCE_NUM_SB_E = 0, 1108 RESOURCE_NUM_L2_QUEUE_E = 1, 1109 RESOURCE_NUM_VPORT_E = 2, 1110 RESOURCE_NUM_VMQ_E = 3, 1111 /* Not a real resource!! it's a factor used to calculate others */ 1112 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 1113 /* Not a real resource!! it's a factor used to calculate others */ 1114 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 1115 RESOURCE_NUM_RL_E = 6, 1116 RESOURCE_NUM_PQ_E = 7, 1117 RESOURCE_NUM_VF_E = 8, 1118 RESOURCE_VFC_FILTER_E = 9, 1119 RESOURCE_ILT_E = 10, 1120 RESOURCE_CQS_E = 11, 1121 RESOURCE_GFT_PROFILES_E = 12, 1122 RESOURCE_NUM_TC_E = 13, 1123 RESOURCE_NUM_RSS_ENGINES_E = 14, 1124 RESOURCE_LL2_QUEUE_E = 15, 1125 RESOURCE_RDMA_STATS_QUEUE_E = 16, 1126 RESOURCE_BDQ_E = 17, 1127 RESOURCE_MAX_NUM, 1128 RESOURCE_NUM_INVALID = 0xFFFFFFFF 1129 }; 1130 1131 /* Resource ID is to be filled by the driver in the MB request 1132 * Size, offset & flags to be filled by the MFW in the MB response 1133 */ 1134 struct resource_info { 1135 enum resource_id_enum res_id; 1136 u32 size; /* number of allocated resources */ 1137 u32 offset; /* Offset of the 1st resource */ 1138 u32 vf_size; 1139 u32 vf_offset; 1140 u32 flags; 1141 #define RESOURCE_ELEMENT_STRICT (1 << 0) 1142 }; 1143 1144 #define DRV_ROLE_NONE 0 1145 #define DRV_ROLE_PREBOOT 1 1146 #define DRV_ROLE_OS 2 1147 #define DRV_ROLE_KDUMP 3 1148 1149 struct load_req_stc { 1150 u32 drv_ver_0; 1151 u32 drv_ver_1; 1152 u32 fw_ver; 1153 u32 misc0; 1154 #define LOAD_REQ_ROLE_MASK 0x000000FF 1155 #define LOAD_REQ_ROLE_OFFSET 0 1156 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1157 #define LOAD_REQ_LOCK_TO_OFFSET 8 1158 #define LOAD_REQ_LOCK_TO_DEFAULT 0 1159 #define LOAD_REQ_LOCK_TO_NONE 255 1160 #define LOAD_REQ_FORCE_MASK 0x000F0000 1161 #define LOAD_REQ_FORCE_OFFSET 16 1162 #define LOAD_REQ_FORCE_NONE 0 1163 #define LOAD_REQ_FORCE_PF 1 1164 #define LOAD_REQ_FORCE_ALL 2 1165 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 1166 #define LOAD_REQ_FLAGS0_OFFSET 20 1167 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1168 }; 1169 1170 struct load_rsp_stc { 1171 u32 drv_ver_0; 1172 u32 drv_ver_1; 1173 u32 fw_ver; 1174 u32 misc0; 1175 #define LOAD_RSP_ROLE_MASK 0x000000FF 1176 #define LOAD_RSP_ROLE_OFFSET 0 1177 #define LOAD_RSP_HSI_MASK 0x0000FF00 1178 #define LOAD_RSP_HSI_OFFSET 8 1179 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 1180 #define LOAD_RSP_FLAGS0_OFFSET 16 1181 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1182 }; 1183 1184 struct mdump_retain_data_stc { 1185 u32 valid; 1186 u32 epoch; 1187 u32 pf; 1188 u32 status; 1189 }; 1190 1191 struct attribute_cmd_write_stc { 1192 u32 val; 1193 u32 mask; 1194 u32 offset; 1195 }; 1196 1197 union drv_union_data { 1198 struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1199 1200 /* This configuration should be set by the driver for the LINK_SET command. */ 1201 1202 struct eth_phy_cfg drv_phy_cfg; 1203 1204 struct mcp_val64 val64; /* For PHY / AVS commands */ 1205 1206 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1207 1208 struct mcp_file_att file_att; 1209 1210 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1211 1212 struct drv_version_stc drv_version; 1213 1214 struct lan_stats_stc lan_stats; 1215 struct fcoe_stats_stc fcoe_stats; 1216 struct iscsi_stats_stc iscsi_stats; 1217 struct rdma_stats_stc rdma_stats; 1218 struct ocbb_data_stc ocbb_info; 1219 struct temperature_status_stc temp_info; 1220 struct resource_info resource; 1221 struct bist_nvm_image_att nvm_image_att; 1222 struct mdump_config_stc mdump_config; 1223 u32 dword; 1224 1225 struct load_req_stc load_req; 1226 struct load_rsp_stc load_rsp; 1227 struct mdump_retain_data_stc mdump_retain; 1228 struct attribute_cmd_write_stc attribute_cmd_write; 1229 /* ... */ 1230 }; 1231 1232 struct public_drv_mb { 1233 u32 drv_mb_header; 1234 #define DRV_MSG_CODE_MASK 0xffff0000 1235 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1236 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1237 #define DRV_MSG_CODE_INIT_HW 0x12000000 1238 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1239 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1240 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1241 #define DRV_MSG_CODE_INIT_PHY 0x22000000 1242 /* Params - FORCE - Reinitialize the link regardless of LFA */ 1243 /* - DONT_CARE - Don't flap the link if up */ 1244 #define DRV_MSG_CODE_LINK_RESET 0x23000000 1245 1246 #define DRV_MSG_CODE_SET_LLDP 0x24000000 1247 #define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 1248 #define DRV_MSG_CODE_SET_DCBX 0x25000000 1249 /* OneView feature driver HSI*/ 1250 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1251 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1252 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1253 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1254 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1255 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1256 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1257 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1258 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, 1259 * data: struct resource_info 1260 */ 1261 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 1262 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1263 1264 /*deprecated don't use*/ 1265 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 1266 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1267 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1268 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1269 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 1270 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1271 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 1272 /* Param should be set to the transaction size (up to 64 bytes) */ 1273 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 1274 /* MFW will place the file offset and len in file_att struct */ 1275 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 1276 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] - 1277 * ??? Len in Bytes 1278 */ 1279 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 1280 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] 1281 * ??? Len in Bytes. In case this address is in the range of secured file in 1282 * secured mode, the operation will fail 1283 */ 1284 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 1285 /* Delete a file from nvram. Param is image_type. */ 1286 #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 1287 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. 1288 * In case operation succeed, MCP will not ack back. 1289 */ 1290 #define DRV_MSG_CODE_MCP_RESET 0x00090000 1291 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1292 * 1 (Secure) / 2 (Full-Secure) 1293 */ 1294 #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 1295 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1296 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1297 * [30:31] - port 1298 */ 1299 #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 1300 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 1301 * 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, 1302 * [30:31] - port 1303 */ 1304 #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 1305 /* Param: [0:15] - Address, [30:31] - port */ 1306 #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 1307 /* Param: [0:15] - Address, [30:31] - port */ 1308 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 1309 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1310 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 1311 /* Halts the MCP. To resume MCP, user will need to use 1312 * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. 1313 */ 1314 #define DRV_MSG_CODE_MCP_HALT 0x00100000 1315 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1316 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1317 */ 1318 #define DRV_MSG_CODE_SET_VMAC 0x00110000 1319 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, 1320 * [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN 1321 */ 1322 #define DRV_MSG_CODE_GET_VMAC 0x00120000 1323 #define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 1324 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1325 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1326 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1327 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1328 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1329 #define DRV_MSG_CODE_GET_STATS 0x00130000 1330 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1331 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1332 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1333 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1334 /* Host shall provide buffer and size for MFW */ 1335 #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 1336 /* Host shall provide buffer and size for MFW */ 1337 #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 1338 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, 1339 * [16:31] - offset 1340 */ 1341 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 1342 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, 1343 * [16:31] - offset 1344 */ 1345 #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 1346 /* indicate OCBB related information */ 1347 #define DRV_MSG_CODE_OCBB_DATA 0x00180000 1348 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1349 #define DRV_MSG_CODE_SET_BW 0x00190000 1350 #define BW_MAX_MASK 0x000000ff 1351 #define BW_MAX_OFFSET 0 1352 #define BW_MIN_MASK 0x0000ff00 1353 #define BW_MIN_OFFSET 8 1354 1355 /* When param is set to 1, all parities will be masked(disabled). When params 1356 * are set to 0, parities will be unmasked again. 1357 */ 1358 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 1359 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1360 #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 1361 #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1362 #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1363 /* Param: [0:15] - gpio number */ 1364 #define DRV_MSG_CODE_GPIO_READ 0x001c0000 1365 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1366 #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 1367 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1368 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 1369 #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1370 1371 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1372 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 1373 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - 1374 * driver version (MAJ MIN BUILD SUB) 1375 */ 1376 #define DRV_MSG_CODE_TIMESTAMP 0x00210000 1377 /* This is an empty mailbox just return OK*/ 1378 #define DRV_MSG_CODE_EMPTY_MB 0x00220000 1379 1380 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, 1381 * param[15:8] - age 1382 */ 1383 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 1384 1385 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1386 #define RESOURCE_CMD_REQ_RESC_OFFSET 0 1387 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1388 #define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 1389 /* request resource ownership with default aging */ 1390 #define RESOURCE_OPCODE_REQ 1 1391 /* request resource ownership without aging */ 1392 #define RESOURCE_OPCODE_REQ_WO_AGING 2 1393 /* request resource ownership with specific aging timer (in seconds) */ 1394 #define RESOURCE_OPCODE_REQ_W_AGING 3 1395 #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1396 /* force resource release */ 1397 #define RESOURCE_OPCODE_FORCE_RELEASE 5 1398 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1399 #define RESOURCE_CMD_REQ_AGE_OFFSET 8 1400 1401 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1402 #define RESOURCE_CMD_RSP_OWNER_OFFSET 0 1403 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1404 #define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 1405 /* resource is free and granted to requester */ 1406 #define RESOURCE_OPCODE_GNT 1 1407 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 1408 * 16 = MFW, 17 = diag over serial 1409 */ 1410 #define RESOURCE_OPCODE_BUSY 2 1411 /* indicate release request was acknowledged */ 1412 #define RESOURCE_OPCODE_RELEASED 3 1413 /* indicate release request was previously received by other owner */ 1414 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 1415 /* indicate wrong owner during release */ 1416 #define RESOURCE_OPCODE_WRONG_OWNER 5 1417 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1418 1419 /* dedicate resource 0 for dump */ 1420 #define RESOURCE_DUMP 0 1421 1422 #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1423 /* Send crash dump commands with param[3:0] - opcode */ 1424 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 1425 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1426 /* acknowledge reception of error indication */ 1427 #define DRV_MSG_CODE_MDUMP_ACK 0x01 1428 /* set epoc and personality as follow: drv_data[3:0] - epoch, 1429 * drv_data[7:4] - personality 1430 */ 1431 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 1432 /* trigger crash dump procedure */ 1433 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 1434 /* Request valid logs and config words */ 1435 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 1436 /* Set triggers mask. drv_mb_param should indicate (bitwise) which 1437 * trigger enabled 1438 */ 1439 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 1440 /* Clear all logs */ 1441 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 1442 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ 1443 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ 1444 #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1445 /* Param: [0:15] - gpio number */ 1446 #define DRV_MSG_CODE_GPIO_INFO 0x00270000 1447 /* Value will be placed in union */ 1448 #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 1449 /* Value should be placed in union */ 1450 #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 1451 #define DRV_MB_PARAM_ADDR_OFFSET 0 1452 #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1453 #define DRV_MB_PARAM_DEVAD_OFFSET 16 1454 #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1455 #define DRV_MB_PARAM_PORT_OFFSET 21 1456 #define DRV_MB_PARAM_PORT_MASK 0x00600000 1457 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1458 1459 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ 1460 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ 1461 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 1462 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ 1463 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 1464 #define DRV_MSG_CODE_READ_WOL_REG 0X00320000 1465 #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 1466 #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 1467 /* Param: [0:23] Attribute key, [24:31] Attribute sub command */ 1468 #define DRV_MSG_CODE_ATTRIBUTE 0x00350000 1469 1470 /* Param: Password len. Union: Plain Password */ 1471 #define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 1472 1473 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1474 1475 u32 drv_mb_param; 1476 /* UNLOAD_REQ params */ 1477 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1478 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1479 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1480 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1481 1482 /* UNLOAD_DONE_params */ 1483 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1484 1485 /* INIT_PHY params */ 1486 #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1487 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1488 1489 /* LLDP / DCBX params*/ 1490 /* To be used with SET_LLDP command */ 1491 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1492 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 1493 /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ 1494 #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1495 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 1496 /* To be used with REGISTER_LLDP_TLVS_RX command */ 1497 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 1498 #define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 1499 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 1500 #define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 1501 /* To be used with SET_DCBX command */ 1502 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1503 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 1504 1505 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1506 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 1507 1508 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1509 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1510 1511 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 1512 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1513 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 1514 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1515 1516 #define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 1517 #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1518 #define DRV_MB_PARAM_PHY_LANE_OFFSET 16 1519 #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1520 #define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 1521 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1522 #define DRV_MB_PARAM_PHY_PORT_OFFSET 30 1523 #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1524 1525 #define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 1526 #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1527 #define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 1528 #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1529 /* configure vf MSIX params BB */ 1530 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 1531 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1532 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 1533 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1534 /* configure vf MSIX for PF params AH*/ 1535 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 1536 #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF 1537 1538 /* OneView configuration parametres */ 1539 #define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 1540 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1541 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1542 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1543 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1544 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1545 #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1546 #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1547 #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1548 #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1549 1550 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 1551 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1552 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1553 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1554 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1555 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1556 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1557 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1558 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1559 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1560 #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1561 #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1562 1563 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 1564 #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1565 1566 #define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 1567 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1568 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1569 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1570 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1571 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1572 1573 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 1574 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1575 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1576 /* Not Installed*/ 1577 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 1578 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1579 /* installed but disabled by user/admin/OS */ 1580 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 1581 /* installed and active */ 1582 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 1583 1584 #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 1585 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1586 1587 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1588 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1589 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1590 1591 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 1592 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1593 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 1594 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1595 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 1596 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1597 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 1598 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1599 1600 #define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 1601 #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1602 #define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 1603 #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1604 #define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 1605 #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1606 #define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 1607 #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1608 1609 /* Resource Allocation params - Driver version support*/ 1610 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1611 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1612 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1613 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1614 1615 #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1616 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1617 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1618 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1619 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1620 1621 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1622 #define DRV_MB_PARAM_BIST_RC_PASSED 1 1623 #define DRV_MB_PARAM_BIST_RC_FAILED 2 1624 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1625 1626 #define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 1627 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1628 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 1629 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1630 1631 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 1632 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 1633 /* driver supports SmartLinQ parameter */ 1634 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 1635 /* driver supports EEE parameter */ 1636 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 1637 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 1638 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 1639 /* driver supports virtual link parameter */ 1640 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 1641 /* Driver attributes params */ 1642 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 1643 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF 1644 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 1645 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 1646 1647 u32 fw_mb_header; 1648 #define FW_MSG_CODE_MASK 0xffff0000 1649 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 1650 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1651 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1652 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1653 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1654 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1655 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1656 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1657 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1658 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1659 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1660 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1661 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1662 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1663 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1664 #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1665 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1666 #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1667 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1668 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1669 #define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 1670 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1671 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1672 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1673 #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1674 #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1675 #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1676 #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1677 #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1678 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1679 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1680 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1681 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1682 #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1683 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1684 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1685 #define FW_MSG_CODE_FLR_ACK 0x02000000 1686 #define FW_MSG_CODE_FLR_NACK 0x02100000 1687 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1688 #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1689 #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1690 1691 #define FW_MSG_CODE_NVM_OK 0x00010000 1692 #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1693 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1694 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1695 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1696 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1697 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1698 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1699 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1700 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1701 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1702 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1703 #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1704 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1705 #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1706 #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1707 #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1708 #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1709 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1710 /* MFW reject "mcp reset" command if one of the drivers is up */ 1711 #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 1712 #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1713 #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1714 #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1715 1716 #define FW_MSG_CODE_PHY_OK 0x00110000 1717 #define FW_MSG_CODE_PHY_ERROR 0x00120000 1718 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1719 #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1720 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1721 #define FW_MSG_CODE_OK 0x00160000 1722 #define FW_MSG_CODE_ERROR 0x00170000 1723 #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1724 #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1725 #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1726 #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1727 #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1728 #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1729 #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1730 #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1731 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1732 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1733 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1734 #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1735 #define FW_MSG_CODE_GPIO_OK 0x00160000 1736 #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1737 #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1738 #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1739 #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1740 #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1741 #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1742 #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1743 #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1744 #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1745 #define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1746 1747 /* mdump related response codes */ 1748 #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1749 #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1750 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1751 #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1752 #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1753 1754 1755 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 1756 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 1757 1758 #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 1759 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 1760 #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 1761 #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 1762 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 1763 1764 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1765 1766 #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 1767 #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 1768 1769 u32 fw_mb_param; 1770 /* Resource Allocation params - MFW version support */ 1771 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1772 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1773 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1774 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1775 1776 /* get MFW feature support response */ 1777 /* MFW supports SmartLinQ */ 1778 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 1779 /* MFW supports EEE */ 1780 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 1781 /* MFW supports DRV_LOAD Timeout */ 1782 #define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 1783 /* MFW supports virtual link */ 1784 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 1785 1786 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) 1787 1788 u32 drv_pulse_mb; 1789 #define DRV_PULSE_SEQ_MASK 0x00007fff 1790 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1791 /* 1792 * The system time is in the format of 1793 * (year-2001)*12*32 + month*32 + day. 1794 */ 1795 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1796 /* 1797 * Indicate to the firmware not to go into the 1798 * OS-absent when it is not getting driver pulse. 1799 * This is used for debugging as well for PXE(MBA). 1800 */ 1801 1802 u32 mcp_pulse_mb; 1803 #define MCP_PULSE_SEQ_MASK 0x00007fff 1804 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1805 /* Indicates to the driver not to assert due to lack 1806 * of MCP response 1807 */ 1808 #define MCP_EVENT_MASK 0xffff0000 1809 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1810 1811 /* The union data is used by the driver to pass parameters to the scratchpad. */ 1812 1813 union drv_union_data union_data; 1814 1815 }; 1816 1817 /* MFW - DRV MB */ 1818 /********************************************************************** 1819 * Description 1820 * Incremental Aggregative 1821 * 8-bit MFW counter per message 1822 * 8-bit ack-counter per message 1823 * Capabilities 1824 * Provides up to 256 aggregative message per type 1825 * Provides 4 message types in dword 1826 * Message type pointers to byte offset 1827 * Backward Compatibility by using sizeof for the counters. 1828 * No lock requires for 32bit messages 1829 * Limitations: 1830 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1831 * is required to prevent data corruption. 1832 **********************************************************************/ 1833 enum MFW_DRV_MSG_TYPE { 1834 MFW_DRV_MSG_LINK_CHANGE, 1835 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1836 MFW_DRV_MSG_VF_DISABLED, 1837 MFW_DRV_MSG_LLDP_DATA_UPDATED, 1838 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1839 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1840 MFW_DRV_MSG_ERROR_RECOVERY, 1841 MFW_DRV_MSG_BW_UPDATE, 1842 MFW_DRV_MSG_S_TAG_UPDATE, 1843 MFW_DRV_MSG_GET_LAN_STATS, 1844 MFW_DRV_MSG_GET_FCOE_STATS, 1845 MFW_DRV_MSG_GET_ISCSI_STATS, 1846 MFW_DRV_MSG_GET_RDMA_STATS, 1847 MFW_DRV_MSG_FAILURE_DETECTED, 1848 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1849 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1850 MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1851 MFW_DRV_MSG_GET_TLV_REQ, 1852 MFW_DRV_MSG_OEM_CFG_UPDATE, 1853 MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, 1854 MFW_DRV_MSG_MAX 1855 }; 1856 1857 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1858 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1859 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1860 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1861 1862 #ifdef BIG_ENDIAN /* Like MFW */ 1863 #define DRV_ACK_MSG(msg_p, msg_id) \ 1864 ((u8)((u8 *)msg_p)[msg_id]++;) 1865 #else 1866 #define DRV_ACK_MSG(msg_p, msg_id) \ 1867 ((u8)((u8 *)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++;) 1868 #endif 1869 1870 #define MFW_DRV_UPDATE(shmem_func, msg_id) \ 1871 ((u8)((u8 *)(MFW_MB_P(shmem_func)->msg))[msg_id]++;) 1872 1873 struct public_mfw_mb { 1874 u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1875 /* Incremented by the MFW */ 1876 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1877 /* Incremented by the driver */ 1878 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 1879 }; 1880 1881 /**************************************/ 1882 /* */ 1883 /* P U B L I C D A T A */ 1884 /* */ 1885 /**************************************/ 1886 enum public_sections { 1887 PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1888 PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1889 PUBLIC_GLOBAL, 1890 PUBLIC_PATH, 1891 PUBLIC_PORT, 1892 PUBLIC_FUNC, 1893 PUBLIC_MAX_SECTIONS 1894 }; 1895 1896 struct drv_ver_info_stc { 1897 u32 ver; 1898 u8 name[32]; 1899 }; 1900 1901 /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1902 * Please make sure data does not exceed this size. 1903 */ 1904 #define NUM_RUNTIME_DWORDS 16 1905 struct drv_init_hw_stc { 1906 u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1907 u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1908 }; 1909 1910 struct mcp_public_data { 1911 /* The sections fields is an array */ 1912 u32 num_sections; 1913 offsize_t sections[PUBLIC_MAX_SECTIONS]; 1914 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1915 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1916 struct public_global global; 1917 struct public_path path[MCP_GLOB_PATH_MAX]; 1918 struct public_port port[MCP_GLOB_PORT_MAX]; 1919 struct public_func func[MCP_GLOB_FUNC_MAX]; 1920 }; 1921 1922 #define I2C_TRANSCEIVER_ADDR 0xa0 1923 #define MAX_I2C_TRANSACTION_SIZE 16 1924 #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1925 1926 #endif /* MCP_PUBLIC_H */ 1927